stpmic1.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. * Author: Christophe Kerello <christophe.kerello@st.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <linux/delay.h>
  10. #include <power/pmic.h>
  11. #include <power/regulator.h>
  12. #include <power/stpmic1.h>
  13. struct stpmic1_range {
  14. int min_uv;
  15. int min_sel;
  16. int max_sel;
  17. int step;
  18. };
  19. struct stpmic1_output {
  20. const struct stpmic1_range *ranges;
  21. int nbranges;
  22. };
  23. #define STPMIC1_MODE(_id, _val, _name) { \
  24. .id = _id, \
  25. .register_value = _val, \
  26. .name = _name, \
  27. }
  28. #define STPMIC1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
  29. .min_uv = _min_uv, \
  30. .min_sel = _min_sel, \
  31. .max_sel = _max_sel, \
  32. .step = _step, \
  33. }
  34. #define STPMIC1_OUTPUT(_ranges, _nbranges) { \
  35. .ranges = _ranges, \
  36. .nbranges = _nbranges, \
  37. }
  38. static int stpmic1_output_find_uv(int sel,
  39. const struct stpmic1_output *output)
  40. {
  41. const struct stpmic1_range *range;
  42. int i;
  43. for (i = 0, range = output->ranges;
  44. i < output->nbranges; i++, range++) {
  45. if (sel >= range->min_sel && sel <= range->max_sel)
  46. return range->min_uv +
  47. (sel - range->min_sel) * range->step;
  48. }
  49. return -EINVAL;
  50. }
  51. static int stpmic1_output_find_sel(int uv,
  52. const struct stpmic1_output *output)
  53. {
  54. const struct stpmic1_range *range;
  55. int i;
  56. for (i = 0, range = output->ranges;
  57. i < output->nbranges; i++, range++) {
  58. if (uv == range->min_uv && !range->step)
  59. return range->min_sel;
  60. if (uv >= range->min_uv &&
  61. uv <= range->min_uv +
  62. (range->max_sel - range->min_sel) * range->step)
  63. return range->min_sel +
  64. (uv - range->min_uv) / range->step;
  65. }
  66. return -EINVAL;
  67. }
  68. /*
  69. * BUCK regulators
  70. */
  71. static const struct stpmic1_range buck1_ranges[] = {
  72. STPMIC1_RANGE(725000, 0, 4, 0),
  73. STPMIC1_RANGE(725000, 5, 36, 25000),
  74. STPMIC1_RANGE(1500000, 37, 63, 0),
  75. };
  76. static const struct stpmic1_range buck2_ranges[] = {
  77. STPMIC1_RANGE(1000000, 0, 17, 0),
  78. STPMIC1_RANGE(1050000, 18, 19, 0),
  79. STPMIC1_RANGE(1100000, 20, 21, 0),
  80. STPMIC1_RANGE(1150000, 22, 23, 0),
  81. STPMIC1_RANGE(1200000, 24, 25, 0),
  82. STPMIC1_RANGE(1250000, 26, 27, 0),
  83. STPMIC1_RANGE(1300000, 28, 29, 0),
  84. STPMIC1_RANGE(1350000, 30, 31, 0),
  85. STPMIC1_RANGE(1400000, 32, 33, 0),
  86. STPMIC1_RANGE(1450000, 34, 35, 0),
  87. STPMIC1_RANGE(1500000, 36, 63, 0),
  88. };
  89. static const struct stpmic1_range buck3_ranges[] = {
  90. STPMIC1_RANGE(1000000, 0, 19, 0),
  91. STPMIC1_RANGE(1100000, 20, 23, 0),
  92. STPMIC1_RANGE(1200000, 24, 27, 0),
  93. STPMIC1_RANGE(1300000, 28, 31, 0),
  94. STPMIC1_RANGE(1400000, 32, 35, 0),
  95. STPMIC1_RANGE(1500000, 36, 55, 100000),
  96. STPMIC1_RANGE(3400000, 56, 63, 0),
  97. };
  98. static const struct stpmic1_range buck4_ranges[] = {
  99. STPMIC1_RANGE(600000, 0, 27, 25000),
  100. STPMIC1_RANGE(1300000, 28, 29, 0),
  101. STPMIC1_RANGE(1350000, 30, 31, 0),
  102. STPMIC1_RANGE(1400000, 32, 33, 0),
  103. STPMIC1_RANGE(1450000, 34, 35, 0),
  104. STPMIC1_RANGE(1500000, 36, 60, 100000),
  105. STPMIC1_RANGE(3900000, 61, 63, 0),
  106. };
  107. /* BUCK: 1,2,3,4 - voltage ranges */
  108. static const struct stpmic1_output buck_voltage_range[] = {
  109. STPMIC1_OUTPUT(buck1_ranges, ARRAY_SIZE(buck1_ranges)),
  110. STPMIC1_OUTPUT(buck2_ranges, ARRAY_SIZE(buck2_ranges)),
  111. STPMIC1_OUTPUT(buck3_ranges, ARRAY_SIZE(buck3_ranges)),
  112. STPMIC1_OUTPUT(buck4_ranges, ARRAY_SIZE(buck4_ranges)),
  113. };
  114. /* BUCK modes */
  115. static const struct dm_regulator_mode buck_modes[] = {
  116. STPMIC1_MODE(STPMIC1_PREG_MODE_HP, STPMIC1_PREG_MODE_HP, "HP"),
  117. STPMIC1_MODE(STPMIC1_PREG_MODE_LP, STPMIC1_PREG_MODE_LP, "LP"),
  118. };
  119. static int stpmic1_buck_get_uv(struct udevice *dev, int buck)
  120. {
  121. int sel;
  122. sel = pmic_reg_read(dev, STPMIC1_BUCKX_MAIN_CR(buck));
  123. if (sel < 0)
  124. return sel;
  125. sel &= STPMIC1_BUCK_VOUT_MASK;
  126. sel >>= STPMIC1_BUCK_VOUT_SHIFT;
  127. return stpmic1_output_find_uv(sel, &buck_voltage_range[buck]);
  128. }
  129. static int stpmic1_buck_get_value(struct udevice *dev)
  130. {
  131. return stpmic1_buck_get_uv(dev->parent, dev->driver_data - 1);
  132. }
  133. static int stpmic1_buck_set_value(struct udevice *dev, int uv)
  134. {
  135. int sel, buck = dev->driver_data - 1;
  136. sel = stpmic1_output_find_sel(uv, &buck_voltage_range[buck]);
  137. if (sel < 0)
  138. return sel;
  139. return pmic_clrsetbits(dev->parent,
  140. STPMIC1_BUCKX_MAIN_CR(buck),
  141. STPMIC1_BUCK_VOUT_MASK,
  142. sel << STPMIC1_BUCK_VOUT_SHIFT);
  143. }
  144. static int stpmic1_buck_get_enable(struct udevice *dev)
  145. {
  146. int ret;
  147. ret = pmic_reg_read(dev->parent,
  148. STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1));
  149. if (ret < 0)
  150. return false;
  151. return ret & STPMIC1_BUCK_ENA ? true : false;
  152. }
  153. static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
  154. {
  155. struct dm_regulator_uclass_plat *uc_pdata;
  156. int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  157. STPMIC1_DEFAULT_STOP_DELAY_MS;
  158. int ret, uv;
  159. /* if regulator is already in the wanted state, nothing to do */
  160. if (stpmic1_buck_get_enable(dev) == enable)
  161. return 0;
  162. if (enable) {
  163. uc_pdata = dev_get_uclass_plat(dev);
  164. uv = stpmic1_buck_get_value(dev);
  165. if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV)
  166. stpmic1_buck_set_value(dev, uc_pdata->min_uV);
  167. }
  168. ret = pmic_clrsetbits(dev->parent,
  169. STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1),
  170. STPMIC1_BUCK_ENA, enable ? STPMIC1_BUCK_ENA : 0);
  171. mdelay(delay);
  172. return ret;
  173. }
  174. static int stpmic1_buck_get_mode(struct udevice *dev)
  175. {
  176. int ret;
  177. ret = pmic_reg_read(dev->parent,
  178. STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1));
  179. if (ret < 0)
  180. return ret;
  181. return ret & STPMIC1_BUCK_PREG_MODE ? STPMIC1_PREG_MODE_LP :
  182. STPMIC1_PREG_MODE_HP;
  183. }
  184. static int stpmic1_buck_set_mode(struct udevice *dev, int mode)
  185. {
  186. return pmic_clrsetbits(dev->parent,
  187. STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1),
  188. STPMIC1_BUCK_PREG_MODE,
  189. mode ? STPMIC1_BUCK_PREG_MODE : 0);
  190. }
  191. static int stpmic1_buck_probe(struct udevice *dev)
  192. {
  193. struct dm_regulator_uclass_plat *uc_pdata;
  194. if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_BUCK)
  195. return -EINVAL;
  196. uc_pdata = dev_get_uclass_plat(dev);
  197. uc_pdata->type = REGULATOR_TYPE_BUCK;
  198. uc_pdata->mode = (struct dm_regulator_mode *)buck_modes;
  199. uc_pdata->mode_count = ARRAY_SIZE(buck_modes);
  200. return 0;
  201. }
  202. static const struct dm_regulator_ops stpmic1_buck_ops = {
  203. .get_value = stpmic1_buck_get_value,
  204. .set_value = stpmic1_buck_set_value,
  205. .get_enable = stpmic1_buck_get_enable,
  206. .set_enable = stpmic1_buck_set_enable,
  207. .get_mode = stpmic1_buck_get_mode,
  208. .set_mode = stpmic1_buck_set_mode,
  209. };
  210. U_BOOT_DRIVER(stpmic1_buck) = {
  211. .name = "stpmic1_buck",
  212. .id = UCLASS_REGULATOR,
  213. .ops = &stpmic1_buck_ops,
  214. .probe = stpmic1_buck_probe,
  215. };
  216. /*
  217. * LDO regulators
  218. */
  219. static const struct stpmic1_range ldo12_ranges[] = {
  220. STPMIC1_RANGE(1700000, 0, 7, 0),
  221. STPMIC1_RANGE(1700000, 8, 24, 100000),
  222. STPMIC1_RANGE(3300000, 25, 31, 0),
  223. };
  224. static const struct stpmic1_range ldo3_ranges[] = {
  225. STPMIC1_RANGE(1700000, 0, 7, 0),
  226. STPMIC1_RANGE(1700000, 8, 24, 100000),
  227. STPMIC1_RANGE(3300000, 25, 30, 0),
  228. /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */
  229. };
  230. static const struct stpmic1_range ldo5_ranges[] = {
  231. STPMIC1_RANGE(1700000, 0, 7, 0),
  232. STPMIC1_RANGE(1700000, 8, 30, 100000),
  233. STPMIC1_RANGE(3900000, 31, 31, 0),
  234. };
  235. static const struct stpmic1_range ldo6_ranges[] = {
  236. STPMIC1_RANGE(900000, 0, 24, 100000),
  237. STPMIC1_RANGE(3300000, 25, 31, 0),
  238. };
  239. /* LDO: 1,2,3,4,5,6 - voltage ranges */
  240. static const struct stpmic1_output ldo_voltage_range[] = {
  241. STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
  242. STPMIC1_OUTPUT(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
  243. STPMIC1_OUTPUT(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)),
  244. STPMIC1_OUTPUT(NULL, 0),
  245. STPMIC1_OUTPUT(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)),
  246. STPMIC1_OUTPUT(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)),
  247. };
  248. /* LDO modes */
  249. static const struct dm_regulator_mode ldo_modes[] = {
  250. STPMIC1_MODE(STPMIC1_LDO_MODE_NORMAL,
  251. STPMIC1_LDO_MODE_NORMAL, "NORMAL"),
  252. STPMIC1_MODE(STPMIC1_LDO_MODE_BYPASS,
  253. STPMIC1_LDO_MODE_BYPASS, "BYPASS"),
  254. STPMIC1_MODE(STPMIC1_LDO_MODE_SINK_SOURCE,
  255. STPMIC1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"),
  256. };
  257. static int stpmic1_ldo_get_value(struct udevice *dev)
  258. {
  259. int sel, ldo = dev->driver_data - 1;
  260. sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
  261. if (sel < 0)
  262. return sel;
  263. /* ldo4 => 3,3V */
  264. if (ldo == STPMIC1_LDO4)
  265. return STPMIC1_LDO4_UV;
  266. sel &= STPMIC1_LDO12356_VOUT_MASK;
  267. sel >>= STPMIC1_LDO12356_VOUT_SHIFT;
  268. /* ldo3, sel = 31 => BUCK2/2 */
  269. if (ldo == STPMIC1_LDO3 && sel == STPMIC1_LDO3_DDR_SEL)
  270. return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2;
  271. return stpmic1_output_find_uv(sel, &ldo_voltage_range[ldo]);
  272. }
  273. static int stpmic1_ldo_set_value(struct udevice *dev, int uv)
  274. {
  275. int sel, ldo = dev->driver_data - 1;
  276. /* ldo4 => not possible */
  277. if (ldo == STPMIC1_LDO4)
  278. return -EINVAL;
  279. sel = stpmic1_output_find_sel(uv, &ldo_voltage_range[ldo]);
  280. if (sel < 0)
  281. return sel;
  282. return pmic_clrsetbits(dev->parent,
  283. STPMIC1_LDOX_MAIN_CR(ldo),
  284. STPMIC1_LDO12356_VOUT_MASK,
  285. sel << STPMIC1_LDO12356_VOUT_SHIFT);
  286. }
  287. static int stpmic1_ldo_get_enable(struct udevice *dev)
  288. {
  289. int ret;
  290. ret = pmic_reg_read(dev->parent,
  291. STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1));
  292. if (ret < 0)
  293. return false;
  294. return ret & STPMIC1_LDO_ENA ? true : false;
  295. }
  296. static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
  297. {
  298. struct dm_regulator_uclass_plat *uc_pdata;
  299. int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  300. STPMIC1_DEFAULT_STOP_DELAY_MS;
  301. int ret, uv;
  302. /* if regulator is already in the wanted state, nothing to do */
  303. if (stpmic1_ldo_get_enable(dev) == enable)
  304. return 0;
  305. if (enable) {
  306. uc_pdata = dev_get_uclass_plat(dev);
  307. uv = stpmic1_ldo_get_value(dev);
  308. if (uv < uc_pdata->min_uV || uv > uc_pdata->max_uV)
  309. stpmic1_ldo_set_value(dev, uc_pdata->min_uV);
  310. }
  311. ret = pmic_clrsetbits(dev->parent,
  312. STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1),
  313. STPMIC1_LDO_ENA, enable ? STPMIC1_LDO_ENA : 0);
  314. mdelay(delay);
  315. return ret;
  316. }
  317. static int stpmic1_ldo_get_mode(struct udevice *dev)
  318. {
  319. int ret, ldo = dev->driver_data - 1;
  320. if (ldo != STPMIC1_LDO3)
  321. return -EINVAL;
  322. ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
  323. if (ret < 0)
  324. return ret;
  325. if (ret & STPMIC1_LDO3_MODE)
  326. return STPMIC1_LDO_MODE_BYPASS;
  327. ret &= STPMIC1_LDO12356_VOUT_MASK;
  328. ret >>= STPMIC1_LDO12356_VOUT_SHIFT;
  329. return ret == STPMIC1_LDO3_DDR_SEL ? STPMIC1_LDO_MODE_SINK_SOURCE :
  330. STPMIC1_LDO_MODE_NORMAL;
  331. }
  332. static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
  333. {
  334. int ret, ldo = dev->driver_data - 1;
  335. if (ldo != STPMIC1_LDO3)
  336. return -EINVAL;
  337. ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
  338. if (ret < 0)
  339. return ret;
  340. switch (mode) {
  341. case STPMIC1_LDO_MODE_SINK_SOURCE:
  342. ret &= ~STPMIC1_LDO12356_VOUT_MASK;
  343. ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT;
  344. /* fallthrough */
  345. case STPMIC1_LDO_MODE_NORMAL:
  346. ret &= ~STPMIC1_LDO3_MODE;
  347. break;
  348. case STPMIC1_LDO_MODE_BYPASS:
  349. ret |= STPMIC1_LDO3_MODE;
  350. break;
  351. }
  352. return pmic_reg_write(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo), ret);
  353. }
  354. static int stpmic1_ldo_probe(struct udevice *dev)
  355. {
  356. struct dm_regulator_uclass_plat *uc_pdata;
  357. if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_LDO)
  358. return -EINVAL;
  359. uc_pdata = dev_get_uclass_plat(dev);
  360. uc_pdata->type = REGULATOR_TYPE_LDO;
  361. if (dev->driver_data - 1 == STPMIC1_LDO3) {
  362. uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes;
  363. uc_pdata->mode_count = ARRAY_SIZE(ldo_modes);
  364. } else {
  365. uc_pdata->mode_count = 0;
  366. }
  367. return 0;
  368. }
  369. static const struct dm_regulator_ops stpmic1_ldo_ops = {
  370. .get_value = stpmic1_ldo_get_value,
  371. .set_value = stpmic1_ldo_set_value,
  372. .get_enable = stpmic1_ldo_get_enable,
  373. .set_enable = stpmic1_ldo_set_enable,
  374. .get_mode = stpmic1_ldo_get_mode,
  375. .set_mode = stpmic1_ldo_set_mode,
  376. };
  377. U_BOOT_DRIVER(stpmic1_ldo) = {
  378. .name = "stpmic1_ldo",
  379. .id = UCLASS_REGULATOR,
  380. .ops = &stpmic1_ldo_ops,
  381. .probe = stpmic1_ldo_probe,
  382. };
  383. /*
  384. * VREF DDR regulator
  385. */
  386. static int stpmic1_vref_ddr_get_value(struct udevice *dev)
  387. {
  388. /* BUCK2/2 */
  389. return stpmic1_buck_get_uv(dev->parent, STPMIC1_BUCK2) / 2;
  390. }
  391. static int stpmic1_vref_ddr_get_enable(struct udevice *dev)
  392. {
  393. int ret;
  394. ret = pmic_reg_read(dev->parent, STPMIC1_REFDDR_MAIN_CR);
  395. if (ret < 0)
  396. return false;
  397. return ret & STPMIC1_VREF_ENA ? true : false;
  398. }
  399. static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable)
  400. {
  401. int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  402. STPMIC1_DEFAULT_STOP_DELAY_MS;
  403. int ret;
  404. /* if regulator is already in the wanted state, nothing to do */
  405. if (stpmic1_vref_ddr_get_enable(dev) == enable)
  406. return 0;
  407. ret = pmic_clrsetbits(dev->parent, STPMIC1_REFDDR_MAIN_CR,
  408. STPMIC1_VREF_ENA, enable ? STPMIC1_VREF_ENA : 0);
  409. mdelay(delay);
  410. return ret;
  411. }
  412. static int stpmic1_vref_ddr_probe(struct udevice *dev)
  413. {
  414. struct dm_regulator_uclass_plat *uc_pdata;
  415. uc_pdata = dev_get_uclass_plat(dev);
  416. uc_pdata->type = REGULATOR_TYPE_FIXED;
  417. uc_pdata->mode_count = 0;
  418. return 0;
  419. }
  420. static const struct dm_regulator_ops stpmic1_vref_ddr_ops = {
  421. .get_value = stpmic1_vref_ddr_get_value,
  422. .get_enable = stpmic1_vref_ddr_get_enable,
  423. .set_enable = stpmic1_vref_ddr_set_enable,
  424. };
  425. U_BOOT_DRIVER(stpmic1_vref_ddr) = {
  426. .name = "stpmic1_vref_ddr",
  427. .id = UCLASS_REGULATOR,
  428. .ops = &stpmic1_vref_ddr_ops,
  429. .probe = stpmic1_vref_ddr_probe,
  430. };
  431. /*
  432. * BOOST regulator
  433. */
  434. static int stpmic1_boost_get_enable(struct udevice *dev)
  435. {
  436. int ret;
  437. ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
  438. if (ret < 0)
  439. return false;
  440. return ret & STPMIC1_BST_ON ? true : false;
  441. }
  442. static int stpmic1_boost_set_enable(struct udevice *dev, bool enable)
  443. {
  444. int ret;
  445. ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
  446. if (ret < 0)
  447. return ret;
  448. if (!enable && ret & STPMIC1_PWR_SW_ON)
  449. return -EINVAL;
  450. /* if regulator is already in the wanted state, nothing to do */
  451. if (!!(ret & STPMIC1_BST_ON) == enable)
  452. return 0;
  453. ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
  454. STPMIC1_BST_ON,
  455. enable ? STPMIC1_BST_ON : 0);
  456. if (enable)
  457. mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
  458. return ret;
  459. }
  460. static int stpmic1_boost_probe(struct udevice *dev)
  461. {
  462. struct dm_regulator_uclass_plat *uc_pdata;
  463. uc_pdata = dev_get_uclass_plat(dev);
  464. uc_pdata->type = REGULATOR_TYPE_FIXED;
  465. uc_pdata->mode_count = 0;
  466. return 0;
  467. }
  468. static const struct dm_regulator_ops stpmic1_boost_ops = {
  469. .get_enable = stpmic1_boost_get_enable,
  470. .set_enable = stpmic1_boost_set_enable,
  471. };
  472. U_BOOT_DRIVER(stpmic1_boost) = {
  473. .name = "stpmic1_boost",
  474. .id = UCLASS_REGULATOR,
  475. .ops = &stpmic1_boost_ops,
  476. .probe = stpmic1_boost_probe,
  477. };
  478. /*
  479. * USB power switch
  480. */
  481. static int stpmic1_pwr_sw_get_enable(struct udevice *dev)
  482. {
  483. uint mask = 1 << dev->driver_data;
  484. int ret;
  485. ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
  486. if (ret < 0)
  487. return false;
  488. return ret & mask ? true : false;
  489. }
  490. static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable)
  491. {
  492. uint mask = 1 << dev->driver_data;
  493. int delay = enable ? STPMIC1_DEFAULT_START_UP_DELAY_MS :
  494. STPMIC1_DEFAULT_STOP_DELAY_MS;
  495. int ret;
  496. ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
  497. if (ret < 0)
  498. return ret;
  499. /* if regulator is already in the wanted state, nothing to do */
  500. if (!!(ret & mask) == enable)
  501. return 0;
  502. /* Boost management */
  503. if (enable && !(ret & STPMIC1_BST_ON)) {
  504. pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
  505. STPMIC1_BST_ON, STPMIC1_BST_ON);
  506. mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
  507. } else if (!enable && ret & STPMIC1_BST_ON &&
  508. (ret & STPMIC1_PWR_SW_ON) != STPMIC1_PWR_SW_ON) {
  509. pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
  510. STPMIC1_BST_ON, 0);
  511. }
  512. ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
  513. mask, enable ? mask : 0);
  514. mdelay(delay);
  515. return ret;
  516. }
  517. static int stpmic1_pwr_sw_probe(struct udevice *dev)
  518. {
  519. struct dm_regulator_uclass_plat *uc_pdata;
  520. if (!dev->driver_data || dev->driver_data > STPMIC1_MAX_PWR_SW)
  521. return -EINVAL;
  522. uc_pdata = dev_get_uclass_plat(dev);
  523. uc_pdata->type = REGULATOR_TYPE_FIXED;
  524. uc_pdata->mode_count = 0;
  525. return 0;
  526. }
  527. static const struct dm_regulator_ops stpmic1_pwr_sw_ops = {
  528. .get_enable = stpmic1_pwr_sw_get_enable,
  529. .set_enable = stpmic1_pwr_sw_set_enable,
  530. };
  531. U_BOOT_DRIVER(stpmic1_pwr_sw) = {
  532. .name = "stpmic1_pwr_sw",
  533. .id = UCLASS_REGULATOR,
  534. .ops = &stpmic1_pwr_sw_ops,
  535. .probe = stpmic1_pwr_sw_probe,
  536. };