s5m8767.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <fdtdec.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <i2c.h>
  10. #include <power/pmic.h>
  11. #include <power/regulator.h>
  12. #include <power/s5m8767.h>
  13. static const struct sec_voltage_desc buck_v1 = {
  14. .max = 2225000,
  15. .min = 650000,
  16. .step = 6250,
  17. };
  18. static const struct sec_voltage_desc buck_v2 = {
  19. .max = 1600000,
  20. .min = 600000,
  21. .step = 6250,
  22. };
  23. static const struct sec_voltage_desc buck_v3 = {
  24. .max = 3000000,
  25. .min = 750000,
  26. .step = 12500,
  27. };
  28. static const struct sec_voltage_desc ldo_v1 = {
  29. .max = 3950000,
  30. .min = 800000,
  31. .step = 50000,
  32. };
  33. static const struct sec_voltage_desc ldo_v2 = {
  34. .max = 2375000,
  35. .min = 800000,
  36. .step = 25000,
  37. };
  38. static const struct s5m8767_para buck_param[] = {
  39. /*
  40. * | voltage ----| | enable -| voltage
  41. * regnum addr bpos mask addr on desc
  42. */
  43. {S5M8767_BUCK1, 0x33, 0x0, 0xff, 0x32, 0x3, &buck_v1},
  44. {S5M8767_BUCK2, 0x35, 0x0, 0xff, 0x34, 0x1, &buck_v2},
  45. {S5M8767_BUCK3, 0x3e, 0x0, 0xff, 0x3d, 0x1, &buck_v2},
  46. {S5M8767_BUCK4, 0x47, 0x0, 0xff, 0x46, 0x1, &buck_v2},
  47. {S5M8767_BUCK5, 0x50, 0x0, 0xff, 0x4f, 0x3, &buck_v1},
  48. {S5M8767_BUCK6, 0x55, 0x0, 0xff, 0x54, 0x3, &buck_v1},
  49. {S5M8767_BUCK7, 0x57, 0x0, 0xff, 0x56, 0x3, &buck_v3},
  50. {S5M8767_BUCK8, 0x59, 0x0, 0xff, 0x58, 0x3, &buck_v3},
  51. {S5M8767_BUCK9, 0x5b, 0x0, 0xff, 0x5a, 0x3, &buck_v3},
  52. };
  53. static const struct s5m8767_para ldo_param[] = {
  54. {S5M8767_LDO1, 0x5c, 0x0, 0x3f, 0x5c, 0x3, &ldo_v2},
  55. {S5M8767_LDO2, 0x5d, 0x0, 0x3f, 0x5d, 0x1, &ldo_v2},
  56. {S5M8767_LDO3, 0x61, 0x0, 0x3f, 0x61, 0x3, &ldo_v1},
  57. {S5M8767_LDO4, 0x62, 0x0, 0x3f, 0x62, 0x3, &ldo_v1},
  58. {S5M8767_LDO5, 0x63, 0x0, 0x3f, 0x63, 0x3, &ldo_v1},
  59. {S5M8767_LDO6, 0x64, 0x0, 0x3f, 0x64, 0x1, &ldo_v2},
  60. {S5M8767_LDO7, 0x65, 0x0, 0x3f, 0x65, 0x1, &ldo_v2},
  61. {S5M8767_LDO8, 0x66, 0x0, 0x3f, 0x66, 0x1, &ldo_v2},
  62. {S5M8767_LDO9, 0x67, 0x0, 0x3f, 0x67, 0x3, &ldo_v1},
  63. {S5M8767_LDO10, 0x68, 0x0, 0x3f, 0x68, 0x1, &ldo_v1},
  64. {S5M8767_LDO11, 0x69, 0x0, 0x3f, 0x69, 0x1, &ldo_v1},
  65. {S5M8767_LDO12, 0x6a, 0x0, 0x3f, 0x6a, 0x1, &ldo_v1},
  66. {S5M8767_LDO13, 0x6b, 0x0, 0x3f, 0x6b, 0x3, &ldo_v1},
  67. {S5M8767_LDO14, 0x6c, 0x0, 0x3f, 0x6c, 0x1, &ldo_v1},
  68. {S5M8767_LDO15, 0x6d, 0x0, 0x3f, 0x6d, 0x1, &ldo_v2},
  69. {S5M8767_LDO16, 0x6e, 0x0, 0x3f, 0x6e, 0x1, &ldo_v1},
  70. {S5M8767_LDO17, 0x6f, 0x0, 0x3f, 0x6f, 0x3, &ldo_v1},
  71. {S5M8767_LDO18, 0x70, 0x0, 0x3f, 0x70, 0x3, &ldo_v1},
  72. {S5M8767_LDO19, 0x71, 0x0, 0x3f, 0x71, 0x3, &ldo_v1},
  73. {S5M8767_LDO20, 0x72, 0x0, 0x3f, 0x72, 0x3, &ldo_v1},
  74. {S5M8767_LDO21, 0x73, 0x0, 0x3f, 0x73, 0x3, &ldo_v1},
  75. {S5M8767_LDO22, 0x74, 0x0, 0x3f, 0x74, 0x3, &ldo_v1},
  76. {S5M8767_LDO23, 0x75, 0x0, 0x3f, 0x75, 0x3, &ldo_v1},
  77. {S5M8767_LDO24, 0x76, 0x0, 0x3f, 0x76, 0x3, &ldo_v1},
  78. {S5M8767_LDO25, 0x77, 0x0, 0x3f, 0x77, 0x3, &ldo_v1},
  79. {S5M8767_LDO26, 0x78, 0x0, 0x3f, 0x78, 0x3, &ldo_v1},
  80. {S5M8767_LDO27, 0x79, 0x0, 0x3f, 0x79, 0x3, &ldo_v1},
  81. {S5M8767_LDO28, 0x7a, 0x0, 0x3f, 0x7a, 0x3, &ldo_v1},
  82. };
  83. enum {
  84. ENABLE_SHIFT = 6,
  85. ENABLE_MASK = 3,
  86. };
  87. static int reg_get_value(struct udevice *dev, const struct s5m8767_para *param)
  88. {
  89. const struct sec_voltage_desc *desc;
  90. int ret, uv, val;
  91. ret = pmic_reg_read(dev->parent, param->vol_addr);
  92. if (ret < 0)
  93. return ret;
  94. desc = param->vol;
  95. val = (ret >> param->vol_bitpos) & param->vol_bitmask;
  96. uv = desc->min + val * desc->step;
  97. return uv;
  98. }
  99. static int reg_set_value(struct udevice *dev, const struct s5m8767_para *param,
  100. int uv)
  101. {
  102. const struct sec_voltage_desc *desc;
  103. int ret, val;
  104. desc = param->vol;
  105. if (uv < desc->min || uv > desc->max)
  106. return -EINVAL;
  107. val = (uv - desc->min) / desc->step;
  108. val = (val & param->vol_bitmask) << param->vol_bitpos;
  109. ret = pmic_clrsetbits(dev->parent, param->vol_addr,
  110. param->vol_bitmask << param->vol_bitpos,
  111. val);
  112. return ret;
  113. }
  114. static int s5m8767_ldo_probe(struct udevice *dev)
  115. {
  116. struct dm_regulator_uclass_plat *uc_pdata;
  117. uc_pdata = dev_get_uclass_plat(dev);
  118. uc_pdata->type = REGULATOR_TYPE_LDO;
  119. uc_pdata->mode_count = 0;
  120. return 0;
  121. }
  122. static int ldo_get_value(struct udevice *dev)
  123. {
  124. int ldo = dev->driver_data;
  125. return reg_get_value(dev, &ldo_param[ldo]);
  126. }
  127. static int ldo_set_value(struct udevice *dev, int uv)
  128. {
  129. int ldo = dev->driver_data;
  130. return reg_set_value(dev, &ldo_param[ldo], uv);
  131. }
  132. static int reg_get_enable(struct udevice *dev, const struct s5m8767_para *param)
  133. {
  134. bool enable;
  135. int ret;
  136. ret = pmic_reg_read(dev->parent, param->reg_enaddr);
  137. if (ret < 0)
  138. return ret;
  139. enable = (ret >> ENABLE_SHIFT) & ENABLE_MASK;
  140. return enable;
  141. }
  142. static int reg_set_enable(struct udevice *dev, const struct s5m8767_para *param,
  143. bool enable)
  144. {
  145. int ret;
  146. ret = pmic_reg_read(dev->parent, param->reg_enaddr);
  147. if (ret < 0)
  148. return ret;
  149. ret = pmic_clrsetbits(dev->parent, param->reg_enaddr,
  150. ENABLE_MASK << ENABLE_SHIFT,
  151. enable ? param->reg_enbiton << ENABLE_SHIFT : 0);
  152. return ret;
  153. }
  154. static int ldo_get_enable(struct udevice *dev)
  155. {
  156. int ldo = dev->driver_data;
  157. return reg_get_enable(dev, &ldo_param[ldo]);
  158. }
  159. static int ldo_set_enable(struct udevice *dev, bool enable)
  160. {
  161. int ldo = dev->driver_data;
  162. return reg_set_enable(dev, &ldo_param[ldo], enable);
  163. }
  164. static int s5m8767_buck_probe(struct udevice *dev)
  165. {
  166. struct dm_regulator_uclass_plat *uc_pdata;
  167. uc_pdata = dev_get_uclass_plat(dev);
  168. uc_pdata->type = REGULATOR_TYPE_BUCK;
  169. uc_pdata->mode_count = 0;
  170. return 0;
  171. }
  172. static int buck_get_value(struct udevice *dev)
  173. {
  174. int buck = dev->driver_data;
  175. return reg_get_value(dev, &buck_param[buck]);
  176. }
  177. static int buck_set_value(struct udevice *dev, int uv)
  178. {
  179. int buck = dev->driver_data;
  180. return reg_set_value(dev, &buck_param[buck], uv);
  181. }
  182. static int buck_get_enable(struct udevice *dev)
  183. {
  184. int buck = dev->driver_data;
  185. return reg_get_enable(dev, &buck_param[buck]);
  186. }
  187. static int buck_set_enable(struct udevice *dev, bool enable)
  188. {
  189. int buck = dev->driver_data;
  190. return reg_set_enable(dev, &buck_param[buck], enable);
  191. }
  192. static const struct dm_regulator_ops s5m8767_ldo_ops = {
  193. .get_value = ldo_get_value,
  194. .set_value = ldo_set_value,
  195. .get_enable = ldo_get_enable,
  196. .set_enable = ldo_set_enable,
  197. };
  198. U_BOOT_DRIVER(s5m8767_ldo) = {
  199. .name = S5M8767_LDO_DRIVER,
  200. .id = UCLASS_REGULATOR,
  201. .ops = &s5m8767_ldo_ops,
  202. .probe = s5m8767_ldo_probe,
  203. };
  204. static const struct dm_regulator_ops s5m8767_buck_ops = {
  205. .get_value = buck_get_value,
  206. .set_value = buck_set_value,
  207. .get_enable = buck_get_enable,
  208. .set_enable = buck_set_enable,
  209. };
  210. U_BOOT_DRIVER(s5m8767_buck) = {
  211. .name = S5M8767_BUCK_DRIVER,
  212. .id = UCLASS_REGULATOR,
  213. .ops = &s5m8767_buck_ops,
  214. .probe = s5m8767_buck_probe,
  215. };