rk8xx.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. *
  6. * Based on Rockchip's drivers/power/pmic/pmic_rk808.c:
  7. * Copyright (C) 2012 rockchips
  8. * zyw <zyw@rock-chips.com>
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <power/rk8xx_pmic.h>
  15. #include <power/pmic.h>
  16. #include <power/regulator.h>
  17. #ifndef CONFIG_SPL_BUILD
  18. #define ENABLE_DRIVER
  19. #endif
  20. /* Not used or exisit register and configure */
  21. #define NA 0xff
  22. /* Field Definitions */
  23. #define RK808_BUCK_VSEL_MASK 0x3f
  24. #define RK808_BUCK4_VSEL_MASK 0xf
  25. #define RK808_LDO_VSEL_MASK 0x1f
  26. /* RK809 BUCK5 */
  27. #define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1)
  28. #define RK809_BUCK5_VSEL_MASK 0x07
  29. /* RK817 BUCK */
  30. #define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * ((n) - 1))
  31. #define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * ((n) - 1))
  32. #define RK817_BUCK_VSEL_MASK 0x7f
  33. #define RK817_BUCK_CONFIG(i) (0xba + (i) * 3)
  34. /* RK817 LDO */
  35. #define RK817_LDO_ON_VSEL(n) (0xcc + 2 * ((n) - 1))
  36. #define RK817_LDO_SLP_VSEL(n) (0xcd + 2 * ((n) - 1))
  37. #define RK817_LDO_VSEL_MASK 0x7f
  38. /* RK817 ENABLE */
  39. #define RK817_POWER_EN(n) (0xb1 + (n))
  40. #define RK817_POWER_SLP_EN(n) (0xb5 + (n))
  41. #define RK818_BUCK_VSEL_MASK 0x3f
  42. #define RK818_BUCK4_VSEL_MASK 0x1f
  43. #define RK818_LDO_VSEL_MASK 0x1f
  44. #define RK818_LDO3_ON_VSEL_MASK 0xf
  45. #define RK818_BOOST_ON_VSEL_MASK 0xe0
  46. #define RK818_USB_ILIM_SEL_MASK 0x0f
  47. #define RK818_USB_CHG_SD_VSEL_MASK 0x70
  48. /*
  49. * Ramp delay
  50. */
  51. #define RK805_RAMP_RATE_OFFSET 3
  52. #define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET)
  53. #define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET)
  54. #define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET)
  55. #define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET)
  56. #define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET)
  57. #define RK808_RAMP_RATE_OFFSET 3
  58. #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
  59. #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
  60. #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET)
  61. #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET)
  62. #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET)
  63. #define RK817_RAMP_RATE_OFFSET 6
  64. #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
  65. #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
  66. #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
  67. #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
  68. #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
  69. struct rk8xx_reg_info {
  70. uint min_uv;
  71. uint step_uv;
  72. u8 vsel_reg;
  73. u8 vsel_sleep_reg;
  74. u8 config_reg;
  75. u8 vsel_mask;
  76. u8 min_sel;
  77. };
  78. static const struct rk8xx_reg_info rk808_buck[] = {
  79. { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, },
  80. { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, },
  81. { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, },
  82. { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, },
  83. };
  84. static const struct rk8xx_reg_info rk816_buck[] = {
  85. /* buck 1 */
  86. { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
  87. { 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
  88. { 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
  89. /* buck 2 */
  90. { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
  91. { 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
  92. { 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
  93. /* buck 3 */
  94. { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
  95. /* buck 4 */
  96. { 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
  97. };
  98. static const struct rk8xx_reg_info rk809_buck5[] = {
  99. /* buck 5 */
  100. { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, },
  101. { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, },
  102. { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, },
  103. { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, },
  104. };
  105. static const struct rk8xx_reg_info rk817_buck[] = {
  106. /* buck 1 */
  107. { 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, },
  108. { 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, },
  109. { 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, },
  110. /* buck 2 */
  111. { 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, },
  112. { 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, },
  113. { 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, },
  114. /* buck 3 */
  115. { 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, },
  116. { 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, },
  117. { 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, },
  118. /* buck 4 */
  119. { 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, },
  120. { 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, },
  121. { 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, },
  122. };
  123. static const struct rk8xx_reg_info rk818_buck[] = {
  124. { 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, },
  125. { 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, },
  126. { 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
  127. { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
  128. };
  129. #ifdef ENABLE_DRIVER
  130. static const struct rk8xx_reg_info rk808_ldo[] = {
  131. { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  132. { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  133. { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK808_BUCK4_VSEL_MASK, },
  134. { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  135. { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  136. { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  137. { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  138. { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
  139. };
  140. static const struct rk8xx_reg_info rk816_ldo[] = {
  141. { 800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  142. { 800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  143. { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  144. { 800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  145. { 800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  146. { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  147. };
  148. static const struct rk8xx_reg_info rk817_ldo[] = {
  149. /* ldo1 */
  150. { 600000, 25000, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x00, },
  151. { 3400000, 0, RK817_LDO_ON_VSEL(1), RK817_LDO_SLP_VSEL(1), NA, RK817_LDO_VSEL_MASK, 0x70, },
  152. /* ldo2 */
  153. { 600000, 25000, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x00, },
  154. { 3400000, 0, RK817_LDO_ON_VSEL(2), RK817_LDO_SLP_VSEL(2), NA, RK817_LDO_VSEL_MASK, 0x70, },
  155. /* ldo3 */
  156. { 600000, 25000, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x00, },
  157. { 3400000, 0, RK817_LDO_ON_VSEL(3), RK817_LDO_SLP_VSEL(3), NA, RK817_LDO_VSEL_MASK, 0x70, },
  158. /* ldo4 */
  159. { 600000, 25000, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x00, },
  160. { 3400000, 0, RK817_LDO_ON_VSEL(4), RK817_LDO_SLP_VSEL(4), NA, RK817_LDO_VSEL_MASK, 0x70, },
  161. /* ldo5 */
  162. { 600000, 25000, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x00, },
  163. { 3400000, 0, RK817_LDO_ON_VSEL(5), RK817_LDO_SLP_VSEL(5), NA, RK817_LDO_VSEL_MASK, 0x70, },
  164. /* ldo6 */
  165. { 600000, 25000, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x00, },
  166. { 3400000, 0, RK817_LDO_ON_VSEL(6), RK817_LDO_SLP_VSEL(6), NA, RK817_LDO_VSEL_MASK, 0x70, },
  167. /* ldo7 */
  168. { 600000, 25000, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x00, },
  169. { 3400000, 0, RK817_LDO_ON_VSEL(7), RK817_LDO_SLP_VSEL(7), NA, RK817_LDO_VSEL_MASK, 0x70, },
  170. /* ldo8 */
  171. { 600000, 25000, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x00, },
  172. { 3400000, 0, RK817_LDO_ON_VSEL(8), RK817_LDO_SLP_VSEL(8), NA, RK817_LDO_VSEL_MASK, 0x70, },
  173. /* ldo9 */
  174. { 600000, 25000, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x00, },
  175. { 3400000, 0, RK817_LDO_ON_VSEL(9), RK817_LDO_SLP_VSEL(9), NA, RK817_LDO_VSEL_MASK, 0x70, },
  176. };
  177. static const struct rk8xx_reg_info rk818_ldo[] = {
  178. { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  179. { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  180. { 800000, 100000, REG_LDO3_ON_VSEL, REG_LDO3_SLP_VSEL, NA, RK818_LDO3_ON_VSEL_MASK, },
  181. { 1800000, 100000, REG_LDO4_ON_VSEL, REG_LDO4_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  182. { 1800000, 100000, REG_LDO5_ON_VSEL, REG_LDO5_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  183. { 800000, 100000, REG_LDO6_ON_VSEL, REG_LDO6_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  184. { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  185. { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
  186. };
  187. #endif
  188. static const u16 rk818_chrg_cur_input_array[] = {
  189. 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
  190. };
  191. static const uint rk818_chrg_shutdown_vsel_array[] = {
  192. 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
  193. };
  194. static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
  195. int num, int uvolt)
  196. {
  197. struct rk8xx_priv *priv = dev_get_priv(pmic);
  198. switch (priv->variant) {
  199. case RK805_ID:
  200. case RK816_ID:
  201. switch (num) {
  202. case 0:
  203. case 1:
  204. if (uvolt <= 1450000)
  205. return &rk816_buck[num * 3 + 0];
  206. else if (uvolt <= 2200000)
  207. return &rk816_buck[num * 3 + 1];
  208. else
  209. return &rk816_buck[num * 3 + 2];
  210. default:
  211. return &rk816_buck[num + 4];
  212. }
  213. case RK809_ID:
  214. case RK817_ID:
  215. switch (num) {
  216. case 0 ... 2:
  217. if (uvolt < 1500000)
  218. return &rk817_buck[num * 3 + 0];
  219. else if (uvolt < 2400000)
  220. return &rk817_buck[num * 3 + 1];
  221. else
  222. return &rk817_buck[num * 3 + 2];
  223. case 3:
  224. if (uvolt < 1500000)
  225. return &rk817_buck[num * 3 + 0];
  226. else if (uvolt < 3400000)
  227. return &rk817_buck[num * 3 + 1];
  228. else
  229. return &rk817_buck[num * 3 + 2];
  230. /* BUCK5 for RK809 */
  231. default:
  232. if (uvolt < 1800000)
  233. return &rk809_buck5[0];
  234. else if (uvolt < 2800000)
  235. return &rk809_buck5[1];
  236. else if (uvolt < 3300000)
  237. return &rk809_buck5[2];
  238. else
  239. return &rk809_buck5[3];
  240. }
  241. case RK818_ID:
  242. return &rk818_buck[num];
  243. default:
  244. return &rk808_buck[num];
  245. }
  246. }
  247. static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
  248. {
  249. const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
  250. struct rk8xx_priv *priv = dev_get_priv(pmic);
  251. int mask = info->vsel_mask;
  252. int val;
  253. if (info->vsel_reg == NA)
  254. return -ENOSYS;
  255. if (info->step_uv == 0) /* Fixed voltage */
  256. val = info->min_sel;
  257. else
  258. val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
  259. debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
  260. __func__, uvolt, buck + 1, info->vsel_reg, mask, val);
  261. if (priv->variant == RK816_ID) {
  262. pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
  263. return pmic_clrsetbits(pmic, RK816_REG_DCDC_EN2,
  264. 1 << 7, 1 << 7);
  265. } else {
  266. return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
  267. }
  268. }
  269. static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
  270. {
  271. uint mask, value, en_reg;
  272. int ret = 0;
  273. struct rk8xx_priv *priv = dev_get_priv(pmic);
  274. switch (priv->variant) {
  275. case RK805_ID:
  276. case RK816_ID:
  277. if (buck >= 4) {
  278. buck -= 4;
  279. en_reg = RK816_REG_DCDC_EN2;
  280. } else {
  281. en_reg = RK816_REG_DCDC_EN1;
  282. }
  283. if (enable)
  284. value = ((1 << buck) | (1 << (buck + 4)));
  285. else
  286. value = ((0 << buck) | (1 << (buck + 4)));
  287. ret = pmic_reg_write(pmic, en_reg, value);
  288. break;
  289. case RK808_ID:
  290. case RK818_ID:
  291. mask = 1 << buck;
  292. if (enable) {
  293. ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX,
  294. 0, 3 << (buck * 2));
  295. if (ret)
  296. return ret;
  297. }
  298. ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask,
  299. enable ? mask : 0);
  300. break;
  301. case RK809_ID:
  302. case RK817_ID:
  303. if (buck < 4) {
  304. if (enable)
  305. value = ((1 << buck) | (1 << (buck + 4)));
  306. else
  307. value = ((0 << buck) | (1 << (buck + 4)));
  308. ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value);
  309. /* BUCK5 for RK809 */
  310. } else {
  311. if (enable)
  312. value = ((1 << 1) | (1 << 5));
  313. else
  314. value = ((0 << 1) | (1 << 5));
  315. ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value);
  316. }
  317. break;
  318. default:
  319. ret = -EINVAL;
  320. }
  321. return ret;
  322. }
  323. #ifdef ENABLE_DRIVER
  324. static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
  325. {
  326. const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
  327. int mask = info->vsel_mask;
  328. int val;
  329. if (info->vsel_sleep_reg == NA)
  330. return -ENOSYS;
  331. if (info->step_uv == 0)
  332. val = info->min_sel;
  333. else
  334. val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
  335. debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
  336. __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val);
  337. return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
  338. }
  339. static int _buck_get_enable(struct udevice *pmic, int buck)
  340. {
  341. struct rk8xx_priv *priv = dev_get_priv(pmic);
  342. uint mask = 0;
  343. int ret = 0;
  344. switch (priv->variant) {
  345. case RK805_ID:
  346. case RK816_ID:
  347. if (buck >= 4) {
  348. mask = 1 << (buck - 4);
  349. ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN2);
  350. } else {
  351. mask = 1 << buck;
  352. ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1);
  353. }
  354. break;
  355. case RK808_ID:
  356. case RK818_ID:
  357. mask = 1 << buck;
  358. ret = pmic_reg_read(pmic, REG_DCDC_EN);
  359. if (ret < 0)
  360. return ret;
  361. break;
  362. case RK809_ID:
  363. case RK817_ID:
  364. if (buck < 4) {
  365. mask = 1 << buck;
  366. ret = pmic_reg_read(pmic, RK817_POWER_EN(0));
  367. /* BUCK5 for RK809 */
  368. } else {
  369. mask = 1 << 1;
  370. ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
  371. }
  372. break;
  373. }
  374. if (ret < 0)
  375. return ret;
  376. return ret & mask ? true : false;
  377. }
  378. static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable)
  379. {
  380. uint mask = 0;
  381. int ret;
  382. struct rk8xx_priv *priv = dev_get_priv(pmic);
  383. switch (priv->variant) {
  384. case RK805_ID:
  385. case RK816_ID:
  386. mask = 1 << buck;
  387. ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask,
  388. enable ? mask : 0);
  389. break;
  390. case RK808_ID:
  391. case RK818_ID:
  392. mask = 1 << buck;
  393. ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask,
  394. enable ? 0 : mask);
  395. break;
  396. case RK809_ID:
  397. case RK817_ID:
  398. if (buck < 4)
  399. mask = 1 << buck;
  400. else
  401. mask = 1 << 5; /* BUCK5 for RK809 */
  402. ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
  403. enable ? mask : 0);
  404. break;
  405. default:
  406. ret = -EINVAL;
  407. }
  408. return ret;
  409. }
  410. static int _buck_get_suspend_enable(struct udevice *pmic, int buck)
  411. {
  412. struct rk8xx_priv *priv = dev_get_priv(pmic);
  413. int ret, val;
  414. uint mask = 0;
  415. switch (priv->variant) {
  416. case RK805_ID:
  417. case RK816_ID:
  418. mask = 1 << buck;
  419. val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN);
  420. if (val < 0)
  421. return val;
  422. ret = val & mask ? 1 : 0;
  423. break;
  424. case RK808_ID:
  425. case RK818_ID:
  426. mask = 1 << buck;
  427. val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1);
  428. if (val < 0)
  429. return val;
  430. ret = val & mask ? 0 : 1;
  431. break;
  432. case RK809_ID:
  433. case RK817_ID:
  434. if (buck < 4)
  435. mask = 1 << buck;
  436. else
  437. mask = 1 << 5; /* BUCK5 for RK809 */
  438. val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
  439. if (val < 0)
  440. return val;
  441. ret = val & mask ? 1 : 0;
  442. break;
  443. default:
  444. ret = -EINVAL;
  445. }
  446. return ret;
  447. }
  448. static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
  449. int num, int uvolt)
  450. {
  451. struct rk8xx_priv *priv = dev_get_priv(pmic);
  452. switch (priv->variant) {
  453. case RK805_ID:
  454. case RK816_ID:
  455. return &rk816_ldo[num];
  456. case RK809_ID:
  457. case RK817_ID:
  458. if (uvolt < 3400000)
  459. return &rk817_ldo[num * 2 + 0];
  460. else
  461. return &rk817_ldo[num * 2 + 1];
  462. case RK818_ID:
  463. return &rk818_ldo[num];
  464. default:
  465. return &rk808_ldo[num];
  466. }
  467. }
  468. static int _ldo_get_enable(struct udevice *pmic, int ldo)
  469. {
  470. struct rk8xx_priv *priv = dev_get_priv(pmic);
  471. uint mask = 0;
  472. int ret = 0;
  473. switch (priv->variant) {
  474. case RK805_ID:
  475. case RK816_ID:
  476. if (ldo >= 4) {
  477. mask = 1 << (ldo - 4);
  478. ret = pmic_reg_read(pmic, RK816_REG_LDO_EN2);
  479. } else {
  480. mask = 1 << ldo;
  481. ret = pmic_reg_read(pmic, RK816_REG_LDO_EN1);
  482. }
  483. break;
  484. case RK808_ID:
  485. case RK818_ID:
  486. mask = 1 << ldo;
  487. ret = pmic_reg_read(pmic, REG_LDO_EN);
  488. if (ret < 0)
  489. return ret;
  490. break;
  491. case RK809_ID:
  492. case RK817_ID:
  493. if (ldo < 4) {
  494. mask = 1 << ldo;
  495. ret = pmic_reg_read(pmic, RK817_POWER_EN(1));
  496. } else if (ldo < 8) {
  497. mask = 1 << (ldo - 4);
  498. ret = pmic_reg_read(pmic, RK817_POWER_EN(2));
  499. } else if (ldo == 8) {
  500. mask = 1 << 0;
  501. ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
  502. } else {
  503. return false;
  504. }
  505. break;
  506. }
  507. if (ret < 0)
  508. return ret;
  509. return ret & mask ? true : false;
  510. }
  511. static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
  512. {
  513. struct rk8xx_priv *priv = dev_get_priv(pmic);
  514. uint mask, value, en_reg;
  515. int ret = 0;
  516. switch (priv->variant) {
  517. case RK805_ID:
  518. case RK816_ID:
  519. if (ldo >= 4) {
  520. ldo -= 4;
  521. en_reg = RK816_REG_LDO_EN2;
  522. } else {
  523. en_reg = RK816_REG_LDO_EN1;
  524. }
  525. if (enable)
  526. value = ((1 << ldo) | (1 << (ldo + 4)));
  527. else
  528. value = ((0 << ldo) | (1 << (ldo + 4)));
  529. ret = pmic_reg_write(pmic, en_reg, value);
  530. break;
  531. case RK808_ID:
  532. case RK818_ID:
  533. mask = 1 << ldo;
  534. ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask,
  535. enable ? mask : 0);
  536. break;
  537. case RK809_ID:
  538. case RK817_ID:
  539. if (ldo < 4) {
  540. en_reg = RK817_POWER_EN(1);
  541. } else if (ldo < 8) {
  542. ldo -= 4;
  543. en_reg = RK817_POWER_EN(2);
  544. } else if (ldo == 8) {
  545. ldo = 0; /* BIT 0 */
  546. en_reg = RK817_POWER_EN(3);
  547. } else {
  548. return -EINVAL;
  549. }
  550. if (enable)
  551. value = ((1 << ldo) | (1 << (ldo + 4)));
  552. else
  553. value = ((0 << ldo) | (1 << (ldo + 4)));
  554. ret = pmic_reg_write(pmic, en_reg, value);
  555. break;
  556. }
  557. return ret;
  558. }
  559. static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
  560. {
  561. struct rk8xx_priv *priv = dev_get_priv(pmic);
  562. uint mask;
  563. int ret = 0;
  564. switch (priv->variant) {
  565. case RK805_ID:
  566. case RK816_ID:
  567. mask = 1 << ldo;
  568. ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask,
  569. enable ? mask : 0);
  570. break;
  571. case RK808_ID:
  572. case RK818_ID:
  573. mask = 1 << ldo;
  574. ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask,
  575. enable ? 0 : mask);
  576. break;
  577. case RK809_ID:
  578. case RK817_ID:
  579. if (ldo == 8) {
  580. mask = 1 << 4; /* LDO9 */
  581. ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
  582. enable ? mask : 0);
  583. } else {
  584. mask = 1 << ldo;
  585. ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask,
  586. enable ? mask : 0);
  587. }
  588. break;
  589. }
  590. return ret;
  591. }
  592. static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
  593. {
  594. struct rk8xx_priv *priv = dev_get_priv(pmic);
  595. int val, ret = 0;
  596. uint mask;
  597. switch (priv->variant) {
  598. case RK805_ID:
  599. case RK816_ID:
  600. mask = 1 << ldo;
  601. val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN);
  602. if (val < 0)
  603. return val;
  604. ret = val & mask ? 1 : 0;
  605. break;
  606. case RK808_ID:
  607. case RK818_ID:
  608. mask = 1 << ldo;
  609. val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2);
  610. if (val < 0)
  611. return val;
  612. ret = val & mask ? 0 : 1;
  613. break;
  614. case RK809_ID:
  615. case RK817_ID:
  616. if (ldo == 8) {
  617. mask = 1 << 4; /* LDO9 */
  618. val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
  619. if (val < 0)
  620. return val;
  621. ret = val & mask ? 1 : 0;
  622. } else {
  623. mask = 1 << ldo;
  624. val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1));
  625. if (val < 0)
  626. return val;
  627. ret = val & mask ? 1 : 0;
  628. }
  629. break;
  630. }
  631. return ret;
  632. }
  633. static int buck_get_value(struct udevice *dev)
  634. {
  635. int buck = dev->driver_data - 1;
  636. /* We assume level-1 voltage is enough for usage in U-Boot */
  637. const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
  638. int mask = info->vsel_mask;
  639. int ret, val;
  640. if (info->vsel_reg == NA)
  641. return -ENOSYS;
  642. ret = pmic_reg_read(dev->parent, info->vsel_reg);
  643. if (ret < 0)
  644. return ret;
  645. val = ret & mask;
  646. return info->min_uv + val * info->step_uv;
  647. }
  648. static int buck_set_value(struct udevice *dev, int uvolt)
  649. {
  650. int buck = dev->driver_data - 1;
  651. return _buck_set_value(dev->parent, buck, uvolt);
  652. }
  653. static int buck_get_suspend_value(struct udevice *dev)
  654. {
  655. int buck = dev->driver_data - 1;
  656. /* We assume level-1 voltage is enough for usage in U-Boot */
  657. const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
  658. int mask = info->vsel_mask;
  659. int ret, val;
  660. if (info->vsel_sleep_reg == NA)
  661. return -ENOSYS;
  662. ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
  663. if (ret < 0)
  664. return ret;
  665. val = ret & mask;
  666. return info->min_uv + val * info->step_uv;
  667. }
  668. static int buck_set_suspend_value(struct udevice *dev, int uvolt)
  669. {
  670. int buck = dev->driver_data - 1;
  671. return _buck_set_suspend_value(dev->parent, buck, uvolt);
  672. }
  673. static int buck_set_enable(struct udevice *dev, bool enable)
  674. {
  675. int buck = dev->driver_data - 1;
  676. return _buck_set_enable(dev->parent, buck, enable);
  677. }
  678. static int buck_set_suspend_enable(struct udevice *dev, bool enable)
  679. {
  680. int buck = dev->driver_data - 1;
  681. return _buck_set_suspend_enable(dev->parent, buck, enable);
  682. }
  683. static int buck_get_suspend_enable(struct udevice *dev)
  684. {
  685. int buck = dev->driver_data - 1;
  686. return _buck_get_suspend_enable(dev->parent, buck);
  687. }
  688. static int buck_get_enable(struct udevice *dev)
  689. {
  690. int buck = dev->driver_data - 1;
  691. return _buck_get_enable(dev->parent, buck);
  692. }
  693. static int ldo_get_value(struct udevice *dev)
  694. {
  695. int ldo = dev->driver_data - 1;
  696. const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
  697. int mask = info->vsel_mask;
  698. int ret, val;
  699. if (info->vsel_reg == NA)
  700. return -ENOSYS;
  701. ret = pmic_reg_read(dev->parent, info->vsel_reg);
  702. if (ret < 0)
  703. return ret;
  704. val = ret & mask;
  705. return info->min_uv + val * info->step_uv;
  706. }
  707. static int ldo_set_value(struct udevice *dev, int uvolt)
  708. {
  709. int ldo = dev->driver_data - 1;
  710. const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
  711. int mask = info->vsel_mask;
  712. int val;
  713. if (info->vsel_reg == NA)
  714. return -ENOSYS;
  715. if (info->step_uv == 0)
  716. val = info->min_sel;
  717. else
  718. val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
  719. debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
  720. __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
  721. return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
  722. }
  723. static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
  724. {
  725. int ldo = dev->driver_data - 1;
  726. const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
  727. int mask = info->vsel_mask;
  728. int val;
  729. if (info->vsel_sleep_reg == NA)
  730. return -ENOSYS;
  731. if (info->step_uv == 0)
  732. val = info->min_sel;
  733. else
  734. val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
  735. debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
  736. __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val);
  737. return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
  738. }
  739. static int ldo_get_suspend_value(struct udevice *dev)
  740. {
  741. int ldo = dev->driver_data - 1;
  742. const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
  743. int mask = info->vsel_mask;
  744. int val, ret;
  745. if (info->vsel_sleep_reg == NA)
  746. return -ENOSYS;
  747. ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg);
  748. if (ret < 0)
  749. return ret;
  750. val = ret & mask;
  751. return info->min_uv + val * info->step_uv;
  752. }
  753. static int ldo_set_enable(struct udevice *dev, bool enable)
  754. {
  755. int ldo = dev->driver_data - 1;
  756. return _ldo_set_enable(dev->parent, ldo, enable);
  757. }
  758. static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
  759. {
  760. int ldo = dev->driver_data - 1;
  761. return _ldo_set_suspend_enable(dev->parent, ldo, enable);
  762. }
  763. static int ldo_get_suspend_enable(struct udevice *dev)
  764. {
  765. int ldo = dev->driver_data - 1;
  766. return _ldo_get_suspend_enable(dev->parent, ldo);
  767. }
  768. static int ldo_get_enable(struct udevice *dev)
  769. {
  770. int ldo = dev->driver_data - 1;
  771. return _ldo_get_enable(dev->parent, ldo);
  772. }
  773. static int switch_set_enable(struct udevice *dev, bool enable)
  774. {
  775. struct rk8xx_priv *priv = dev_get_priv(dev->parent);
  776. int ret = 0, sw = dev->driver_data - 1;
  777. uint mask = 0;
  778. switch (priv->variant) {
  779. case RK808_ID:
  780. mask = 1 << (sw + 5);
  781. ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
  782. enable ? mask : 0);
  783. break;
  784. case RK809_ID:
  785. mask = (1 << (sw + 2)) | (1 << (sw + 6));
  786. ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
  787. enable ? mask : 0);
  788. break;
  789. case RK818_ID:
  790. mask = 1 << 6;
  791. ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
  792. enable ? mask : 0);
  793. break;
  794. }
  795. debug("%s: switch%d, enable=%d, mask=0x%x\n",
  796. __func__, sw + 1, enable, mask);
  797. return ret;
  798. }
  799. static int switch_get_enable(struct udevice *dev)
  800. {
  801. struct rk8xx_priv *priv = dev_get_priv(dev->parent);
  802. int ret = 0, sw = dev->driver_data - 1;
  803. uint mask = 0;
  804. switch (priv->variant) {
  805. case RK808_ID:
  806. mask = 1 << (sw + 5);
  807. ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
  808. break;
  809. case RK809_ID:
  810. mask = 1 << (sw + 2);
  811. ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
  812. break;
  813. case RK818_ID:
  814. mask = 1 << 6;
  815. ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
  816. break;
  817. }
  818. if (ret < 0)
  819. return ret;
  820. return ret & mask ? true : false;
  821. }
  822. static int switch_set_suspend_value(struct udevice *dev, int uvolt)
  823. {
  824. return 0;
  825. }
  826. static int switch_get_suspend_value(struct udevice *dev)
  827. {
  828. return 0;
  829. }
  830. static int switch_set_suspend_enable(struct udevice *dev, bool enable)
  831. {
  832. struct rk8xx_priv *priv = dev_get_priv(dev->parent);
  833. int ret = 0, sw = dev->driver_data - 1;
  834. uint mask = 0;
  835. switch (priv->variant) {
  836. case RK808_ID:
  837. mask = 1 << (sw + 5);
  838. ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
  839. enable ? 0 : mask);
  840. break;
  841. case RK809_ID:
  842. mask = 1 << (sw + 6);
  843. ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
  844. enable ? mask : 0);
  845. break;
  846. case RK818_ID:
  847. mask = 1 << 6;
  848. ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
  849. enable ? 0 : mask);
  850. break;
  851. }
  852. debug("%s: switch%d, enable=%d, mask=0x%x\n",
  853. __func__, sw + 1, enable, mask);
  854. return ret;
  855. }
  856. static int switch_get_suspend_enable(struct udevice *dev)
  857. {
  858. struct rk8xx_priv *priv = dev_get_priv(dev->parent);
  859. int val, ret = 0, sw = dev->driver_data - 1;
  860. uint mask = 0;
  861. switch (priv->variant) {
  862. case RK808_ID:
  863. mask = 1 << (sw + 5);
  864. val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
  865. if (val < 0)
  866. return val;
  867. ret = val & mask ? 0 : 1;
  868. break;
  869. case RK809_ID:
  870. mask = 1 << (sw + 6);
  871. val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
  872. if (val < 0)
  873. return val;
  874. ret = val & mask ? 1 : 0;
  875. break;
  876. case RK818_ID:
  877. mask = 1 << 6;
  878. val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);
  879. if (val < 0)
  880. return val;
  881. ret = val & mask ? 0 : 1;
  882. break;
  883. }
  884. return ret;
  885. }
  886. /*
  887. * RK8xx switch does not need to set the voltage,
  888. * but if dts set regulator-min-microvolt/regulator-max-microvolt,
  889. * will cause regulator set value fail and not to enable this switch.
  890. * So add an empty function to return success.
  891. */
  892. static int switch_get_value(struct udevice *dev)
  893. {
  894. return 0;
  895. }
  896. static int switch_set_value(struct udevice *dev, int uvolt)
  897. {
  898. return 0;
  899. }
  900. static int rk8xx_buck_probe(struct udevice *dev)
  901. {
  902. struct dm_regulator_uclass_plat *uc_pdata;
  903. uc_pdata = dev_get_uclass_plat(dev);
  904. uc_pdata->type = REGULATOR_TYPE_BUCK;
  905. uc_pdata->mode_count = 0;
  906. return 0;
  907. }
  908. static int rk8xx_ldo_probe(struct udevice *dev)
  909. {
  910. struct dm_regulator_uclass_plat *uc_pdata;
  911. uc_pdata = dev_get_uclass_plat(dev);
  912. uc_pdata->type = REGULATOR_TYPE_LDO;
  913. uc_pdata->mode_count = 0;
  914. return 0;
  915. }
  916. static int rk8xx_switch_probe(struct udevice *dev)
  917. {
  918. struct dm_regulator_uclass_plat *uc_pdata;
  919. uc_pdata = dev_get_uclass_plat(dev);
  920. uc_pdata->type = REGULATOR_TYPE_FIXED;
  921. uc_pdata->mode_count = 0;
  922. return 0;
  923. }
  924. static const struct dm_regulator_ops rk8xx_buck_ops = {
  925. .get_value = buck_get_value,
  926. .set_value = buck_set_value,
  927. .set_suspend_value = buck_set_suspend_value,
  928. .get_suspend_value = buck_get_suspend_value,
  929. .get_enable = buck_get_enable,
  930. .set_enable = buck_set_enable,
  931. .set_suspend_enable = buck_set_suspend_enable,
  932. .get_suspend_enable = buck_get_suspend_enable,
  933. };
  934. static const struct dm_regulator_ops rk8xx_ldo_ops = {
  935. .get_value = ldo_get_value,
  936. .set_value = ldo_set_value,
  937. .set_suspend_value = ldo_set_suspend_value,
  938. .get_suspend_value = ldo_get_suspend_value,
  939. .get_enable = ldo_get_enable,
  940. .set_enable = ldo_set_enable,
  941. .set_suspend_enable = ldo_set_suspend_enable,
  942. .get_suspend_enable = ldo_get_suspend_enable,
  943. };
  944. static const struct dm_regulator_ops rk8xx_switch_ops = {
  945. .get_value = switch_get_value,
  946. .set_value = switch_set_value,
  947. .get_enable = switch_get_enable,
  948. .set_enable = switch_set_enable,
  949. .set_suspend_enable = switch_set_suspend_enable,
  950. .get_suspend_enable = switch_get_suspend_enable,
  951. .set_suspend_value = switch_set_suspend_value,
  952. .get_suspend_value = switch_get_suspend_value,
  953. };
  954. U_BOOT_DRIVER(rk8xx_buck) = {
  955. .name = "rk8xx_buck",
  956. .id = UCLASS_REGULATOR,
  957. .ops = &rk8xx_buck_ops,
  958. .probe = rk8xx_buck_probe,
  959. };
  960. U_BOOT_DRIVER(rk8xx_ldo) = {
  961. .name = "rk8xx_ldo",
  962. .id = UCLASS_REGULATOR,
  963. .ops = &rk8xx_ldo_ops,
  964. .probe = rk8xx_ldo_probe,
  965. };
  966. U_BOOT_DRIVER(rk8xx_switch) = {
  967. .name = "rk8xx_switch",
  968. .id = UCLASS_REGULATOR,
  969. .ops = &rk8xx_switch_ops,
  970. .probe = rk8xx_switch_probe,
  971. };
  972. #endif
  973. int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
  974. {
  975. int ret;
  976. ret = _buck_set_value(pmic, buck, uvolt);
  977. if (ret)
  978. return ret;
  979. return _buck_set_enable(pmic, buck, true);
  980. }
  981. int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
  982. {
  983. uint i;
  984. for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
  985. if (current_ma <= rk818_chrg_cur_input_array[i])
  986. break;
  987. return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
  988. }
  989. int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
  990. {
  991. uint i;
  992. for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
  993. if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
  994. break;
  995. return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
  996. i);
  997. }