meson-ee-pwrc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <power-domain-uclass.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <reset.h>
  14. #include <clk.h>
  15. #include <dt-bindings/power/meson-axg-power.h>
  16. #include <dt-bindings/power/meson-g12a-power.h>
  17. #include <dt-bindings/power/meson-gxbb-power.h>
  18. #include <dt-bindings/power/meson-sm1-power.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <linux/err.h>
  22. /* AO Offsets */
  23. #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
  24. #define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
  25. /* HHI Offsets */
  26. #define HHI_MEM_PD_REG0 (0x40 << 2)
  27. #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
  28. #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
  29. #define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
  30. #define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
  31. #define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
  32. #define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
  33. #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
  34. #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
  35. struct meson_ee_pwrc;
  36. struct meson_ee_pwrc_domain;
  37. struct meson_ee_pwrc_mem_domain {
  38. unsigned int reg;
  39. unsigned int mask;
  40. };
  41. struct meson_ee_pwrc_top_domain {
  42. unsigned int sleep_reg;
  43. unsigned int sleep_mask;
  44. unsigned int iso_reg;
  45. unsigned int iso_mask;
  46. };
  47. struct meson_ee_pwrc_domain_desc {
  48. char *name;
  49. unsigned int reset_names_count;
  50. unsigned int clk_names_count;
  51. struct meson_ee_pwrc_top_domain *top_pd;
  52. unsigned int mem_pd_count;
  53. struct meson_ee_pwrc_mem_domain *mem_pd;
  54. bool (*get_power)(struct power_domain *power_domain);
  55. };
  56. struct meson_ee_pwrc_domain_data {
  57. unsigned int count;
  58. struct meson_ee_pwrc_domain_desc *domains;
  59. };
  60. /* TOP Power Domains */
  61. static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
  62. .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  63. .sleep_mask = BIT(8),
  64. .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  65. .iso_mask = BIT(9),
  66. };
  67. #define SM1_EE_PD(__bit) \
  68. { \
  69. .sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \
  70. .sleep_mask = BIT(__bit), \
  71. .iso_reg = AO_RTI_GEN_PWR_ISO0, \
  72. .iso_mask = BIT(__bit), \
  73. }
  74. static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  75. static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  76. static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  77. static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  78. static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  79. /* Memory PD Domains */
  80. #define VPU_MEMPD(__reg) \
  81. { __reg, GENMASK(1, 0) }, \
  82. { __reg, GENMASK(3, 2) }, \
  83. { __reg, GENMASK(5, 4) }, \
  84. { __reg, GENMASK(7, 6) }, \
  85. { __reg, GENMASK(9, 8) }, \
  86. { __reg, GENMASK(11, 10) }, \
  87. { __reg, GENMASK(13, 12) }, \
  88. { __reg, GENMASK(15, 14) }, \
  89. { __reg, GENMASK(17, 16) }, \
  90. { __reg, GENMASK(19, 18) }, \
  91. { __reg, GENMASK(21, 20) }, \
  92. { __reg, GENMASK(23, 22) }, \
  93. { __reg, GENMASK(25, 24) }, \
  94. { __reg, GENMASK(27, 26) }, \
  95. { __reg, GENMASK(29, 28) }, \
  96. { __reg, GENMASK(31, 30) }
  97. #define VPU_HHI_MEMPD(__reg) \
  98. { __reg, BIT(8) }, \
  99. { __reg, BIT(9) }, \
  100. { __reg, BIT(10) }, \
  101. { __reg, BIT(11) }, \
  102. { __reg, BIT(12) }, \
  103. { __reg, BIT(13) }, \
  104. { __reg, BIT(14) }, \
  105. { __reg, BIT(15) }
  106. static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
  107. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  108. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  109. VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
  110. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  111. };
  112. static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = {
  113. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  114. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  115. };
  116. static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = {
  117. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  118. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  119. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  120. };
  121. static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
  122. { HHI_MEM_PD_REG0, GENMASK(3, 2) },
  123. };
  124. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
  125. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  126. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  127. VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
  128. VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
  129. { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
  130. { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
  131. { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
  132. { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
  133. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  134. };
  135. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
  136. { HHI_NANOQ_MEM_PD_REG0, 0xff },
  137. { HHI_NANOQ_MEM_PD_REG1, 0xff },
  138. };
  139. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
  140. { HHI_MEM_PD_REG0, GENMASK(31, 30) },
  141. };
  142. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
  143. { HHI_MEM_PD_REG0, GENMASK(29, 26) },
  144. };
  145. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
  146. { HHI_MEM_PD_REG0, GENMASK(25, 18) },
  147. };
  148. static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = {
  149. { HHI_MEM_PD_REG0, GENMASK(5, 4) },
  150. };
  151. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
  152. { HHI_MEM_PD_REG0, GENMASK(5, 4) },
  153. { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
  154. { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
  155. { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
  156. { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
  157. { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
  158. { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
  159. { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
  160. { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
  161. { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
  162. { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
  163. { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
  164. { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
  165. };
  166. #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \
  167. { \
  168. .name = __name, \
  169. .reset_names_count = __resets, \
  170. .clk_names_count = __clks, \
  171. .top_pd = __top_pd, \
  172. .mem_pd_count = ARRAY_SIZE(__mem), \
  173. .mem_pd = __mem, \
  174. .get_power = __get_power, \
  175. }
  176. #define TOP_PD(__name, __top_pd, __mem, __get_power) \
  177. { \
  178. .name = __name, \
  179. .top_pd = __top_pd, \
  180. .mem_pd_count = ARRAY_SIZE(__mem), \
  181. .mem_pd = __mem, \
  182. .get_power = __get_power, \
  183. }
  184. #define MEM_PD(__name, __mem) \
  185. TOP_PD(__name, NULL, __mem, NULL)
  186. static bool pwrc_ee_get_power(struct power_domain *power_domain);
  187. static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
  188. [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
  189. pwrc_ee_get_power, 11, 2),
  190. [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  191. };
  192. static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = {
  193. [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu,
  194. pwrc_ee_get_power, 5, 2),
  195. [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  196. [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio),
  197. };
  198. static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
  199. [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu,
  200. pwrc_ee_get_power, 12, 2),
  201. [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  202. };
  203. static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
  204. [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
  205. pwrc_ee_get_power, 11, 2),
  206. [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
  207. pwrc_ee_get_power),
  208. [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
  209. pwrc_ee_get_power),
  210. [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
  211. pwrc_ee_get_power),
  212. [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
  213. pwrc_ee_get_power),
  214. [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
  215. [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  216. };
  217. struct meson_ee_pwrc_priv {
  218. struct regmap *regmap_ao;
  219. struct regmap *regmap_hhi;
  220. struct reset_ctl_bulk resets;
  221. struct clk_bulk clks;
  222. const struct meson_ee_pwrc_domain_data *data;
  223. };
  224. static bool pwrc_ee_get_power(struct power_domain *power_domain)
  225. {
  226. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  227. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  228. u32 reg;
  229. pwrc_domain = &priv->data->domains[power_domain->id];
  230. regmap_read(priv->regmap_ao,
  231. pwrc_domain->top_pd->sleep_reg, &reg);
  232. return (reg & pwrc_domain->top_pd->sleep_mask);
  233. }
  234. static int meson_ee_pwrc_request(struct power_domain *power_domain)
  235. {
  236. return 0;
  237. }
  238. static int meson_ee_pwrc_free(struct power_domain *power_domain)
  239. {
  240. return 0;
  241. }
  242. static int meson_ee_pwrc_off(struct power_domain *power_domain)
  243. {
  244. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  245. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  246. int i;
  247. pwrc_domain = &priv->data->domains[power_domain->id];
  248. if (pwrc_domain->top_pd)
  249. regmap_update_bits(priv->regmap_ao,
  250. pwrc_domain->top_pd->sleep_reg,
  251. pwrc_domain->top_pd->sleep_mask,
  252. pwrc_domain->top_pd->sleep_mask);
  253. udelay(20);
  254. for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
  255. regmap_update_bits(priv->regmap_hhi,
  256. pwrc_domain->mem_pd[i].reg,
  257. pwrc_domain->mem_pd[i].mask,
  258. pwrc_domain->mem_pd[i].mask);
  259. udelay(20);
  260. if (pwrc_domain->top_pd)
  261. regmap_update_bits(priv->regmap_ao,
  262. pwrc_domain->top_pd->iso_reg,
  263. pwrc_domain->top_pd->iso_mask,
  264. pwrc_domain->top_pd->iso_mask);
  265. if (pwrc_domain->clk_names_count) {
  266. mdelay(20);
  267. clk_disable_bulk(&priv->clks);
  268. }
  269. return 0;
  270. }
  271. static int meson_ee_pwrc_on(struct power_domain *power_domain)
  272. {
  273. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  274. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  275. int i, ret;
  276. pwrc_domain = &priv->data->domains[power_domain->id];
  277. if (pwrc_domain->top_pd)
  278. regmap_update_bits(priv->regmap_ao,
  279. pwrc_domain->top_pd->sleep_reg,
  280. pwrc_domain->top_pd->sleep_mask, 0);
  281. udelay(20);
  282. for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
  283. regmap_update_bits(priv->regmap_hhi,
  284. pwrc_domain->mem_pd[i].reg,
  285. pwrc_domain->mem_pd[i].mask, 0);
  286. udelay(20);
  287. if (pwrc_domain->reset_names_count) {
  288. ret = reset_assert_bulk(&priv->resets);
  289. if (ret)
  290. return ret;
  291. }
  292. if (pwrc_domain->top_pd)
  293. regmap_update_bits(priv->regmap_ao,
  294. pwrc_domain->top_pd->iso_reg,
  295. pwrc_domain->top_pd->iso_mask, 0);
  296. if (pwrc_domain->reset_names_count) {
  297. ret = reset_deassert_bulk(&priv->resets);
  298. if (ret)
  299. return ret;
  300. }
  301. if (pwrc_domain->clk_names_count)
  302. return clk_enable_bulk(&priv->clks);
  303. return 0;
  304. }
  305. static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
  306. struct ofnode_phandle_args *args)
  307. {
  308. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  309. /* #power-domain-cells is 1 */
  310. if (args->args_count < 1) {
  311. debug("Invalid args_count: %d\n", args->args_count);
  312. return -EINVAL;
  313. }
  314. power_domain->id = args->args[0];
  315. if (power_domain->id >= priv->data->count) {
  316. debug("Invalid domain ID: %lu\n", power_domain->id);
  317. return -EINVAL;
  318. }
  319. return 0;
  320. }
  321. struct power_domain_ops meson_ee_pwrc_ops = {
  322. .rfree = meson_ee_pwrc_free,
  323. .off = meson_ee_pwrc_off,
  324. .on = meson_ee_pwrc_on,
  325. .request = meson_ee_pwrc_request,
  326. .of_xlate = meson_ee_pwrc_of_xlate,
  327. };
  328. static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
  329. .count = ARRAY_SIZE(g12a_pwrc_domains),
  330. .domains = g12a_pwrc_domains,
  331. };
  332. static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = {
  333. .count = ARRAY_SIZE(axg_pwrc_domains),
  334. .domains = axg_pwrc_domains,
  335. };
  336. static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = {
  337. .count = ARRAY_SIZE(gxbb_pwrc_domains),
  338. .domains = gxbb_pwrc_domains,
  339. };
  340. static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
  341. .count = ARRAY_SIZE(sm1_pwrc_domains),
  342. .domains = sm1_pwrc_domains,
  343. };
  344. static const struct udevice_id meson_ee_pwrc_ids[] = {
  345. {
  346. .compatible = "amlogic,meson-g12a-pwrc",
  347. .data = (unsigned long)&meson_ee_g12a_pwrc_data,
  348. },
  349. {
  350. .compatible = "amlogic,meson-gxbb-pwrc",
  351. .data = (unsigned long)&meson_ee_gxbb_pwrc_data,
  352. },
  353. {
  354. .compatible = "amlogic,meson-axg-pwrc",
  355. .data = (unsigned long)&meson_ee_axg_pwrc_data,
  356. },
  357. {
  358. .compatible = "amlogic,meson-sm1-pwrc",
  359. .data = (unsigned long)&meson_ee_sm1_pwrc_data,
  360. },
  361. { }
  362. };
  363. static int meson_ee_pwrc_probe(struct udevice *dev)
  364. {
  365. struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
  366. u32 ao_phandle;
  367. ofnode ao_node;
  368. int ret;
  369. priv->data = (void *)dev_get_driver_data(dev);
  370. if (!priv->data)
  371. return -EINVAL;
  372. priv->regmap_hhi = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
  373. if (IS_ERR(priv->regmap_hhi))
  374. return PTR_ERR(priv->regmap_hhi);
  375. ret = ofnode_read_u32(dev_ofnode(dev), "amlogic,ao-sysctrl",
  376. &ao_phandle);
  377. if (ret)
  378. return ret;
  379. ao_node = ofnode_get_by_phandle(ao_phandle);
  380. if (!ofnode_valid(ao_node))
  381. return -EINVAL;
  382. priv->regmap_ao = syscon_node_to_regmap(ao_node);
  383. if (IS_ERR(priv->regmap_ao))
  384. return PTR_ERR(priv->regmap_ao);
  385. ret = reset_get_bulk(dev, &priv->resets);
  386. if (ret)
  387. return ret;
  388. ret = clk_get_bulk(dev, &priv->clks);
  389. if (ret)
  390. return ret;
  391. return 0;
  392. }
  393. U_BOOT_DRIVER(meson_ee_pwrc) = {
  394. .name = "meson_ee_pwrc",
  395. .id = UCLASS_POWER_DOMAIN,
  396. .of_match = meson_ee_pwrc_ids,
  397. .probe = meson_ee_pwrc_probe,
  398. .ops = &meson_ee_pwrc_ops,
  399. .priv_auto = sizeof(struct meson_ee_pwrc_priv),
  400. };