pinctrl-rv1108.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <dm/pinctrl.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <linux/bitops.h>
  12. #include "pinctrl-rockchip.h"
  13. static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
  14. {
  15. .num = 1,
  16. .pin = 0,
  17. .reg = 0x418,
  18. .bit = 0,
  19. .mask = 0x3
  20. }, {
  21. .num = 1,
  22. .pin = 1,
  23. .reg = 0x418,
  24. .bit = 2,
  25. .mask = 0x3
  26. }, {
  27. .num = 1,
  28. .pin = 2,
  29. .reg = 0x418,
  30. .bit = 4,
  31. .mask = 0x3
  32. }, {
  33. .num = 1,
  34. .pin = 3,
  35. .reg = 0x418,
  36. .bit = 6,
  37. .mask = 0x3
  38. }, {
  39. .num = 1,
  40. .pin = 4,
  41. .reg = 0x418,
  42. .bit = 8,
  43. .mask = 0x3
  44. }, {
  45. .num = 1,
  46. .pin = 5,
  47. .reg = 0x418,
  48. .bit = 10,
  49. .mask = 0x3
  50. }, {
  51. .num = 1,
  52. .pin = 6,
  53. .reg = 0x418,
  54. .bit = 12,
  55. .mask = 0x3
  56. }, {
  57. .num = 1,
  58. .pin = 7,
  59. .reg = 0x418,
  60. .bit = 14,
  61. .mask = 0x3
  62. }, {
  63. .num = 1,
  64. .pin = 8,
  65. .reg = 0x41c,
  66. .bit = 0,
  67. .mask = 0x3
  68. }, {
  69. .num = 1,
  70. .pin = 9,
  71. .reg = 0x41c,
  72. .bit = 2,
  73. .mask = 0x3
  74. },
  75. };
  76. static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  77. {
  78. struct rockchip_pinctrl_priv *priv = bank->priv;
  79. int iomux_num = (pin / 8);
  80. struct regmap *regmap;
  81. int reg, ret, mask, mux_type;
  82. u8 bit;
  83. u32 data;
  84. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  85. ? priv->regmap_pmu : priv->regmap_base;
  86. /* get basic quadrupel of mux registers and the correct reg inside */
  87. mux_type = bank->iomux[iomux_num].type;
  88. reg = bank->iomux[iomux_num].offset;
  89. reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  90. if (bank->recalced_mask & BIT(pin))
  91. rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
  92. data = (mask << (bit + 16));
  93. data |= (mux & mask) << bit;
  94. ret = regmap_write(regmap, reg, data);
  95. return ret;
  96. }
  97. #define RV1108_PULL_PMU_OFFSET 0x10
  98. #define RV1108_PULL_OFFSET 0x110
  99. static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  100. int pin_num, struct regmap **regmap,
  101. int *reg, u8 *bit)
  102. {
  103. struct rockchip_pinctrl_priv *priv = bank->priv;
  104. /* The first 24 pins of the first bank are located in PMU */
  105. if (bank->bank_num == 0) {
  106. *regmap = priv->regmap_pmu;
  107. *reg = RV1108_PULL_PMU_OFFSET;
  108. } else {
  109. *reg = RV1108_PULL_OFFSET;
  110. *regmap = priv->regmap_base;
  111. /* correct the offset, as we're starting with the 2nd bank */
  112. *reg -= 0x10;
  113. *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
  114. }
  115. *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  116. *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
  117. *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  118. }
  119. static int rv1108_set_pull(struct rockchip_pin_bank *bank,
  120. int pin_num, int pull)
  121. {
  122. struct regmap *regmap;
  123. int reg, ret;
  124. u8 bit, type;
  125. u32 data;
  126. if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
  127. return -ENOTSUPP;
  128. rv1108_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  129. type = bank->pull_type[pin_num / 8];
  130. ret = rockchip_translate_pull_value(type, pull);
  131. if (ret < 0) {
  132. debug("unsupported pull setting %d\n", pull);
  133. return ret;
  134. }
  135. /* enable the write to the equivalent lower bits */
  136. data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
  137. data |= (ret << bit);
  138. ret = regmap_write(regmap, reg, data);
  139. return ret;
  140. }
  141. #define RV1108_DRV_PMU_OFFSET 0x20
  142. #define RV1108_DRV_GRF_OFFSET 0x210
  143. static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  144. int pin_num, struct regmap **regmap,
  145. int *reg, u8 *bit)
  146. {
  147. struct rockchip_pinctrl_priv *priv = bank->priv;
  148. /* The first 24 pins of the first bank are located in PMU */
  149. if (bank->bank_num == 0) {
  150. *regmap = priv->regmap_pmu;
  151. *reg = RV1108_DRV_PMU_OFFSET;
  152. } else {
  153. *regmap = priv->regmap_base;
  154. *reg = RV1108_DRV_GRF_OFFSET;
  155. /* correct the offset, as we're starting with the 2nd bank */
  156. *reg -= 0x10;
  157. *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
  158. }
  159. *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
  160. *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
  161. *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
  162. }
  163. static int rv1108_set_drive(struct rockchip_pin_bank *bank,
  164. int pin_num, int strength)
  165. {
  166. struct regmap *regmap;
  167. int reg, ret;
  168. u32 data;
  169. u8 bit;
  170. int type = bank->drv[pin_num / 8].drv_type;
  171. rv1108_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  172. ret = rockchip_translate_drive_value(type, strength);
  173. if (ret < 0) {
  174. debug("unsupported driver strength %d\n", strength);
  175. return ret;
  176. }
  177. /* enable the write to the equivalent lower bits */
  178. data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
  179. data |= (ret << bit);
  180. ret = regmap_write(regmap, reg, data);
  181. return ret;
  182. }
  183. #define RV1108_SCHMITT_PMU_OFFSET 0x30
  184. #define RV1108_SCHMITT_GRF_OFFSET 0x388
  185. #define RV1108_SCHMITT_BANK_STRIDE 8
  186. #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
  187. #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
  188. static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
  189. int pin_num,
  190. struct regmap **regmap,
  191. int *reg, u8 *bit)
  192. {
  193. struct rockchip_pinctrl_priv *priv = bank->priv;
  194. int pins_per_reg;
  195. if (bank->bank_num == 0) {
  196. *regmap = priv->regmap_pmu;
  197. *reg = RV1108_SCHMITT_PMU_OFFSET;
  198. pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
  199. } else {
  200. *regmap = priv->regmap_base;
  201. *reg = RV1108_SCHMITT_GRF_OFFSET;
  202. pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
  203. *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
  204. }
  205. *reg += ((pin_num / pins_per_reg) * 4);
  206. *bit = pin_num % pins_per_reg;
  207. return 0;
  208. }
  209. static int rv1108_set_schmitt(struct rockchip_pin_bank *bank,
  210. int pin_num, int enable)
  211. {
  212. struct regmap *regmap;
  213. int reg;
  214. u8 bit;
  215. u32 data;
  216. rv1108_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  217. /* enable the write to the equivalent lower bits */
  218. data = BIT(bit + 16) | (enable << bit);
  219. return regmap_write(regmap, reg, data);
  220. }
  221. static struct rockchip_pin_bank rv1108_pin_banks[] = {
  222. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
  223. IOMUX_SOURCE_PMU,
  224. IOMUX_SOURCE_PMU,
  225. IOMUX_SOURCE_PMU),
  226. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
  227. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
  228. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
  229. };
  230. static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
  231. .pin_banks = rv1108_pin_banks,
  232. .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
  233. .grf_mux_offset = 0x10,
  234. .pmu_mux_offset = 0x0,
  235. .iomux_recalced = rv1108_mux_recalced_data,
  236. .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
  237. .set_mux = rv1108_set_mux,
  238. .set_pull = rv1108_set_pull,
  239. .set_drive = rv1108_set_drive,
  240. .set_schmitt = rv1108_set_schmitt,
  241. };
  242. static const struct udevice_id rv1108_pinctrl_ids[] = {
  243. {
  244. .compatible = "rockchip,rv1108-pinctrl",
  245. .data = (ulong)&rv1108_pin_ctrl
  246. },
  247. { }
  248. };
  249. U_BOOT_DRIVER(pinctrl_rv1108) = {
  250. .name = "pinctrl_rv1108",
  251. .id = UCLASS_PINCTRL,
  252. .of_match = rv1108_pinctrl_ids,
  253. .priv_auto = sizeof(struct rockchip_pinctrl_priv),
  254. .ops = &rockchip_pinctrl_ops,
  255. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  256. .bind = dm_scan_fdt_dev,
  257. #endif
  258. .probe = rockchip_pinctrl_probe,
  259. };