pinctrl-rockchip-core.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <dm/pinctrl.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <fdtdec.h>
  12. #include <linux/bitops.h>
  13. #include <linux/libfdt.h>
  14. #include <asm/global_data.h>
  15. #include "pinctrl-rockchip.h"
  16. #define MAX_ROCKCHIP_PINS_ENTRIES 30
  17. #define MAX_ROCKCHIP_GPIO_PER_BANK 32
  18. #define RK_FUNC_GPIO 0
  19. static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
  20. {
  21. struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  22. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  23. if (bank >= ctrl->nr_banks) {
  24. debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
  25. return -EINVAL;
  26. }
  27. if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
  28. debug("pin conf pin %d >= %d\n", pin,
  29. MAX_ROCKCHIP_GPIO_PER_BANK);
  30. return -EINVAL;
  31. }
  32. return 0;
  33. }
  34. void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
  35. int *reg, u8 *bit, int *mask)
  36. {
  37. struct rockchip_pinctrl_priv *priv = bank->priv;
  38. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  39. struct rockchip_mux_recalced_data *data;
  40. int i;
  41. for (i = 0; i < ctrl->niomux_recalced; i++) {
  42. data = &ctrl->iomux_recalced[i];
  43. if (data->num == bank->bank_num &&
  44. data->pin == pin)
  45. break;
  46. }
  47. if (i >= ctrl->niomux_recalced)
  48. return;
  49. *reg = data->reg;
  50. *mask = data->mask;
  51. *bit = data->bit;
  52. }
  53. bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
  54. int mux, u32 *reg, u32 *value)
  55. {
  56. struct rockchip_pinctrl_priv *priv = bank->priv;
  57. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  58. struct rockchip_mux_route_data *data;
  59. int i;
  60. for (i = 0; i < ctrl->niomux_routes; i++) {
  61. data = &ctrl->iomux_routes[i];
  62. if (data->bank_num == bank->bank_num &&
  63. data->pin == pin && data->func == mux)
  64. break;
  65. }
  66. if (i >= ctrl->niomux_routes)
  67. return false;
  68. *reg = data->route_offset;
  69. *value = data->route_val;
  70. return true;
  71. }
  72. int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
  73. {
  74. int offset = 0;
  75. if (mux_type & IOMUX_WIDTH_4BIT) {
  76. if ((pin % 8) >= 4)
  77. offset = 0x4;
  78. *bit = (pin % 4) * 4;
  79. *mask = 0xf;
  80. } else if (mux_type & IOMUX_WIDTH_3BIT) {
  81. /*
  82. * pin0 ~ pin4 are at first register, and
  83. * pin5 ~ pin7 are at second register.
  84. */
  85. if ((pin % 8) >= 5)
  86. offset = 0x4;
  87. *bit = (pin % 8 % 5) * 3;
  88. *mask = 0x7;
  89. } else {
  90. *bit = (pin % 8) * 2;
  91. *mask = 0x3;
  92. }
  93. return offset;
  94. }
  95. static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
  96. {
  97. struct rockchip_pinctrl_priv *priv = bank->priv;
  98. int iomux_num = (pin / 8);
  99. struct regmap *regmap;
  100. unsigned int val;
  101. int reg, ret, mask, mux_type;
  102. u8 bit;
  103. if (iomux_num > 3)
  104. return -EINVAL;
  105. if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
  106. debug("pin %d is unrouted\n", pin);
  107. return -EINVAL;
  108. }
  109. if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
  110. return RK_FUNC_GPIO;
  111. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  112. ? priv->regmap_pmu : priv->regmap_base;
  113. /* get basic quadrupel of mux registers and the correct reg inside */
  114. mux_type = bank->iomux[iomux_num].type;
  115. reg = bank->iomux[iomux_num].offset;
  116. reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  117. if (bank->recalced_mask & BIT(pin))
  118. rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
  119. ret = regmap_read(regmap, reg, &val);
  120. if (ret)
  121. return ret;
  122. return ((val >> bit) & mask);
  123. }
  124. static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
  125. int index)
  126. { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  127. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  128. return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
  129. }
  130. static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
  131. int pin, int mux)
  132. {
  133. int iomux_num = (pin / 8);
  134. if (iomux_num > 3)
  135. return -EINVAL;
  136. if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
  137. debug("pin %d is unrouted\n", pin);
  138. return -EINVAL;
  139. }
  140. if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
  141. if (mux != IOMUX_GPIO_ONLY) {
  142. debug("pin %d only supports a gpio mux\n", pin);
  143. return -ENOTSUPP;
  144. }
  145. }
  146. return 0;
  147. }
  148. /*
  149. * Set a new mux function for a pin.
  150. *
  151. * The register is divided into the upper and lower 16 bit. When changing
  152. * a value, the previous register value is not read and changed. Instead
  153. * it seems the changed bits are marked in the upper 16 bit, while the
  154. * changed value gets set in the same offset in the lower 16 bit.
  155. * All pin settings seem to be 2 bit wide in both the upper and lower
  156. * parts.
  157. * @bank: pin bank to change
  158. * @pin: pin to change
  159. * @mux: new mux function to set
  160. */
  161. static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  162. {
  163. struct rockchip_pinctrl_priv *priv = bank->priv;
  164. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  165. int iomux_num = (pin / 8);
  166. int ret;
  167. ret = rockchip_verify_mux(bank, pin, mux);
  168. if (ret < 0)
  169. return ret;
  170. if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
  171. return 0;
  172. debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
  173. if (!ctrl->set_mux)
  174. return -ENOTSUPP;
  175. ret = ctrl->set_mux(bank, pin, mux);
  176. return ret;
  177. }
  178. static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
  179. { 2, 4, 8, 12, -1, -1, -1, -1 },
  180. { 3, 6, 9, 12, -1, -1, -1, -1 },
  181. { 5, 10, 15, 20, -1, -1, -1, -1 },
  182. { 4, 6, 8, 10, 12, 14, 16, 18 },
  183. { 4, 7, 10, 13, 16, 19, 22, 26 }
  184. };
  185. int rockchip_translate_drive_value(int type, int strength)
  186. {
  187. int i, ret;
  188. ret = -EINVAL;
  189. for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
  190. if (rockchip_perpin_drv_list[type][i] == strength) {
  191. ret = i;
  192. break;
  193. } else if (rockchip_perpin_drv_list[type][i] < 0) {
  194. ret = rockchip_perpin_drv_list[type][i];
  195. break;
  196. }
  197. }
  198. return ret;
  199. }
  200. static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
  201. int pin_num, int strength)
  202. {
  203. struct rockchip_pinctrl_priv *priv = bank->priv;
  204. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  205. debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
  206. pin_num, strength);
  207. if (!ctrl->set_drive)
  208. return -ENOTSUPP;
  209. return ctrl->set_drive(bank, pin_num, strength);
  210. }
  211. static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
  212. {
  213. PIN_CONFIG_BIAS_DISABLE,
  214. PIN_CONFIG_BIAS_PULL_UP,
  215. PIN_CONFIG_BIAS_PULL_DOWN,
  216. PIN_CONFIG_BIAS_BUS_HOLD
  217. },
  218. {
  219. PIN_CONFIG_BIAS_DISABLE,
  220. PIN_CONFIG_BIAS_PULL_DOWN,
  221. PIN_CONFIG_BIAS_DISABLE,
  222. PIN_CONFIG_BIAS_PULL_UP
  223. },
  224. };
  225. int rockchip_translate_pull_value(int type, int pull)
  226. {
  227. int i, ret;
  228. ret = -EINVAL;
  229. for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
  230. i++) {
  231. if (rockchip_pull_list[type][i] == pull) {
  232. ret = i;
  233. break;
  234. }
  235. }
  236. return ret;
  237. }
  238. static int rockchip_set_pull(struct rockchip_pin_bank *bank,
  239. int pin_num, int pull)
  240. {
  241. struct rockchip_pinctrl_priv *priv = bank->priv;
  242. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  243. debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
  244. pin_num, pull);
  245. if (!ctrl->set_pull)
  246. return -ENOTSUPP;
  247. return ctrl->set_pull(bank, pin_num, pull);
  248. }
  249. static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
  250. int pin_num, int enable)
  251. {
  252. struct rockchip_pinctrl_priv *priv = bank->priv;
  253. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  254. debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
  255. pin_num, enable);
  256. if (!ctrl->set_schmitt)
  257. return -ENOTSUPP;
  258. return ctrl->set_schmitt(bank, pin_num, enable);
  259. }
  260. /* set the pin config settings for a specified pin */
  261. static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
  262. u32 pin, u32 param, u32 arg)
  263. {
  264. int rc;
  265. switch (param) {
  266. case PIN_CONFIG_BIAS_DISABLE:
  267. case PIN_CONFIG_BIAS_PULL_UP:
  268. case PIN_CONFIG_BIAS_PULL_DOWN:
  269. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  270. case PIN_CONFIG_BIAS_BUS_HOLD:
  271. rc = rockchip_set_pull(bank, pin, param);
  272. if (rc)
  273. return rc;
  274. break;
  275. case PIN_CONFIG_DRIVE_STRENGTH:
  276. rc = rockchip_set_drive_perpin(bank, pin, arg);
  277. if (rc < 0)
  278. return rc;
  279. break;
  280. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  281. rc = rockchip_set_schmitt(bank, pin, arg);
  282. if (rc < 0)
  283. return rc;
  284. break;
  285. default:
  286. break;
  287. }
  288. return 0;
  289. }
  290. static const struct pinconf_param rockchip_conf_params[] = {
  291. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  292. { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
  293. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
  294. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
  295. { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
  296. { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
  297. { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
  298. { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
  299. };
  300. static int rockchip_pinconf_prop_name_to_param(const char *property,
  301. u32 *default_value)
  302. {
  303. const struct pinconf_param *p, *end;
  304. p = rockchip_conf_params;
  305. end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
  306. /* See if this pctldev supports this parameter */
  307. for (; p < end; p++) {
  308. if (!strcmp(property, p->property)) {
  309. *default_value = p->default_value;
  310. return p->param;
  311. }
  312. }
  313. *default_value = 0;
  314. return -EPERM;
  315. }
  316. static int rockchip_pinctrl_set_state(struct udevice *dev,
  317. struct udevice *config)
  318. {
  319. struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  320. struct rockchip_pin_ctrl *ctrl = priv->ctrl;
  321. u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
  322. u32 bank, pin, mux, conf, arg, default_val;
  323. int ret, count, i;
  324. const char *prop_name;
  325. const void *value;
  326. int prop_len, param;
  327. const u32 *data;
  328. ofnode node;
  329. #ifdef CONFIG_OF_LIVE
  330. const struct device_node *np;
  331. struct property *pp;
  332. #else
  333. int property_offset, pcfg_node;
  334. const void *blob = gd->fdt_blob;
  335. #endif
  336. data = dev_read_prop(config, "rockchip,pins", &count);
  337. if (count < 0) {
  338. debug("%s: bad array size %d\n", __func__, count);
  339. return -EINVAL;
  340. }
  341. count /= sizeof(u32);
  342. if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
  343. debug("%s: unsupported pins array count %d\n",
  344. __func__, count);
  345. return -EINVAL;
  346. }
  347. for (i = 0; i < count; i++)
  348. cells[i] = fdt32_to_cpu(data[i]);
  349. for (i = 0; i < (count >> 2); i++) {
  350. bank = cells[4 * i + 0];
  351. pin = cells[4 * i + 1];
  352. mux = cells[4 * i + 2];
  353. conf = cells[4 * i + 3];
  354. ret = rockchip_verify_config(dev, bank, pin);
  355. if (ret)
  356. return ret;
  357. ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
  358. if (ret)
  359. return ret;
  360. node = ofnode_get_by_phandle(conf);
  361. if (!ofnode_valid(node))
  362. return -ENODEV;
  363. #ifdef CONFIG_OF_LIVE
  364. np = ofnode_to_np(node);
  365. for (pp = np->properties; pp; pp = pp->next) {
  366. prop_name = pp->name;
  367. prop_len = pp->length;
  368. value = pp->value;
  369. #else
  370. pcfg_node = ofnode_to_offset(node);
  371. fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
  372. value = fdt_getprop_by_offset(blob, property_offset,
  373. &prop_name, &prop_len);
  374. if (!value)
  375. return -ENOENT;
  376. #endif
  377. param = rockchip_pinconf_prop_name_to_param(prop_name,
  378. &default_val);
  379. if (param < 0)
  380. break;
  381. if (prop_len >= sizeof(fdt32_t))
  382. arg = fdt32_to_cpu(*(fdt32_t *)value);
  383. else
  384. arg = default_val;
  385. ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
  386. param, arg);
  387. if (ret) {
  388. debug("%s: rockchip_pinconf_set fail: %d\n",
  389. __func__, ret);
  390. return ret;
  391. }
  392. }
  393. }
  394. return 0;
  395. }
  396. const struct pinctrl_ops rockchip_pinctrl_ops = {
  397. .set_state = rockchip_pinctrl_set_state,
  398. .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
  399. };
  400. /* retrieve the soc specific data */
  401. static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
  402. {
  403. struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  404. struct rockchip_pin_ctrl *ctrl =
  405. (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
  406. struct rockchip_pin_bank *bank;
  407. int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
  408. grf_offs = ctrl->grf_mux_offset;
  409. pmu_offs = ctrl->pmu_mux_offset;
  410. drv_pmu_offs = ctrl->pmu_drv_offset;
  411. drv_grf_offs = ctrl->grf_drv_offset;
  412. bank = ctrl->pin_banks;
  413. for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
  414. int bank_pins = 0;
  415. bank->priv = priv;
  416. bank->pin_base = ctrl->nr_pins;
  417. ctrl->nr_pins += bank->nr_pins;
  418. /* calculate iomux and drv offsets */
  419. for (j = 0; j < 4; j++) {
  420. struct rockchip_iomux *iom = &bank->iomux[j];
  421. struct rockchip_drv *drv = &bank->drv[j];
  422. int inc;
  423. if (bank_pins >= bank->nr_pins)
  424. break;
  425. /* preset iomux offset value, set new start value */
  426. if (iom->offset >= 0) {
  427. if (iom->type & IOMUX_SOURCE_PMU)
  428. pmu_offs = iom->offset;
  429. else
  430. grf_offs = iom->offset;
  431. } else { /* set current iomux offset */
  432. iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
  433. pmu_offs : grf_offs;
  434. }
  435. /* preset drv offset value, set new start value */
  436. if (drv->offset >= 0) {
  437. if (iom->type & IOMUX_SOURCE_PMU)
  438. drv_pmu_offs = drv->offset;
  439. else
  440. drv_grf_offs = drv->offset;
  441. } else { /* set current drv offset */
  442. drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
  443. drv_pmu_offs : drv_grf_offs;
  444. }
  445. debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
  446. i, j, iom->offset, drv->offset);
  447. /*
  448. * Increase offset according to iomux width.
  449. * 4bit iomux'es are spread over two registers.
  450. */
  451. inc = (iom->type & (IOMUX_WIDTH_4BIT |
  452. IOMUX_WIDTH_3BIT |
  453. IOMUX_8WIDTH_2BIT)) ? 8 : 4;
  454. if (iom->type & IOMUX_SOURCE_PMU)
  455. pmu_offs += inc;
  456. else
  457. grf_offs += inc;
  458. /*
  459. * Increase offset according to drv width.
  460. * 3bit drive-strenth'es are spread over two registers.
  461. */
  462. if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
  463. (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
  464. inc = 8;
  465. else
  466. inc = 4;
  467. if (iom->type & IOMUX_SOURCE_PMU)
  468. drv_pmu_offs += inc;
  469. else
  470. drv_grf_offs += inc;
  471. bank_pins += 8;
  472. }
  473. /* calculate the per-bank recalced_mask */
  474. for (j = 0; j < ctrl->niomux_recalced; j++) {
  475. int pin = 0;
  476. if (ctrl->iomux_recalced[j].num == bank->bank_num) {
  477. pin = ctrl->iomux_recalced[j].pin;
  478. bank->recalced_mask |= BIT(pin);
  479. }
  480. }
  481. /* calculate the per-bank route_mask */
  482. for (j = 0; j < ctrl->niomux_routes; j++) {
  483. int pin = 0;
  484. if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
  485. pin = ctrl->iomux_routes[j].pin;
  486. bank->route_mask |= BIT(pin);
  487. }
  488. }
  489. }
  490. return ctrl;
  491. }
  492. int rockchip_pinctrl_probe(struct udevice *dev)
  493. {
  494. struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
  495. struct rockchip_pin_ctrl *ctrl;
  496. struct udevice *syscon;
  497. struct regmap *regmap;
  498. int ret = 0;
  499. /* get rockchip grf syscon phandle */
  500. ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
  501. &syscon);
  502. if (ret) {
  503. debug("unable to find rockchip,grf syscon device (%d)\n", ret);
  504. return ret;
  505. }
  506. /* get grf-reg base address */
  507. regmap = syscon_get_regmap(syscon);
  508. if (!regmap) {
  509. debug("unable to find rockchip grf regmap\n");
  510. return -ENODEV;
  511. }
  512. priv->regmap_base = regmap;
  513. /* option: get pmu-reg base address */
  514. ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
  515. &syscon);
  516. if (!ret) {
  517. /* get pmugrf-reg base address */
  518. regmap = syscon_get_regmap(syscon);
  519. if (!regmap) {
  520. debug("unable to find rockchip pmu regmap\n");
  521. return -ENODEV;
  522. }
  523. priv->regmap_pmu = regmap;
  524. }
  525. ctrl = rockchip_pinctrl_get_soc_data(dev);
  526. if (!ctrl) {
  527. debug("driver data not available\n");
  528. return -EINVAL;
  529. }
  530. priv->ctrl = ctrl;
  531. return 0;
  532. }