pinctrl-rk3368.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <dm/pinctrl.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include "pinctrl-rockchip.h"
  12. static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  13. {
  14. struct rockchip_pinctrl_priv *priv = bank->priv;
  15. int iomux_num = (pin / 8);
  16. struct regmap *regmap;
  17. int reg, ret, mask, mux_type;
  18. u8 bit;
  19. u32 data;
  20. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  21. ? priv->regmap_pmu : priv->regmap_base;
  22. /* get basic quadrupel of mux registers and the correct reg inside */
  23. mux_type = bank->iomux[iomux_num].type;
  24. reg = bank->iomux[iomux_num].offset;
  25. reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  26. data = (mask << (bit + 16));
  27. data |= (mux & mask) << bit;
  28. ret = regmap_write(regmap, reg, data);
  29. return ret;
  30. }
  31. #define RK3368_PULL_GRF_OFFSET 0x100
  32. #define RK3368_PULL_PMU_OFFSET 0x10
  33. static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  34. int pin_num, struct regmap **regmap,
  35. int *reg, u8 *bit)
  36. {
  37. struct rockchip_pinctrl_priv *priv = bank->priv;
  38. /* The first 32 pins of the first bank are located in PMU */
  39. if (bank->bank_num == 0) {
  40. *regmap = priv->regmap_pmu;
  41. *reg = RK3368_PULL_PMU_OFFSET;
  42. } else {
  43. *regmap = priv->regmap_base;
  44. *reg = RK3368_PULL_GRF_OFFSET;
  45. /* correct the offset, as we're starting with the 2nd bank */
  46. *reg -= 0x10;
  47. *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
  48. }
  49. *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  50. *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
  51. *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  52. }
  53. static int rk3368_set_pull(struct rockchip_pin_bank *bank,
  54. int pin_num, int pull)
  55. {
  56. struct regmap *regmap;
  57. int reg, ret;
  58. u8 bit, type;
  59. u32 data;
  60. if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
  61. return -ENOTSUPP;
  62. rk3368_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  63. type = bank->pull_type[pin_num / 8];
  64. ret = rockchip_translate_pull_value(type, pull);
  65. if (ret < 0) {
  66. debug("unsupported pull setting %d\n", pull);
  67. return ret;
  68. }
  69. /* enable the write to the equivalent lower bits */
  70. data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
  71. data |= (ret << bit);
  72. ret = regmap_write(regmap, reg, data);
  73. return ret;
  74. }
  75. #define RK3368_DRV_PMU_OFFSET 0x20
  76. #define RK3368_DRV_GRF_OFFSET 0x200
  77. static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  78. int pin_num, struct regmap **regmap,
  79. int *reg, u8 *bit)
  80. {
  81. struct rockchip_pinctrl_priv *priv = bank->priv;
  82. /* The first 32 pins of the first bank are located in PMU */
  83. if (bank->bank_num == 0) {
  84. *regmap = priv->regmap_pmu;
  85. *reg = RK3368_DRV_PMU_OFFSET;
  86. } else {
  87. *regmap = priv->regmap_base;
  88. *reg = RK3368_DRV_GRF_OFFSET;
  89. /* correct the offset, as we're starting with the 2nd bank */
  90. *reg -= 0x10;
  91. *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
  92. }
  93. *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
  94. *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
  95. *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
  96. }
  97. static int rk3368_set_drive(struct rockchip_pin_bank *bank,
  98. int pin_num, int strength)
  99. {
  100. struct regmap *regmap;
  101. int reg, ret;
  102. u32 data;
  103. u8 bit;
  104. int type = bank->drv[pin_num / 8].drv_type;
  105. rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  106. ret = rockchip_translate_drive_value(type, strength);
  107. if (ret < 0) {
  108. debug("unsupported driver strength %d\n", strength);
  109. return ret;
  110. }
  111. /* enable the write to the equivalent lower bits */
  112. data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
  113. data |= (ret << bit);
  114. ret = regmap_write(regmap, reg, data);
  115. return ret;
  116. }
  117. static struct rockchip_pin_bank rk3368_pin_banks[] = {
  118. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
  119. IOMUX_SOURCE_PMU,
  120. IOMUX_SOURCE_PMU,
  121. IOMUX_SOURCE_PMU
  122. ),
  123. PIN_BANK(1, 32, "gpio1"),
  124. PIN_BANK(2, 32, "gpio2"),
  125. PIN_BANK(3, 32, "gpio3"),
  126. };
  127. static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
  128. .pin_banks = rk3368_pin_banks,
  129. .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
  130. .grf_mux_offset = 0x0,
  131. .pmu_mux_offset = 0x0,
  132. .set_mux = rk3368_set_mux,
  133. .set_pull = rk3368_set_pull,
  134. .set_drive = rk3368_set_drive,
  135. };
  136. static const struct udevice_id rk3368_pinctrl_ids[] = {
  137. {
  138. .compatible = "rockchip,rk3368-pinctrl",
  139. .data = (ulong)&rk3368_pin_ctrl
  140. },
  141. { }
  142. };
  143. U_BOOT_DRIVER(rockchip_rk3368_pinctrl) = {
  144. .name = "rockchip_rk3368_pinctrl",
  145. .id = UCLASS_PINCTRL,
  146. .of_match = rk3368_pinctrl_ids,
  147. .priv_auto = sizeof(struct rockchip_pinctrl_priv),
  148. .ops = &rockchip_pinctrl_ops,
  149. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  150. .bind = dm_scan_fdt_dev,
  151. #endif
  152. .probe = rockchip_pinctrl_probe,
  153. };