pinctrl-rk3036.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <dm/pinctrl.h>
  8. #include <regmap.h>
  9. #include <syscon.h>
  10. #include <linux/bitops.h>
  11. #include "pinctrl-rockchip.h"
  12. static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  13. {
  14. struct rockchip_pinctrl_priv *priv = bank->priv;
  15. int iomux_num = (pin / 8);
  16. struct regmap *regmap;
  17. int reg, ret, mask, mux_type;
  18. u8 bit;
  19. u32 data;
  20. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  21. ? priv->regmap_pmu : priv->regmap_base;
  22. /* get basic quadrupel of mux registers and the correct reg inside */
  23. mux_type = bank->iomux[iomux_num].type;
  24. reg = bank->iomux[iomux_num].offset;
  25. reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  26. data = (mask << (bit + 16));
  27. data |= (mux & mask) << bit;
  28. ret = regmap_write(regmap, reg, data);
  29. return ret;
  30. }
  31. #define RK3036_PULL_OFFSET 0x118
  32. #define RK3036_PULL_PINS_PER_REG 16
  33. #define RK3036_PULL_BANK_STRIDE 8
  34. static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  35. int pin_num, struct regmap **regmap,
  36. int *reg, u8 *bit)
  37. {
  38. struct rockchip_pinctrl_priv *priv = bank->priv;
  39. *regmap = priv->regmap_base;
  40. *reg = RK3036_PULL_OFFSET;
  41. *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE;
  42. *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4;
  43. *bit = pin_num % RK3036_PULL_PINS_PER_REG;
  44. };
  45. static int rk3036_set_pull(struct rockchip_pin_bank *bank,
  46. int pin_num, int pull)
  47. {
  48. struct regmap *regmap;
  49. int reg, ret;
  50. u8 bit;
  51. u32 data;
  52. if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
  53. pull != PIN_CONFIG_BIAS_DISABLE)
  54. return -ENOTSUPP;
  55. rk3036_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  56. data = BIT(bit + 16);
  57. if (pull == PIN_CONFIG_BIAS_DISABLE)
  58. data |= BIT(bit);
  59. ret = regmap_write(regmap, reg, data);
  60. return ret;
  61. }
  62. static struct rockchip_pin_bank rk3036_pin_banks[] = {
  63. PIN_BANK(0, 32, "gpio0"),
  64. PIN_BANK(1, 32, "gpio1"),
  65. PIN_BANK(2, 32, "gpio2"),
  66. };
  67. static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
  68. .pin_banks = rk3036_pin_banks,
  69. .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
  70. .grf_mux_offset = 0xa8,
  71. .set_mux = rk3036_set_mux,
  72. .set_pull = rk3036_set_pull,
  73. };
  74. static const struct udevice_id rk3036_pinctrl_ids[] = {
  75. {
  76. .compatible = "rockchip,rk3036-pinctrl",
  77. .data = (ulong)&rk3036_pin_ctrl
  78. },
  79. {}
  80. };
  81. U_BOOT_DRIVER(pinctrl_rockchip) = {
  82. .name = "rk3036-pinctrl",
  83. .id = UCLASS_PINCTRL,
  84. .of_match = rk3036_pinctrl_ids,
  85. .priv_auto = sizeof(struct rockchip_pinctrl_priv),
  86. .ops = &rockchip_pinctrl_ops,
  87. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  88. .bind = dm_scan_fdt_dev,
  89. #endif
  90. .probe = rockchip_pinctrl_probe,
  91. };