pinctrl-px30.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <dm/pinctrl.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <linux/bitops.h>
  12. #include "pinctrl-rockchip.h"
  13. static struct rockchip_mux_route_data px30_mux_route_data[] = {
  14. {
  15. /* cif-d2m0 */
  16. .bank_num = 2,
  17. .pin = 0,
  18. .func = 1,
  19. .route_offset = 0x184,
  20. .route_val = BIT(16 + 7),
  21. }, {
  22. /* cif-d2m1 */
  23. .bank_num = 3,
  24. .pin = 3,
  25. .func = 3,
  26. .route_offset = 0x184,
  27. .route_val = BIT(16 + 7) | BIT(7),
  28. }, {
  29. /* pdm-m0 */
  30. .bank_num = 3,
  31. .pin = 22,
  32. .func = 2,
  33. .route_offset = 0x184,
  34. .route_val = BIT(16 + 8),
  35. }, {
  36. /* pdm-m1 */
  37. .bank_num = 2,
  38. .pin = 22,
  39. .func = 1,
  40. .route_offset = 0x184,
  41. .route_val = BIT(16 + 8) | BIT(8),
  42. }, {
  43. /* uart2-rxm0 */
  44. .bank_num = 1,
  45. .pin = 27,
  46. .func = 2,
  47. .route_offset = 0x184,
  48. .route_val = BIT(16 + 10),
  49. }, {
  50. /* uart2-rxm1 */
  51. .bank_num = 2,
  52. .pin = 14,
  53. .func = 2,
  54. .route_offset = 0x184,
  55. .route_val = BIT(16 + 10) | BIT(10),
  56. }, {
  57. /* uart3-rxm0 */
  58. .bank_num = 0,
  59. .pin = 17,
  60. .func = 2,
  61. .route_offset = 0x184,
  62. .route_val = BIT(16 + 9),
  63. }, {
  64. /* uart3-rxm1 */
  65. .bank_num = 1,
  66. .pin = 15,
  67. .func = 2,
  68. .route_offset = 0x184,
  69. .route_val = BIT(16 + 9) | BIT(9),
  70. },
  71. };
  72. static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  73. {
  74. struct rockchip_pinctrl_priv *priv = bank->priv;
  75. int iomux_num = (pin / 8);
  76. struct regmap *regmap;
  77. int reg, ret, mask, mux_type;
  78. u8 bit;
  79. u32 data, route_reg, route_val;
  80. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  81. ? priv->regmap_pmu : priv->regmap_base;
  82. /* get basic quadrupel of mux registers and the correct reg inside */
  83. mux_type = bank->iomux[iomux_num].type;
  84. reg = bank->iomux[iomux_num].offset;
  85. reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  86. if (bank->route_mask & BIT(pin)) {
  87. if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
  88. &route_val)) {
  89. ret = regmap_write(regmap, route_reg, route_val);
  90. if (ret)
  91. return ret;
  92. }
  93. }
  94. data = (mask << (bit + 16));
  95. data |= (mux & mask) << bit;
  96. ret = regmap_write(regmap, reg, data);
  97. return ret;
  98. }
  99. #define PX30_PULL_PMU_OFFSET 0x10
  100. #define PX30_PULL_GRF_OFFSET 0x60
  101. #define PX30_PULL_BITS_PER_PIN 2
  102. #define PX30_PULL_PINS_PER_REG 8
  103. #define PX30_PULL_BANK_STRIDE 16
  104. static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  105. int pin_num, struct regmap **regmap,
  106. int *reg, u8 *bit)
  107. {
  108. struct rockchip_pinctrl_priv *priv = bank->priv;
  109. /* The first 32 pins of the first bank are located in PMU */
  110. if (bank->bank_num == 0) {
  111. *regmap = priv->regmap_pmu;
  112. *reg = PX30_PULL_PMU_OFFSET;
  113. } else {
  114. *regmap = priv->regmap_base;
  115. *reg = PX30_PULL_GRF_OFFSET;
  116. /* correct the offset, as we're starting with the 2nd bank */
  117. *reg -= 0x10;
  118. *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
  119. }
  120. *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
  121. *bit = (pin_num % PX30_PULL_PINS_PER_REG);
  122. *bit *= PX30_PULL_BITS_PER_PIN;
  123. }
  124. static int px30_set_pull(struct rockchip_pin_bank *bank,
  125. int pin_num, int pull)
  126. {
  127. struct regmap *regmap;
  128. int reg, ret;
  129. u8 bit, type;
  130. u32 data;
  131. if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
  132. return -ENOTSUPP;
  133. px30_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  134. type = bank->pull_type[pin_num / 8];
  135. ret = rockchip_translate_pull_value(type, pull);
  136. if (ret < 0) {
  137. debug("unsupported pull setting %d\n", pull);
  138. return ret;
  139. }
  140. /* enable the write to the equivalent lower bits */
  141. data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
  142. data |= (ret << bit);
  143. ret = regmap_write(regmap, reg, data);
  144. return ret;
  145. }
  146. #define PX30_DRV_PMU_OFFSET 0x20
  147. #define PX30_DRV_GRF_OFFSET 0xf0
  148. #define PX30_DRV_BITS_PER_PIN 2
  149. #define PX30_DRV_PINS_PER_REG 8
  150. #define PX30_DRV_BANK_STRIDE 16
  151. static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  152. int pin_num, struct regmap **regmap,
  153. int *reg, u8 *bit)
  154. {
  155. struct rockchip_pinctrl_priv *priv = bank->priv;
  156. /* The first 32 pins of the first bank are located in PMU */
  157. if (bank->bank_num == 0) {
  158. *regmap = priv->regmap_pmu;
  159. *reg = PX30_DRV_PMU_OFFSET;
  160. } else {
  161. *regmap = priv->regmap_base;
  162. *reg = PX30_DRV_GRF_OFFSET;
  163. /* correct the offset, as we're starting with the 2nd bank */
  164. *reg -= 0x10;
  165. *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
  166. }
  167. *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
  168. *bit = (pin_num % PX30_DRV_PINS_PER_REG);
  169. *bit *= PX30_DRV_BITS_PER_PIN;
  170. }
  171. static int px30_set_drive(struct rockchip_pin_bank *bank,
  172. int pin_num, int strength)
  173. {
  174. struct regmap *regmap;
  175. int reg, ret;
  176. u32 data, rmask_bits, temp;
  177. u8 bit;
  178. int drv_type = bank->drv[pin_num / 8].drv_type;
  179. px30_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  180. ret = rockchip_translate_drive_value(drv_type, strength);
  181. if (ret < 0) {
  182. debug("unsupported driver strength %d\n", strength);
  183. return ret;
  184. }
  185. switch (drv_type) {
  186. case DRV_TYPE_IO_1V8_3V0_AUTO:
  187. case DRV_TYPE_IO_3V3_ONLY:
  188. rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
  189. switch (bit) {
  190. case 0 ... 12:
  191. /* regular case, nothing to do */
  192. break;
  193. case 15:
  194. /*
  195. * drive-strength offset is special, as it is spread
  196. * over 2 registers, the bit data[15] contains bit 0
  197. * of the value while temp[1:0] contains bits 2 and 1
  198. */
  199. data = (ret & 0x1) << 15;
  200. temp = (ret >> 0x1) & 0x3;
  201. data |= BIT(31);
  202. ret = regmap_write(regmap, reg, data);
  203. if (ret)
  204. return ret;
  205. temp |= (0x3 << 16);
  206. reg += 0x4;
  207. ret = regmap_write(regmap, reg, temp);
  208. return ret;
  209. case 18 ... 21:
  210. /* setting fully enclosed in the second register */
  211. reg += 4;
  212. bit -= 16;
  213. break;
  214. default:
  215. debug("unsupported bit: %d for pinctrl drive type: %d\n",
  216. bit, drv_type);
  217. return -EINVAL;
  218. }
  219. break;
  220. case DRV_TYPE_IO_DEFAULT:
  221. case DRV_TYPE_IO_1V8_OR_3V0:
  222. case DRV_TYPE_IO_1V8_ONLY:
  223. rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
  224. break;
  225. default:
  226. debug("unsupported pinctrl drive type: %d\n",
  227. drv_type);
  228. return -EINVAL;
  229. }
  230. /* enable the write to the equivalent lower bits */
  231. data = ((1 << rmask_bits) - 1) << (bit + 16);
  232. data |= (ret << bit);
  233. ret = regmap_write(regmap, reg, data);
  234. return ret;
  235. }
  236. #define PX30_SCHMITT_PMU_OFFSET 0x38
  237. #define PX30_SCHMITT_GRF_OFFSET 0xc0
  238. #define PX30_SCHMITT_PINS_PER_PMU_REG 16
  239. #define PX30_SCHMITT_BANK_STRIDE 16
  240. #define PX30_SCHMITT_PINS_PER_GRF_REG 8
  241. static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
  242. int pin_num,
  243. struct regmap **regmap,
  244. int *reg, u8 *bit)
  245. {
  246. struct rockchip_pinctrl_priv *priv = bank->priv;
  247. int pins_per_reg;
  248. if (bank->bank_num == 0) {
  249. *regmap = priv->regmap_pmu;
  250. *reg = PX30_SCHMITT_PMU_OFFSET;
  251. pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
  252. } else {
  253. *regmap = priv->regmap_base;
  254. *reg = PX30_SCHMITT_GRF_OFFSET;
  255. pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
  256. *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
  257. }
  258. *reg += ((pin_num / pins_per_reg) * 4);
  259. *bit = pin_num % pins_per_reg;
  260. return 0;
  261. }
  262. static int px30_set_schmitt(struct rockchip_pin_bank *bank,
  263. int pin_num, int enable)
  264. {
  265. struct regmap *regmap;
  266. int reg;
  267. u8 bit;
  268. u32 data;
  269. px30_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  270. /* enable the write to the equivalent lower bits */
  271. data = BIT(bit + 16) | (enable << bit);
  272. return regmap_write(regmap, reg, data);
  273. }
  274. static struct rockchip_pin_bank px30_pin_banks[] = {
  275. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
  276. IOMUX_SOURCE_PMU,
  277. IOMUX_SOURCE_PMU,
  278. IOMUX_SOURCE_PMU
  279. ),
  280. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
  281. IOMUX_WIDTH_4BIT,
  282. IOMUX_WIDTH_4BIT,
  283. IOMUX_WIDTH_4BIT
  284. ),
  285. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
  286. IOMUX_WIDTH_4BIT,
  287. IOMUX_WIDTH_4BIT,
  288. IOMUX_WIDTH_4BIT
  289. ),
  290. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
  291. IOMUX_WIDTH_4BIT,
  292. IOMUX_WIDTH_4BIT,
  293. IOMUX_WIDTH_4BIT
  294. ),
  295. };
  296. static struct rockchip_pin_ctrl px30_pin_ctrl = {
  297. .pin_banks = px30_pin_banks,
  298. .nr_banks = ARRAY_SIZE(px30_pin_banks),
  299. .grf_mux_offset = 0x0,
  300. .pmu_mux_offset = 0x0,
  301. .grf_drv_offset = 0xf0,
  302. .pmu_drv_offset = 0x20,
  303. .iomux_routes = px30_mux_route_data,
  304. .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
  305. .set_mux = px30_set_mux,
  306. .set_pull = px30_set_pull,
  307. .set_drive = px30_set_drive,
  308. .set_schmitt = px30_set_schmitt,
  309. };
  310. static const struct udevice_id px30_pinctrl_ids[] = {
  311. {
  312. .compatible = "rockchip,px30-pinctrl",
  313. .data = (ulong)&px30_pin_ctrl
  314. },
  315. { }
  316. };
  317. U_BOOT_DRIVER(pinctrl_px30) = {
  318. .name = "rockchip_px30_pinctrl",
  319. .id = UCLASS_PINCTRL,
  320. .of_match = px30_pinctrl_ids,
  321. .priv_auto = sizeof(struct rockchip_pinctrl_priv),
  322. .ops = &rockchip_pinctrl_ops,
  323. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  324. .bind = dm_scan_fdt_dev,
  325. #endif
  326. .probe = rockchip_pinctrl_probe,
  327. };