pfc-r8a77990.c 157 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A77990 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2018-2019 Renesas Electronics Corp.
  6. *
  7. * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
  8. *
  9. * R8A7796 processor support - PFC hardware block.
  10. *
  11. * Copyright (C) 2016-2017 Renesas Electronics Corp.
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <dm/pinctrl.h>
  17. #include <linux/bitops.h>
  18. #include <linux/kernel.h>
  19. #include "sh_pfc.h"
  20. #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
  21. #define CPU_ALL_GP(fn, sfx) \
  22. PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
  23. PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
  24. PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
  25. PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  26. PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
  27. PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
  28. PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
  29. PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
  30. PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  31. PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
  32. PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
  33. PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
  34. PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
  35. PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
  36. PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
  37. PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
  38. PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
  39. PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
  40. PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
  41. PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
  42. #define CPU_ALL_NOGP(fn) \
  43. PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
  44. PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
  45. PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
  46. PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
  47. PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
  48. PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
  49. PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
  50. PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
  51. PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
  52. PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
  53. PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
  54. PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
  55. PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
  56. PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
  57. PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
  58. PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
  59. /*
  60. * F_() : just information
  61. * FM() : macro for FN_xxx / xxx_MARK
  62. */
  63. /* GPSR0 */
  64. #define GPSR0_17 F_(SDA4, IP7_27_24)
  65. #define GPSR0_16 F_(SCL4, IP7_23_20)
  66. #define GPSR0_15 F_(D15, IP7_19_16)
  67. #define GPSR0_14 F_(D14, IP7_15_12)
  68. #define GPSR0_13 F_(D13, IP7_11_8)
  69. #define GPSR0_12 F_(D12, IP7_7_4)
  70. #define GPSR0_11 F_(D11, IP7_3_0)
  71. #define GPSR0_10 F_(D10, IP6_31_28)
  72. #define GPSR0_9 F_(D9, IP6_27_24)
  73. #define GPSR0_8 F_(D8, IP6_23_20)
  74. #define GPSR0_7 F_(D7, IP6_19_16)
  75. #define GPSR0_6 F_(D6, IP6_15_12)
  76. #define GPSR0_5 F_(D5, IP6_11_8)
  77. #define GPSR0_4 F_(D4, IP6_7_4)
  78. #define GPSR0_3 F_(D3, IP6_3_0)
  79. #define GPSR0_2 F_(D2, IP5_31_28)
  80. #define GPSR0_1 F_(D1, IP5_27_24)
  81. #define GPSR0_0 F_(D0, IP5_23_20)
  82. /* GPSR1 */
  83. #define GPSR1_22 F_(WE0_N, IP5_19_16)
  84. #define GPSR1_21 F_(CS0_N, IP5_15_12)
  85. #define GPSR1_20 FM(CLKOUT)
  86. #define GPSR1_19 F_(A19, IP5_11_8)
  87. #define GPSR1_18 F_(A18, IP5_7_4)
  88. #define GPSR1_17 F_(A17, IP5_3_0)
  89. #define GPSR1_16 F_(A16, IP4_31_28)
  90. #define GPSR1_15 F_(A15, IP4_27_24)
  91. #define GPSR1_14 F_(A14, IP4_23_20)
  92. #define GPSR1_13 F_(A13, IP4_19_16)
  93. #define GPSR1_12 F_(A12, IP4_15_12)
  94. #define GPSR1_11 F_(A11, IP4_11_8)
  95. #define GPSR1_10 F_(A10, IP4_7_4)
  96. #define GPSR1_9 F_(A9, IP4_3_0)
  97. #define GPSR1_8 F_(A8, IP3_31_28)
  98. #define GPSR1_7 F_(A7, IP3_27_24)
  99. #define GPSR1_6 F_(A6, IP3_23_20)
  100. #define GPSR1_5 F_(A5, IP3_19_16)
  101. #define GPSR1_4 F_(A4, IP3_15_12)
  102. #define GPSR1_3 F_(A3, IP3_11_8)
  103. #define GPSR1_2 F_(A2, IP3_7_4)
  104. #define GPSR1_1 F_(A1, IP3_3_0)
  105. #define GPSR1_0 F_(A0, IP2_31_28)
  106. /* GPSR2 */
  107. #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
  108. #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
  109. #define GPSR2_23 F_(RD_N, IP2_19_16)
  110. #define GPSR2_22 F_(BS_N, IP2_15_12)
  111. #define GPSR2_21 FM(AVB_PHY_INT)
  112. #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
  113. #define GPSR2_19 FM(AVB_RD3)
  114. #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
  115. #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
  116. #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
  117. #define GPSR2_15 FM(AVB_RXC)
  118. #define GPSR2_14 FM(AVB_RX_CTL)
  119. #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
  120. #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
  121. #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
  122. #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
  123. #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
  124. #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
  125. #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
  126. #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
  127. #define GPSR2_5 FM(QSPI0_SSL)
  128. #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
  129. #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
  130. #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
  131. #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
  132. #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
  133. /* GPSR3 */
  134. #define GPSR3_15 F_(SD1_WP, IP11_7_4)
  135. #define GPSR3_14 F_(SD1_CD, IP11_3_0)
  136. #define GPSR3_13 F_(SD0_WP, IP10_31_28)
  137. #define GPSR3_12 F_(SD0_CD, IP10_27_24)
  138. #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
  139. #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
  140. #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
  141. #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
  142. #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
  143. #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
  144. #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
  145. #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
  146. #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
  147. #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
  148. #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
  149. #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
  150. /* GPSR4 */
  151. #define GPSR4_10 F_(SD3_DS, IP10_23_20)
  152. #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
  153. #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
  154. #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
  155. #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
  156. #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
  157. #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
  158. #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
  159. #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
  160. #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
  161. #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
  162. /* GPSR5 */
  163. #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
  164. #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
  165. #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
  166. #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
  167. #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
  168. #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
  169. #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
  170. #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
  171. #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
  172. #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
  173. #define GPSR5_9 F_(RX2_A, IP12_15_12)
  174. #define GPSR5_8 F_(TX2_A, IP12_11_8)
  175. #define GPSR5_7 F_(SCK2_A, IP12_7_4)
  176. #define GPSR5_6 F_(TX1, IP12_3_0)
  177. #define GPSR5_5 F_(RX1, IP11_31_28)
  178. #define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
  179. #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
  180. #define GPSR5_2 F_(TX0_A, IP11_15_12)
  181. #define GPSR5_1 F_(RX0_A, IP11_11_8)
  182. #define GPSR5_0 F_(SCK0_A, IP11_27_24)
  183. /* GPSR6 */
  184. #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
  185. #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
  186. #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
  187. #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
  188. #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
  189. #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
  190. #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
  191. #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
  192. #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
  193. #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
  194. #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
  195. #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
  196. #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
  197. #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
  198. #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
  199. #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
  200. #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
  201. #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
  202. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
  203. #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  204. #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  205. #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  206. #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  207. #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  208. #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  209. #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  210. #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  211. #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  212. #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  213. #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  214. #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  215. #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  216. #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  217. #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  218. #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  219. #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  220. #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  221. #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  222. #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  223. #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  224. #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  225. #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  226. #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  227. #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  228. #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  229. #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  230. #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  231. #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  232. #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  233. #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  234. #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  235. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
  236. #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  237. #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  238. #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  239. #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  240. #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  241. #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  242. #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  243. #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  244. #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  245. #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  246. #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  247. #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  248. #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  249. #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  250. #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  251. #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  252. #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  253. #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  254. #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  255. #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  256. #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  257. #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  258. #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  259. #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  260. #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  261. #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  262. #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  263. #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  264. #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  265. #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  266. #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  267. #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  268. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
  269. #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  270. #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  271. #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  272. #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  273. #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  274. #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  275. #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  276. #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  277. #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  278. #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  279. #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  280. #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  281. #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  282. #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  283. #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  284. #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  285. #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  286. #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  287. #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  288. #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  289. #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  290. #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  291. #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  292. #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  293. #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  294. #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  295. #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  296. #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  297. #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  298. #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  299. #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  300. #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  301. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
  302. #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  303. #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  304. #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  305. #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  306. #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  307. #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  308. #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  309. #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  310. #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  311. #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  312. #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  313. #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  314. #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  315. #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  316. #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  317. #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  318. #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  319. #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  320. #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  321. #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  322. #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  323. #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  324. #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  325. #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  326. #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  327. #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  328. #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  329. #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  330. #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  331. #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  332. #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  333. #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  334. #define PINMUX_GPSR \
  335. \
  336. \
  337. \
  338. \
  339. \
  340. \
  341. \
  342. GPSR2_25 \
  343. GPSR2_24 \
  344. GPSR2_23 \
  345. GPSR1_22 GPSR2_22 \
  346. GPSR1_21 GPSR2_21 \
  347. GPSR1_20 GPSR2_20 \
  348. GPSR1_19 GPSR2_19 GPSR5_19 \
  349. GPSR1_18 GPSR2_18 GPSR5_18 \
  350. GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
  351. GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
  352. GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
  353. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
  354. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
  355. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
  356. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
  357. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
  358. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
  359. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
  360. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
  361. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
  362. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
  363. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
  364. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
  365. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
  366. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
  367. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
  368. #define PINMUX_IPSR \
  369. \
  370. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  371. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  372. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  373. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  374. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  375. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  376. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  377. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  378. \
  379. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  380. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  381. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  382. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
  383. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  384. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  385. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  386. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  387. \
  388. FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
  389. FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
  390. FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
  391. FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
  392. FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
  393. FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
  394. FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
  395. FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
  396. \
  397. FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
  398. FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
  399. FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
  400. FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
  401. FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
  402. FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
  403. FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
  404. FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
  405. /* The bit numbering in MOD_SEL fields is reversed */
  406. #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
  407. #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
  408. /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  409. #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
  410. #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
  411. #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
  412. #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
  413. #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
  414. #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
  415. #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
  416. #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
  417. #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
  418. #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
  419. #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
  420. #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  421. #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
  422. #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
  423. #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  424. #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
  425. #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
  426. #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
  427. #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
  428. #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
  429. #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
  430. #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
  431. /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  432. #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
  433. #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
  434. #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
  435. #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
  436. #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
  437. #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
  438. #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
  439. #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
  440. #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
  441. #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
  442. #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
  443. #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
  444. #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
  445. #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
  446. #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
  447. #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
  448. #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
  449. #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
  450. #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
  451. #define PINMUX_MOD_SELS \
  452. \
  453. MOD_SEL1_31 \
  454. MOD_SEL0_30_29 MOD_SEL1_30 \
  455. MOD_SEL1_29 \
  456. MOD_SEL0_28 MOD_SEL1_28 \
  457. MOD_SEL0_27_26 \
  458. MOD_SEL1_26 \
  459. MOD_SEL0_25 MOD_SEL1_25 \
  460. MOD_SEL0_24 MOD_SEL1_24_23_22 \
  461. MOD_SEL0_23 \
  462. MOD_SEL0_22 \
  463. MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
  464. MOD_SEL0_19_18_17 MOD_SEL1_18 \
  465. MOD_SEL1_17 \
  466. MOD_SEL0_16 MOD_SEL1_16 \
  467. MOD_SEL0_15 MOD_SEL1_15 \
  468. MOD_SEL0_14 MOD_SEL1_14_13 \
  469. MOD_SEL0_13_12 \
  470. MOD_SEL1_12_11 \
  471. MOD_SEL0_11_10 \
  472. MOD_SEL1_10_9 \
  473. MOD_SEL0_9 \
  474. MOD_SEL0_8 MOD_SEL1_8 \
  475. MOD_SEL0_7 MOD_SEL1_7 \
  476. MOD_SEL0_6_5 MOD_SEL1_6_5 \
  477. MOD_SEL0_4 MOD_SEL1_4 \
  478. MOD_SEL0_3 \
  479. MOD_SEL0_2 \
  480. MOD_SEL0_1_0
  481. /*
  482. * These pins are not able to be muxed but have other properties
  483. * that can be set, such as pull-up/pull-down enable.
  484. */
  485. #define PINMUX_STATIC \
  486. FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
  487. FM(AVB_TD3) \
  488. FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
  489. FM(ASEBRK) \
  490. FM(MLB_REF)
  491. enum {
  492. PINMUX_RESERVED = 0,
  493. PINMUX_DATA_BEGIN,
  494. GP_ALL(DATA),
  495. PINMUX_DATA_END,
  496. #define F_(x, y)
  497. #define FM(x) FN_##x,
  498. PINMUX_FUNCTION_BEGIN,
  499. GP_ALL(FN),
  500. PINMUX_GPSR
  501. PINMUX_IPSR
  502. PINMUX_MOD_SELS
  503. PINMUX_FUNCTION_END,
  504. #undef F_
  505. #undef FM
  506. #define F_(x, y)
  507. #define FM(x) x##_MARK,
  508. PINMUX_MARK_BEGIN,
  509. PINMUX_GPSR
  510. PINMUX_IPSR
  511. PINMUX_MOD_SELS
  512. PINMUX_STATIC
  513. PINMUX_MARK_END,
  514. #undef F_
  515. #undef FM
  516. };
  517. static const u16 pinmux_data[] = {
  518. PINMUX_DATA_GP_ALL(),
  519. PINMUX_SINGLE(CLKOUT),
  520. PINMUX_SINGLE(AVB_PHY_INT),
  521. PINMUX_SINGLE(AVB_RD3),
  522. PINMUX_SINGLE(AVB_RXC),
  523. PINMUX_SINGLE(AVB_RX_CTL),
  524. PINMUX_SINGLE(QSPI0_SSL),
  525. /* IPSR0 */
  526. PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
  527. PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
  528. PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
  529. PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
  530. PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
  531. PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
  532. PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
  533. PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
  534. PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
  535. PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
  536. PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
  537. PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
  538. PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
  539. PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
  540. PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
  541. PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
  542. PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
  543. PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
  544. PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
  545. PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
  546. PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
  547. PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
  548. /* IPSR1 */
  549. PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
  550. PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
  551. PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
  552. PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
  553. PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
  554. PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
  555. PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
  556. PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
  557. PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
  558. PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
  559. PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
  560. PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
  561. PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
  562. PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
  563. PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
  564. PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
  565. PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
  566. PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
  567. PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
  568. PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
  569. PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
  570. PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
  571. PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
  572. /* IPSR2 */
  573. PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
  574. PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
  575. PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
  576. PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
  577. PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
  578. PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
  579. PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
  580. PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
  581. PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
  582. PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
  583. PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
  584. PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
  585. PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
  586. PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
  587. PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
  588. PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
  589. PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
  590. PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
  591. PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
  592. PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
  593. PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
  594. PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
  595. PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
  596. PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
  597. PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
  598. PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
  599. PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
  600. PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
  601. PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
  602. PINMUX_IPSR_GPSR(IP2_31_28, A0),
  603. PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
  604. PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
  605. PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
  606. PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
  607. PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
  608. PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
  609. PINMUX_IPSR_GPSR(IP2_31_28, IERX),
  610. PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
  611. /* IPSR3 */
  612. PINMUX_IPSR_GPSR(IP3_3_0, A1),
  613. PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
  614. PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
  615. PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
  616. PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
  617. PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
  618. PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
  619. PINMUX_IPSR_GPSR(IP3_3_0, IETX),
  620. PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
  621. PINMUX_IPSR_GPSR(IP3_7_4, A2),
  622. PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
  623. PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
  624. PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
  625. PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
  626. PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
  627. PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
  628. PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
  629. PINMUX_IPSR_GPSR(IP3_11_8, A3),
  630. PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
  631. PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
  632. PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
  633. PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
  634. PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
  635. PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
  636. PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
  637. PINMUX_IPSR_GPSR(IP3_15_12, A4),
  638. PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
  639. PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
  640. PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
  641. PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
  642. PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
  643. PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
  644. PINMUX_IPSR_GPSR(IP3_19_16, A5),
  645. PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
  646. PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
  647. PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
  648. PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
  649. PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
  650. PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
  651. PINMUX_IPSR_GPSR(IP3_23_20, A6),
  652. PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
  653. PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
  654. PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
  655. PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
  656. PINMUX_IPSR_GPSR(IP3_27_24, A7),
  657. PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
  658. PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
  659. PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
  660. PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
  661. PINMUX_IPSR_GPSR(IP3_31_28, A8),
  662. PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
  663. PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
  664. PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
  665. PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
  666. PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
  667. PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
  668. PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
  669. /* IPSR4 */
  670. PINMUX_IPSR_GPSR(IP4_3_0, A9),
  671. PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
  672. PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
  673. PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
  674. PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
  675. PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
  676. PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
  677. PINMUX_IPSR_GPSR(IP4_7_4, A10),
  678. PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
  679. PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
  680. PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
  681. PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
  682. PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
  683. PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
  684. PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
  685. PINMUX_IPSR_GPSR(IP4_11_8, A11),
  686. PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
  687. PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
  688. PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
  689. PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
  690. PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
  691. PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
  692. PINMUX_IPSR_GPSR(IP4_15_12, A12),
  693. PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
  694. PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
  695. PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
  696. PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
  697. PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
  698. PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
  699. PINMUX_IPSR_GPSR(IP4_19_16, A13),
  700. PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
  701. PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
  702. PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
  703. PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
  704. PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
  705. PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
  706. PINMUX_IPSR_GPSR(IP4_23_20, A14),
  707. PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
  708. PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
  709. PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
  710. PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
  711. PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
  712. PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
  713. PINMUX_IPSR_GPSR(IP4_27_24, A15),
  714. PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
  715. PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
  716. PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
  717. PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
  718. PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
  719. PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
  720. PINMUX_IPSR_GPSR(IP4_31_28, A16),
  721. PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
  722. PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
  723. PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
  724. PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
  725. PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
  726. PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
  727. /* IPSR5 */
  728. PINMUX_IPSR_GPSR(IP5_3_0, A17),
  729. PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
  730. PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
  731. PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
  732. PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
  733. PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
  734. PINMUX_IPSR_GPSR(IP5_7_4, A18),
  735. PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
  736. PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
  737. PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
  738. PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
  739. PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
  740. PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
  741. PINMUX_IPSR_GPSR(IP5_11_8, A19),
  742. PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
  743. PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
  744. PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
  745. PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
  746. PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
  747. PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
  748. PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
  749. PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
  750. PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
  751. PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
  752. PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
  753. PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
  754. PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
  755. PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
  756. PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
  757. PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
  758. PINMUX_IPSR_GPSR(IP5_23_20, D0),
  759. PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
  760. PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
  761. PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
  762. PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
  763. PINMUX_IPSR_GPSR(IP5_27_24, D1),
  764. PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
  765. PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
  766. PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
  767. PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
  768. PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
  769. PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
  770. PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
  771. PINMUX_IPSR_GPSR(IP5_31_28, D2),
  772. PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
  773. PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
  774. PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
  775. PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
  776. PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
  777. PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
  778. /* IPSR6 */
  779. PINMUX_IPSR_GPSR(IP6_3_0, D3),
  780. PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
  781. PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
  782. PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
  783. PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
  784. PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
  785. PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
  786. PINMUX_IPSR_GPSR(IP6_7_4, D4),
  787. PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
  788. PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
  789. PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
  790. PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
  791. PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
  792. PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
  793. PINMUX_IPSR_GPSR(IP6_11_8, D5),
  794. PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
  795. PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
  796. PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
  797. PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
  798. PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
  799. PINMUX_IPSR_GPSR(IP6_15_12, D6),
  800. PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
  801. PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
  802. PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
  803. PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
  804. PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
  805. PINMUX_IPSR_GPSR(IP6_19_16, D7),
  806. PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
  807. PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
  808. PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
  809. PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
  810. PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
  811. PINMUX_IPSR_GPSR(IP6_23_20, D8),
  812. PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
  813. PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
  814. PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
  815. PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
  816. PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
  817. PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
  818. PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
  819. PINMUX_IPSR_GPSR(IP6_27_24, D9),
  820. PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
  821. PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
  822. PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
  823. PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
  824. PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
  825. PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
  826. PINMUX_IPSR_GPSR(IP6_31_28, D10),
  827. PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
  828. PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
  829. PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
  830. PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
  831. PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
  832. PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
  833. /* IPSR7 */
  834. PINMUX_IPSR_GPSR(IP7_3_0, D11),
  835. PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
  836. PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
  837. PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
  838. PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
  839. PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
  840. PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
  841. PINMUX_IPSR_GPSR(IP7_7_4, D12),
  842. PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
  843. PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
  844. PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
  845. PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
  846. PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
  847. PINMUX_IPSR_GPSR(IP7_11_8, D13),
  848. PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
  849. PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
  850. PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
  851. PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
  852. PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
  853. PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
  854. PINMUX_IPSR_GPSR(IP7_15_12, D14),
  855. PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
  856. PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
  857. PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
  858. PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
  859. PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
  860. PINMUX_IPSR_GPSR(IP7_19_16, D15),
  861. PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
  862. PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
  863. PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
  864. PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
  865. PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
  866. PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
  867. PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
  868. PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
  869. PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
  870. PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
  871. PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
  872. PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
  873. PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
  874. PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
  875. PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
  876. PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
  877. PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
  878. PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
  879. PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
  880. PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
  881. PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
  882. PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
  883. /* IPSR8 */
  884. PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
  885. PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
  886. PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
  887. PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
  888. PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
  889. PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
  890. PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
  891. PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
  892. PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
  893. PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
  894. PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
  895. PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
  896. PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
  897. PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
  898. PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
  899. PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
  900. PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
  901. PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
  902. PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
  903. PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
  904. PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
  905. PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
  906. PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
  907. PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
  908. PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
  909. PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
  910. PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
  911. PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
  912. PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
  913. PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
  914. /* IPSR9 */
  915. PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
  916. PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
  917. PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
  918. PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
  919. PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
  920. PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
  921. PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
  922. PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
  923. PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
  924. PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
  925. PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
  926. PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
  927. PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
  928. PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
  929. PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
  930. PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
  931. /* IPSR10 */
  932. PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
  933. PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
  934. PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
  935. PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
  936. PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
  937. PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
  938. PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
  939. PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
  940. PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
  941. PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
  942. PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
  943. PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
  944. PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
  945. PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
  946. PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
  947. PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
  948. PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
  949. PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
  950. PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
  951. PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
  952. PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
  953. PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
  954. PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
  955. PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
  956. PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
  957. PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
  958. PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
  959. PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
  960. /* IPSR11 */
  961. PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
  962. PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
  963. PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
  964. PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
  965. PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
  966. PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
  967. PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
  968. PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
  969. PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
  970. PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
  971. PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
  972. PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
  973. PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
  974. PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
  975. PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
  976. PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
  977. PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
  978. PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
  979. PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
  980. PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
  981. PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
  982. PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
  983. PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
  984. PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
  985. PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
  986. PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
  987. PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
  988. PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
  989. PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
  990. PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
  991. PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
  992. PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
  993. PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
  994. PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
  995. PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
  996. PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
  997. PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
  998. PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
  999. PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
  1000. PINMUX_IPSR_GPSR(IP11_31_28, RX1),
  1001. PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
  1002. PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
  1003. PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
  1004. /* IPSR12 */
  1005. PINMUX_IPSR_GPSR(IP12_3_0, TX1),
  1006. PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
  1007. PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
  1008. PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
  1009. PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
  1010. PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
  1011. PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
  1012. PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
  1013. PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
  1014. PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
  1015. PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
  1016. PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
  1017. PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
  1018. PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
  1019. PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
  1020. PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
  1021. PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
  1022. PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
  1023. PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
  1024. PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
  1025. PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
  1026. PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
  1027. PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
  1028. PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
  1029. PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
  1030. PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
  1031. PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
  1032. PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
  1033. PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
  1034. PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
  1035. PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
  1036. PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
  1037. PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
  1038. PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
  1039. /* IPSR13 */
  1040. PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
  1041. PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
  1042. PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
  1043. PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
  1044. PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
  1045. PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
  1046. PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
  1047. PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
  1048. PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
  1049. PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
  1050. PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
  1051. PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
  1052. PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
  1053. PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
  1054. PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
  1055. PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
  1056. PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
  1057. PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
  1058. PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
  1059. PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
  1060. PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
  1061. PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
  1062. PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
  1063. PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
  1064. PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
  1065. PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
  1066. PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
  1067. PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
  1068. PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
  1069. PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
  1070. PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
  1071. PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
  1072. PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
  1073. /* IPSR14 */
  1074. PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
  1075. PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
  1076. PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
  1077. PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
  1078. PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
  1079. PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
  1080. PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
  1081. PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
  1082. PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
  1083. PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
  1084. PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
  1085. PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
  1086. PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
  1087. PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
  1088. PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
  1089. PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
  1090. PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
  1091. PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
  1092. PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
  1093. PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
  1094. PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
  1095. PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
  1096. PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
  1097. PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
  1098. /* IPSR15 */
  1099. PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
  1100. PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
  1101. PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
  1102. PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
  1103. PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
  1104. PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
  1105. PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
  1106. PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
  1107. PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
  1108. PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
  1109. PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
  1110. PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
  1111. PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
  1112. PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
  1113. PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
  1114. PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
  1115. PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
  1116. PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
  1117. PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
  1118. PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
  1119. PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
  1120. PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
  1121. PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
  1122. PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
  1123. PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
  1124. PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
  1125. PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
  1126. PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
  1127. PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
  1128. PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
  1129. PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
  1130. PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
  1131. PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
  1132. /*
  1133. * Static pins can not be muxed between different functions but
  1134. * still need mark entries in the pinmux list. Add each static
  1135. * pin to the list without an associated function. The sh-pfc
  1136. * core will do the right thing and skip trying to mux the pin
  1137. * while still applying configuration to it.
  1138. */
  1139. #define FM(x) PINMUX_DATA(x##_MARK, 0),
  1140. PINMUX_STATIC
  1141. #undef FM
  1142. };
  1143. /*
  1144. * Pins not associated with a GPIO port.
  1145. */
  1146. enum {
  1147. GP_ASSIGN_LAST(),
  1148. NOGP_ALL(),
  1149. };
  1150. static const struct sh_pfc_pin pinmux_pins[] = {
  1151. PINMUX_GPIO_GP_ALL(),
  1152. PINMUX_NOGP_ALL(),
  1153. };
  1154. /* - AUDIO CLOCK ------------------------------------------------------------ */
  1155. static const unsigned int audio_clk_a_pins[] = {
  1156. /* CLK A */
  1157. RCAR_GP_PIN(6, 8),
  1158. };
  1159. static const unsigned int audio_clk_a_mux[] = {
  1160. AUDIO_CLKA_MARK,
  1161. };
  1162. static const unsigned int audio_clk_b_a_pins[] = {
  1163. /* CLK B_A */
  1164. RCAR_GP_PIN(5, 7),
  1165. };
  1166. static const unsigned int audio_clk_b_a_mux[] = {
  1167. AUDIO_CLKB_A_MARK,
  1168. };
  1169. static const unsigned int audio_clk_b_b_pins[] = {
  1170. /* CLK B_B */
  1171. RCAR_GP_PIN(6, 7),
  1172. };
  1173. static const unsigned int audio_clk_b_b_mux[] = {
  1174. AUDIO_CLKB_B_MARK,
  1175. };
  1176. static const unsigned int audio_clk_b_c_pins[] = {
  1177. /* CLK B_C */
  1178. RCAR_GP_PIN(6, 13),
  1179. };
  1180. static const unsigned int audio_clk_b_c_mux[] = {
  1181. AUDIO_CLKB_C_MARK,
  1182. };
  1183. static const unsigned int audio_clk_c_a_pins[] = {
  1184. /* CLK C_A */
  1185. RCAR_GP_PIN(5, 16),
  1186. };
  1187. static const unsigned int audio_clk_c_a_mux[] = {
  1188. AUDIO_CLKC_A_MARK,
  1189. };
  1190. static const unsigned int audio_clk_c_b_pins[] = {
  1191. /* CLK C_B */
  1192. RCAR_GP_PIN(6, 3),
  1193. };
  1194. static const unsigned int audio_clk_c_b_mux[] = {
  1195. AUDIO_CLKC_B_MARK,
  1196. };
  1197. static const unsigned int audio_clk_c_c_pins[] = {
  1198. /* CLK C_C */
  1199. RCAR_GP_PIN(6, 14),
  1200. };
  1201. static const unsigned int audio_clk_c_c_mux[] = {
  1202. AUDIO_CLKC_C_MARK,
  1203. };
  1204. static const unsigned int audio_clkout_a_pins[] = {
  1205. /* CLKOUT_A */
  1206. RCAR_GP_PIN(5, 3),
  1207. };
  1208. static const unsigned int audio_clkout_a_mux[] = {
  1209. AUDIO_CLKOUT_A_MARK,
  1210. };
  1211. static const unsigned int audio_clkout_b_pins[] = {
  1212. /* CLKOUT_B */
  1213. RCAR_GP_PIN(5, 13),
  1214. };
  1215. static const unsigned int audio_clkout_b_mux[] = {
  1216. AUDIO_CLKOUT_B_MARK,
  1217. };
  1218. static const unsigned int audio_clkout1_a_pins[] = {
  1219. /* CLKOUT1_A */
  1220. RCAR_GP_PIN(5, 4),
  1221. };
  1222. static const unsigned int audio_clkout1_a_mux[] = {
  1223. AUDIO_CLKOUT1_A_MARK,
  1224. };
  1225. static const unsigned int audio_clkout1_b_pins[] = {
  1226. /* CLKOUT1_B */
  1227. RCAR_GP_PIN(5, 5),
  1228. };
  1229. static const unsigned int audio_clkout1_b_mux[] = {
  1230. AUDIO_CLKOUT1_B_MARK,
  1231. };
  1232. static const unsigned int audio_clkout1_c_pins[] = {
  1233. /* CLKOUT1_C */
  1234. RCAR_GP_PIN(6, 7),
  1235. };
  1236. static const unsigned int audio_clkout1_c_mux[] = {
  1237. AUDIO_CLKOUT1_C_MARK,
  1238. };
  1239. static const unsigned int audio_clkout2_a_pins[] = {
  1240. /* CLKOUT2_A */
  1241. RCAR_GP_PIN(5, 8),
  1242. };
  1243. static const unsigned int audio_clkout2_a_mux[] = {
  1244. AUDIO_CLKOUT2_A_MARK,
  1245. };
  1246. static const unsigned int audio_clkout2_b_pins[] = {
  1247. /* CLKOUT2_B */
  1248. RCAR_GP_PIN(6, 4),
  1249. };
  1250. static const unsigned int audio_clkout2_b_mux[] = {
  1251. AUDIO_CLKOUT2_B_MARK,
  1252. };
  1253. static const unsigned int audio_clkout2_c_pins[] = {
  1254. /* CLKOUT2_C */
  1255. RCAR_GP_PIN(6, 15),
  1256. };
  1257. static const unsigned int audio_clkout2_c_mux[] = {
  1258. AUDIO_CLKOUT2_C_MARK,
  1259. };
  1260. static const unsigned int audio_clkout3_a_pins[] = {
  1261. /* CLKOUT3_A */
  1262. RCAR_GP_PIN(5, 9),
  1263. };
  1264. static const unsigned int audio_clkout3_a_mux[] = {
  1265. AUDIO_CLKOUT3_A_MARK,
  1266. };
  1267. static const unsigned int audio_clkout3_b_pins[] = {
  1268. /* CLKOUT3_B */
  1269. RCAR_GP_PIN(5, 6),
  1270. };
  1271. static const unsigned int audio_clkout3_b_mux[] = {
  1272. AUDIO_CLKOUT3_B_MARK,
  1273. };
  1274. static const unsigned int audio_clkout3_c_pins[] = {
  1275. /* CLKOUT3_C */
  1276. RCAR_GP_PIN(6, 16),
  1277. };
  1278. static const unsigned int audio_clkout3_c_mux[] = {
  1279. AUDIO_CLKOUT3_C_MARK,
  1280. };
  1281. /* - EtherAVB --------------------------------------------------------------- */
  1282. static const unsigned int avb_link_pins[] = {
  1283. /* AVB_LINK */
  1284. RCAR_GP_PIN(2, 23),
  1285. };
  1286. static const unsigned int avb_link_mux[] = {
  1287. AVB_LINK_MARK,
  1288. };
  1289. static const unsigned int avb_magic_pins[] = {
  1290. /* AVB_MAGIC */
  1291. RCAR_GP_PIN(2, 22),
  1292. };
  1293. static const unsigned int avb_magic_mux[] = {
  1294. AVB_MAGIC_MARK,
  1295. };
  1296. static const unsigned int avb_phy_int_pins[] = {
  1297. /* AVB_PHY_INT */
  1298. RCAR_GP_PIN(2, 21),
  1299. };
  1300. static const unsigned int avb_phy_int_mux[] = {
  1301. AVB_PHY_INT_MARK,
  1302. };
  1303. static const unsigned int avb_mii_pins[] = {
  1304. /*
  1305. * AVB_RX_CTL, AVB_RXC, AVB_RD0,
  1306. * AVB_RD1, AVB_RD2, AVB_RD3,
  1307. * AVB_TXCREFCLK
  1308. */
  1309. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
  1310. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
  1311. RCAR_GP_PIN(2, 20),
  1312. };
  1313. static const unsigned int avb_mii_mux[] = {
  1314. AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
  1315. AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
  1316. AVB_TXCREFCLK_MARK,
  1317. };
  1318. static const unsigned int avb_avtp_pps_pins[] = {
  1319. /* AVB_AVTP_PPS */
  1320. RCAR_GP_PIN(1, 2),
  1321. };
  1322. static const unsigned int avb_avtp_pps_mux[] = {
  1323. AVB_AVTP_PPS_MARK,
  1324. };
  1325. static const unsigned int avb_avtp_match_pins[] = {
  1326. /* AVB_AVTP_MATCH */
  1327. RCAR_GP_PIN(2, 24),
  1328. };
  1329. static const unsigned int avb_avtp_match_mux[] = {
  1330. AVB_AVTP_MATCH_MARK,
  1331. };
  1332. static const unsigned int avb_avtp_capture_pins[] = {
  1333. /* AVB_AVTP_CAPTURE */
  1334. RCAR_GP_PIN(2, 25),
  1335. };
  1336. static const unsigned int avb_avtp_capture_mux[] = {
  1337. AVB_AVTP_CAPTURE_MARK,
  1338. };
  1339. /* - CAN ------------------------------------------------------------------ */
  1340. static const unsigned int can0_data_pins[] = {
  1341. /* TX, RX */
  1342. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  1343. };
  1344. static const unsigned int can0_data_mux[] = {
  1345. CAN0_TX_MARK, CAN0_RX_MARK,
  1346. };
  1347. static const unsigned int can1_data_pins[] = {
  1348. /* TX, RX */
  1349. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
  1350. };
  1351. static const unsigned int can1_data_mux[] = {
  1352. CAN1_TX_MARK, CAN1_RX_MARK,
  1353. };
  1354. /* - CAN Clock -------------------------------------------------------------- */
  1355. static const unsigned int can_clk_pins[] = {
  1356. /* CLK */
  1357. RCAR_GP_PIN(0, 14),
  1358. };
  1359. static const unsigned int can_clk_mux[] = {
  1360. CAN_CLK_MARK,
  1361. };
  1362. /* - CAN FD --------------------------------------------------------------- */
  1363. static const unsigned int canfd0_data_pins[] = {
  1364. /* TX, RX */
  1365. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  1366. };
  1367. static const unsigned int canfd0_data_mux[] = {
  1368. CANFD0_TX_MARK, CANFD0_RX_MARK,
  1369. };
  1370. static const unsigned int canfd1_data_pins[] = {
  1371. /* TX, RX */
  1372. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
  1373. };
  1374. static const unsigned int canfd1_data_mux[] = {
  1375. CANFD1_TX_MARK, CANFD1_RX_MARK,
  1376. };
  1377. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  1378. /* - DRIF0 --------------------------------------------------------------- */
  1379. static const unsigned int drif0_ctrl_a_pins[] = {
  1380. /* CLK, SYNC */
  1381. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
  1382. };
  1383. static const unsigned int drif0_ctrl_a_mux[] = {
  1384. RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
  1385. };
  1386. static const unsigned int drif0_data0_a_pins[] = {
  1387. /* D0 */
  1388. RCAR_GP_PIN(5, 17),
  1389. };
  1390. static const unsigned int drif0_data0_a_mux[] = {
  1391. RIF0_D0_A_MARK,
  1392. };
  1393. static const unsigned int drif0_data1_a_pins[] = {
  1394. /* D1 */
  1395. RCAR_GP_PIN(5, 18),
  1396. };
  1397. static const unsigned int drif0_data1_a_mux[] = {
  1398. RIF0_D1_A_MARK,
  1399. };
  1400. static const unsigned int drif0_ctrl_b_pins[] = {
  1401. /* CLK, SYNC */
  1402. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
  1403. };
  1404. static const unsigned int drif0_ctrl_b_mux[] = {
  1405. RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
  1406. };
  1407. static const unsigned int drif0_data0_b_pins[] = {
  1408. /* D0 */
  1409. RCAR_GP_PIN(3, 13),
  1410. };
  1411. static const unsigned int drif0_data0_b_mux[] = {
  1412. RIF0_D0_B_MARK,
  1413. };
  1414. static const unsigned int drif0_data1_b_pins[] = {
  1415. /* D1 */
  1416. RCAR_GP_PIN(3, 14),
  1417. };
  1418. static const unsigned int drif0_data1_b_mux[] = {
  1419. RIF0_D1_B_MARK,
  1420. };
  1421. /* - DRIF1 --------------------------------------------------------------- */
  1422. static const unsigned int drif1_ctrl_pins[] = {
  1423. /* CLK, SYNC */
  1424. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
  1425. };
  1426. static const unsigned int drif1_ctrl_mux[] = {
  1427. RIF1_CLK_MARK, RIF1_SYNC_MARK,
  1428. };
  1429. static const unsigned int drif1_data0_pins[] = {
  1430. /* D0 */
  1431. RCAR_GP_PIN(5, 2),
  1432. };
  1433. static const unsigned int drif1_data0_mux[] = {
  1434. RIF1_D0_MARK,
  1435. };
  1436. static const unsigned int drif1_data1_pins[] = {
  1437. /* D1 */
  1438. RCAR_GP_PIN(5, 3),
  1439. };
  1440. static const unsigned int drif1_data1_mux[] = {
  1441. RIF1_D1_MARK,
  1442. };
  1443. /* - DRIF2 --------------------------------------------------------------- */
  1444. static const unsigned int drif2_ctrl_a_pins[] = {
  1445. /* CLK, SYNC */
  1446. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  1447. };
  1448. static const unsigned int drif2_ctrl_a_mux[] = {
  1449. RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
  1450. };
  1451. static const unsigned int drif2_data0_a_pins[] = {
  1452. /* D0 */
  1453. RCAR_GP_PIN(2, 8),
  1454. };
  1455. static const unsigned int drif2_data0_a_mux[] = {
  1456. RIF2_D0_A_MARK,
  1457. };
  1458. static const unsigned int drif2_data1_a_pins[] = {
  1459. /* D1 */
  1460. RCAR_GP_PIN(2, 9),
  1461. };
  1462. static const unsigned int drif2_data1_a_mux[] = {
  1463. RIF2_D1_A_MARK,
  1464. };
  1465. static const unsigned int drif2_ctrl_b_pins[] = {
  1466. /* CLK, SYNC */
  1467. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  1468. };
  1469. static const unsigned int drif2_ctrl_b_mux[] = {
  1470. RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
  1471. };
  1472. static const unsigned int drif2_data0_b_pins[] = {
  1473. /* D0 */
  1474. RCAR_GP_PIN(1, 6),
  1475. };
  1476. static const unsigned int drif2_data0_b_mux[] = {
  1477. RIF2_D0_B_MARK,
  1478. };
  1479. static const unsigned int drif2_data1_b_pins[] = {
  1480. /* D1 */
  1481. RCAR_GP_PIN(1, 7),
  1482. };
  1483. static const unsigned int drif2_data1_b_mux[] = {
  1484. RIF2_D1_B_MARK,
  1485. };
  1486. /* - DRIF3 --------------------------------------------------------------- */
  1487. static const unsigned int drif3_ctrl_a_pins[] = {
  1488. /* CLK, SYNC */
  1489. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  1490. };
  1491. static const unsigned int drif3_ctrl_a_mux[] = {
  1492. RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
  1493. };
  1494. static const unsigned int drif3_data0_a_pins[] = {
  1495. /* D0 */
  1496. RCAR_GP_PIN(2, 12),
  1497. };
  1498. static const unsigned int drif3_data0_a_mux[] = {
  1499. RIF3_D0_A_MARK,
  1500. };
  1501. static const unsigned int drif3_data1_a_pins[] = {
  1502. /* D1 */
  1503. RCAR_GP_PIN(2, 13),
  1504. };
  1505. static const unsigned int drif3_data1_a_mux[] = {
  1506. RIF3_D1_A_MARK,
  1507. };
  1508. static const unsigned int drif3_ctrl_b_pins[] = {
  1509. /* CLK, SYNC */
  1510. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  1511. };
  1512. static const unsigned int drif3_ctrl_b_mux[] = {
  1513. RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
  1514. };
  1515. static const unsigned int drif3_data0_b_pins[] = {
  1516. /* D0 */
  1517. RCAR_GP_PIN(0, 10),
  1518. };
  1519. static const unsigned int drif3_data0_b_mux[] = {
  1520. RIF3_D0_B_MARK,
  1521. };
  1522. static const unsigned int drif3_data1_b_pins[] = {
  1523. /* D1 */
  1524. RCAR_GP_PIN(0, 11),
  1525. };
  1526. static const unsigned int drif3_data1_b_mux[] = {
  1527. RIF3_D1_B_MARK,
  1528. };
  1529. #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
  1530. /* - DU --------------------------------------------------------------------- */
  1531. static const unsigned int du_rgb666_pins[] = {
  1532. /* R[7:2], G[7:2], B[7:2] */
  1533. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
  1534. RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
  1535. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
  1536. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
  1537. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  1538. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1539. };
  1540. static const unsigned int du_rgb666_mux[] = {
  1541. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1542. DU_DR3_MARK, DU_DR2_MARK,
  1543. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1544. DU_DG3_MARK, DU_DG2_MARK,
  1545. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1546. DU_DB3_MARK, DU_DB2_MARK,
  1547. };
  1548. static const unsigned int du_rgb888_pins[] = {
  1549. /* R[7:0], G[7:0], B[7:0] */
  1550. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
  1551. RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
  1552. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
  1553. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
  1554. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
  1555. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
  1556. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  1557. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1558. RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1559. };
  1560. static const unsigned int du_rgb888_mux[] = {
  1561. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1562. DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
  1563. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1564. DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
  1565. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1566. DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
  1567. };
  1568. static const unsigned int du_clk_in_0_pins[] = {
  1569. /* CLKIN0 */
  1570. RCAR_GP_PIN(0, 16),
  1571. };
  1572. static const unsigned int du_clk_in_0_mux[] = {
  1573. DU_DOTCLKIN0_MARK
  1574. };
  1575. static const unsigned int du_clk_in_1_pins[] = {
  1576. /* CLKIN1 */
  1577. RCAR_GP_PIN(1, 1),
  1578. };
  1579. static const unsigned int du_clk_in_1_mux[] = {
  1580. DU_DOTCLKIN1_MARK
  1581. };
  1582. static const unsigned int du_clk_out_0_pins[] = {
  1583. /* CLKOUT */
  1584. RCAR_GP_PIN(1, 3),
  1585. };
  1586. static const unsigned int du_clk_out_0_mux[] = {
  1587. DU_DOTCLKOUT0_MARK
  1588. };
  1589. static const unsigned int du_sync_pins[] = {
  1590. /* VSYNC, HSYNC */
  1591. RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
  1592. };
  1593. static const unsigned int du_sync_mux[] = {
  1594. DU_VSYNC_MARK, DU_HSYNC_MARK
  1595. };
  1596. static const unsigned int du_disp_cde_pins[] = {
  1597. /* DISP_CDE */
  1598. RCAR_GP_PIN(1, 1),
  1599. };
  1600. static const unsigned int du_disp_cde_mux[] = {
  1601. DU_DISP_CDE_MARK,
  1602. };
  1603. static const unsigned int du_cde_pins[] = {
  1604. /* CDE */
  1605. RCAR_GP_PIN(1, 0),
  1606. };
  1607. static const unsigned int du_cde_mux[] = {
  1608. DU_CDE_MARK,
  1609. };
  1610. static const unsigned int du_disp_pins[] = {
  1611. /* DISP */
  1612. RCAR_GP_PIN(1, 2),
  1613. };
  1614. static const unsigned int du_disp_mux[] = {
  1615. DU_DISP_MARK,
  1616. };
  1617. /* - HSCIF0 --------------------------------------------------*/
  1618. static const unsigned int hscif0_data_a_pins[] = {
  1619. /* RX, TX */
  1620. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
  1621. };
  1622. static const unsigned int hscif0_data_a_mux[] = {
  1623. HRX0_A_MARK, HTX0_A_MARK,
  1624. };
  1625. static const unsigned int hscif0_clk_a_pins[] = {
  1626. /* SCK */
  1627. RCAR_GP_PIN(5, 7),
  1628. };
  1629. static const unsigned int hscif0_clk_a_mux[] = {
  1630. HSCK0_A_MARK,
  1631. };
  1632. static const unsigned int hscif0_ctrl_a_pins[] = {
  1633. /* RTS, CTS */
  1634. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
  1635. };
  1636. static const unsigned int hscif0_ctrl_a_mux[] = {
  1637. HRTS0_N_A_MARK, HCTS0_N_A_MARK,
  1638. };
  1639. static const unsigned int hscif0_data_b_pins[] = {
  1640. /* RX, TX */
  1641. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  1642. };
  1643. static const unsigned int hscif0_data_b_mux[] = {
  1644. HRX0_B_MARK, HTX0_B_MARK,
  1645. };
  1646. static const unsigned int hscif0_clk_b_pins[] = {
  1647. /* SCK */
  1648. RCAR_GP_PIN(6, 13),
  1649. };
  1650. static const unsigned int hscif0_clk_b_mux[] = {
  1651. HSCK0_B_MARK,
  1652. };
  1653. /* - HSCIF1 ------------------------------------------------- */
  1654. static const unsigned int hscif1_data_a_pins[] = {
  1655. /* RX, TX */
  1656. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1657. };
  1658. static const unsigned int hscif1_data_a_mux[] = {
  1659. HRX1_A_MARK, HTX1_A_MARK,
  1660. };
  1661. static const unsigned int hscif1_clk_a_pins[] = {
  1662. /* SCK */
  1663. RCAR_GP_PIN(5, 0),
  1664. };
  1665. static const unsigned int hscif1_clk_a_mux[] = {
  1666. HSCK1_A_MARK,
  1667. };
  1668. static const unsigned int hscif1_data_b_pins[] = {
  1669. /* RX, TX */
  1670. RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
  1671. };
  1672. static const unsigned int hscif1_data_b_mux[] = {
  1673. HRX1_B_MARK, HTX1_B_MARK,
  1674. };
  1675. static const unsigned int hscif1_clk_b_pins[] = {
  1676. /* SCK */
  1677. RCAR_GP_PIN(3, 0),
  1678. };
  1679. static const unsigned int hscif1_clk_b_mux[] = {
  1680. HSCK1_B_MARK,
  1681. };
  1682. static const unsigned int hscif1_ctrl_b_pins[] = {
  1683. /* RTS, CTS */
  1684. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
  1685. };
  1686. static const unsigned int hscif1_ctrl_b_mux[] = {
  1687. HRTS1_N_B_MARK, HCTS1_N_B_MARK,
  1688. };
  1689. /* - HSCIF2 ------------------------------------------------- */
  1690. static const unsigned int hscif2_data_a_pins[] = {
  1691. /* RX, TX */
  1692. RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
  1693. };
  1694. static const unsigned int hscif2_data_a_mux[] = {
  1695. HRX2_A_MARK, HTX2_A_MARK,
  1696. };
  1697. static const unsigned int hscif2_clk_a_pins[] = {
  1698. /* SCK */
  1699. RCAR_GP_PIN(6, 14),
  1700. };
  1701. static const unsigned int hscif2_clk_a_mux[] = {
  1702. HSCK2_A_MARK,
  1703. };
  1704. static const unsigned int hscif2_ctrl_a_pins[] = {
  1705. /* RTS, CTS */
  1706. RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
  1707. };
  1708. static const unsigned int hscif2_ctrl_a_mux[] = {
  1709. HRTS2_N_A_MARK, HCTS2_N_A_MARK,
  1710. };
  1711. static const unsigned int hscif2_data_b_pins[] = {
  1712. /* RX, TX */
  1713. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  1714. };
  1715. static const unsigned int hscif2_data_b_mux[] = {
  1716. HRX2_B_MARK, HTX2_B_MARK,
  1717. };
  1718. /* - HSCIF3 ------------------------------------------------*/
  1719. static const unsigned int hscif3_data_a_pins[] = {
  1720. /* RX, TX */
  1721. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  1722. };
  1723. static const unsigned int hscif3_data_a_mux[] = {
  1724. HRX3_A_MARK, HTX3_A_MARK,
  1725. };
  1726. static const unsigned int hscif3_data_b_pins[] = {
  1727. /* RX, TX */
  1728. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  1729. };
  1730. static const unsigned int hscif3_data_b_mux[] = {
  1731. HRX3_B_MARK, HTX3_B_MARK,
  1732. };
  1733. static const unsigned int hscif3_clk_b_pins[] = {
  1734. /* SCK */
  1735. RCAR_GP_PIN(0, 4),
  1736. };
  1737. static const unsigned int hscif3_clk_b_mux[] = {
  1738. HSCK3_B_MARK,
  1739. };
  1740. static const unsigned int hscif3_data_c_pins[] = {
  1741. /* RX, TX */
  1742. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
  1743. };
  1744. static const unsigned int hscif3_data_c_mux[] = {
  1745. HRX3_C_MARK, HTX3_C_MARK,
  1746. };
  1747. static const unsigned int hscif3_clk_c_pins[] = {
  1748. /* SCK */
  1749. RCAR_GP_PIN(2, 11),
  1750. };
  1751. static const unsigned int hscif3_clk_c_mux[] = {
  1752. HSCK3_C_MARK,
  1753. };
  1754. static const unsigned int hscif3_ctrl_c_pins[] = {
  1755. /* RTS, CTS */
  1756. RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
  1757. };
  1758. static const unsigned int hscif3_ctrl_c_mux[] = {
  1759. HRTS3_N_C_MARK, HCTS3_N_C_MARK,
  1760. };
  1761. static const unsigned int hscif3_data_d_pins[] = {
  1762. /* RX, TX */
  1763. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
  1764. };
  1765. static const unsigned int hscif3_data_d_mux[] = {
  1766. HRX3_D_MARK, HTX3_D_MARK,
  1767. };
  1768. static const unsigned int hscif3_data_e_pins[] = {
  1769. /* RX, TX */
  1770. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  1771. };
  1772. static const unsigned int hscif3_data_e_mux[] = {
  1773. HRX3_E_MARK, HTX3_E_MARK,
  1774. };
  1775. static const unsigned int hscif3_ctrl_e_pins[] = {
  1776. /* RTS, CTS */
  1777. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
  1778. };
  1779. static const unsigned int hscif3_ctrl_e_mux[] = {
  1780. HRTS3_N_E_MARK, HCTS3_N_E_MARK,
  1781. };
  1782. /* - HSCIF4 -------------------------------------------------- */
  1783. static const unsigned int hscif4_data_a_pins[] = {
  1784. /* RX, TX */
  1785. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
  1786. };
  1787. static const unsigned int hscif4_data_a_mux[] = {
  1788. HRX4_A_MARK, HTX4_A_MARK,
  1789. };
  1790. static const unsigned int hscif4_clk_a_pins[] = {
  1791. /* SCK */
  1792. RCAR_GP_PIN(2, 0),
  1793. };
  1794. static const unsigned int hscif4_clk_a_mux[] = {
  1795. HSCK4_A_MARK,
  1796. };
  1797. static const unsigned int hscif4_ctrl_a_pins[] = {
  1798. /* RTS, CTS */
  1799. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
  1800. };
  1801. static const unsigned int hscif4_ctrl_a_mux[] = {
  1802. HRTS4_N_A_MARK, HCTS4_N_A_MARK,
  1803. };
  1804. static const unsigned int hscif4_data_b_pins[] = {
  1805. /* RX, TX */
  1806. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
  1807. };
  1808. static const unsigned int hscif4_data_b_mux[] = {
  1809. HRX4_B_MARK, HTX4_B_MARK,
  1810. };
  1811. static const unsigned int hscif4_clk_b_pins[] = {
  1812. /* SCK */
  1813. RCAR_GP_PIN(2, 6),
  1814. };
  1815. static const unsigned int hscif4_clk_b_mux[] = {
  1816. HSCK4_B_MARK,
  1817. };
  1818. static const unsigned int hscif4_data_c_pins[] = {
  1819. /* RX, TX */
  1820. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  1821. };
  1822. static const unsigned int hscif4_data_c_mux[] = {
  1823. HRX4_C_MARK, HTX4_C_MARK,
  1824. };
  1825. static const unsigned int hscif4_data_d_pins[] = {
  1826. /* RX, TX */
  1827. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  1828. };
  1829. static const unsigned int hscif4_data_d_mux[] = {
  1830. HRX4_D_MARK, HTX4_D_MARK,
  1831. };
  1832. static const unsigned int hscif4_data_e_pins[] = {
  1833. /* RX, TX */
  1834. RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
  1835. };
  1836. static const unsigned int hscif4_data_e_mux[] = {
  1837. HRX4_E_MARK, HTX4_E_MARK,
  1838. };
  1839. /* - I2C -------------------------------------------------------------------- */
  1840. static const unsigned int i2c1_a_pins[] = {
  1841. /* SCL, SDA */
  1842. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
  1843. };
  1844. static const unsigned int i2c1_a_mux[] = {
  1845. SCL1_A_MARK, SDA1_A_MARK,
  1846. };
  1847. static const unsigned int i2c1_b_pins[] = {
  1848. /* SCL, SDA */
  1849. RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
  1850. };
  1851. static const unsigned int i2c1_b_mux[] = {
  1852. SCL1_B_MARK, SDA1_B_MARK,
  1853. };
  1854. static const unsigned int i2c1_c_pins[] = {
  1855. /* SCL, SDA */
  1856. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
  1857. };
  1858. static const unsigned int i2c1_c_mux[] = {
  1859. SCL1_C_MARK, SDA1_C_MARK,
  1860. };
  1861. static const unsigned int i2c1_d_pins[] = {
  1862. /* SCL, SDA */
  1863. RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
  1864. };
  1865. static const unsigned int i2c1_d_mux[] = {
  1866. SCL1_D_MARK, SDA1_D_MARK,
  1867. };
  1868. static const unsigned int i2c2_a_pins[] = {
  1869. /* SCL, SDA */
  1870. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
  1871. };
  1872. static const unsigned int i2c2_a_mux[] = {
  1873. SCL2_A_MARK, SDA2_A_MARK,
  1874. };
  1875. static const unsigned int i2c2_b_pins[] = {
  1876. /* SCL, SDA */
  1877. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
  1878. };
  1879. static const unsigned int i2c2_b_mux[] = {
  1880. SCL2_B_MARK, SDA2_B_MARK,
  1881. };
  1882. static const unsigned int i2c2_c_pins[] = {
  1883. /* SCL, SDA */
  1884. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
  1885. };
  1886. static const unsigned int i2c2_c_mux[] = {
  1887. SCL2_C_MARK, SDA2_C_MARK,
  1888. };
  1889. static const unsigned int i2c2_d_pins[] = {
  1890. /* SCL, SDA */
  1891. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  1892. };
  1893. static const unsigned int i2c2_d_mux[] = {
  1894. SCL2_D_MARK, SDA2_D_MARK,
  1895. };
  1896. static const unsigned int i2c2_e_pins[] = {
  1897. /* SCL, SDA */
  1898. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
  1899. };
  1900. static const unsigned int i2c2_e_mux[] = {
  1901. SCL2_E_MARK, SDA2_E_MARK,
  1902. };
  1903. static const unsigned int i2c4_pins[] = {
  1904. /* SCL, SDA */
  1905. RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
  1906. };
  1907. static const unsigned int i2c4_mux[] = {
  1908. SCL4_MARK, SDA4_MARK,
  1909. };
  1910. static const unsigned int i2c5_pins[] = {
  1911. /* SCL, SDA */
  1912. RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
  1913. };
  1914. static const unsigned int i2c5_mux[] = {
  1915. SCL5_MARK, SDA5_MARK,
  1916. };
  1917. static const unsigned int i2c6_a_pins[] = {
  1918. /* SCL, SDA */
  1919. RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
  1920. };
  1921. static const unsigned int i2c6_a_mux[] = {
  1922. SCL6_A_MARK, SDA6_A_MARK,
  1923. };
  1924. static const unsigned int i2c6_b_pins[] = {
  1925. /* SCL, SDA */
  1926. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
  1927. };
  1928. static const unsigned int i2c6_b_mux[] = {
  1929. SCL6_B_MARK, SDA6_B_MARK,
  1930. };
  1931. static const unsigned int i2c7_a_pins[] = {
  1932. /* SCL, SDA */
  1933. RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
  1934. };
  1935. static const unsigned int i2c7_a_mux[] = {
  1936. SCL7_A_MARK, SDA7_A_MARK,
  1937. };
  1938. static const unsigned int i2c7_b_pins[] = {
  1939. /* SCL, SDA */
  1940. RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
  1941. };
  1942. static const unsigned int i2c7_b_mux[] = {
  1943. SCL7_B_MARK, SDA7_B_MARK,
  1944. };
  1945. /* - INTC-EX ---------------------------------------------------------------- */
  1946. static const unsigned int intc_ex_irq0_pins[] = {
  1947. /* IRQ0 */
  1948. RCAR_GP_PIN(1, 0),
  1949. };
  1950. static const unsigned int intc_ex_irq0_mux[] = {
  1951. IRQ0_MARK,
  1952. };
  1953. static const unsigned int intc_ex_irq1_pins[] = {
  1954. /* IRQ1 */
  1955. RCAR_GP_PIN(1, 1),
  1956. };
  1957. static const unsigned int intc_ex_irq1_mux[] = {
  1958. IRQ1_MARK,
  1959. };
  1960. static const unsigned int intc_ex_irq2_pins[] = {
  1961. /* IRQ2 */
  1962. RCAR_GP_PIN(1, 2),
  1963. };
  1964. static const unsigned int intc_ex_irq2_mux[] = {
  1965. IRQ2_MARK,
  1966. };
  1967. static const unsigned int intc_ex_irq3_pins[] = {
  1968. /* IRQ3 */
  1969. RCAR_GP_PIN(1, 9),
  1970. };
  1971. static const unsigned int intc_ex_irq3_mux[] = {
  1972. IRQ3_MARK,
  1973. };
  1974. static const unsigned int intc_ex_irq4_pins[] = {
  1975. /* IRQ4 */
  1976. RCAR_GP_PIN(1, 10),
  1977. };
  1978. static const unsigned int intc_ex_irq4_mux[] = {
  1979. IRQ4_MARK,
  1980. };
  1981. static const unsigned int intc_ex_irq5_pins[] = {
  1982. /* IRQ5 */
  1983. RCAR_GP_PIN(0, 7),
  1984. };
  1985. static const unsigned int intc_ex_irq5_mux[] = {
  1986. IRQ5_MARK,
  1987. };
  1988. /* - MSIOF0 ----------------------------------------------------------------- */
  1989. static const unsigned int msiof0_clk_pins[] = {
  1990. /* SCK */
  1991. RCAR_GP_PIN(5, 10),
  1992. };
  1993. static const unsigned int msiof0_clk_mux[] = {
  1994. MSIOF0_SCK_MARK,
  1995. };
  1996. static const unsigned int msiof0_sync_pins[] = {
  1997. /* SYNC */
  1998. RCAR_GP_PIN(5, 13),
  1999. };
  2000. static const unsigned int msiof0_sync_mux[] = {
  2001. MSIOF0_SYNC_MARK,
  2002. };
  2003. static const unsigned int msiof0_ss1_pins[] = {
  2004. /* SS1 */
  2005. RCAR_GP_PIN(5, 14),
  2006. };
  2007. static const unsigned int msiof0_ss1_mux[] = {
  2008. MSIOF0_SS1_MARK,
  2009. };
  2010. static const unsigned int msiof0_ss2_pins[] = {
  2011. /* SS2 */
  2012. RCAR_GP_PIN(5, 15),
  2013. };
  2014. static const unsigned int msiof0_ss2_mux[] = {
  2015. MSIOF0_SS2_MARK,
  2016. };
  2017. static const unsigned int msiof0_txd_pins[] = {
  2018. /* TXD */
  2019. RCAR_GP_PIN(5, 12),
  2020. };
  2021. static const unsigned int msiof0_txd_mux[] = {
  2022. MSIOF0_TXD_MARK,
  2023. };
  2024. static const unsigned int msiof0_rxd_pins[] = {
  2025. /* RXD */
  2026. RCAR_GP_PIN(5, 11),
  2027. };
  2028. static const unsigned int msiof0_rxd_mux[] = {
  2029. MSIOF0_RXD_MARK,
  2030. };
  2031. /* - MSIOF1 ----------------------------------------------------------------- */
  2032. static const unsigned int msiof1_clk_pins[] = {
  2033. /* SCK */
  2034. RCAR_GP_PIN(1, 19),
  2035. };
  2036. static const unsigned int msiof1_clk_mux[] = {
  2037. MSIOF1_SCK_MARK,
  2038. };
  2039. static const unsigned int msiof1_sync_pins[] = {
  2040. /* SYNC */
  2041. RCAR_GP_PIN(1, 16),
  2042. };
  2043. static const unsigned int msiof1_sync_mux[] = {
  2044. MSIOF1_SYNC_MARK,
  2045. };
  2046. static const unsigned int msiof1_ss1_pins[] = {
  2047. /* SS1 */
  2048. RCAR_GP_PIN(1, 14),
  2049. };
  2050. static const unsigned int msiof1_ss1_mux[] = {
  2051. MSIOF1_SS1_MARK,
  2052. };
  2053. static const unsigned int msiof1_ss2_pins[] = {
  2054. /* SS2 */
  2055. RCAR_GP_PIN(1, 15),
  2056. };
  2057. static const unsigned int msiof1_ss2_mux[] = {
  2058. MSIOF1_SS2_MARK,
  2059. };
  2060. static const unsigned int msiof1_txd_pins[] = {
  2061. /* TXD */
  2062. RCAR_GP_PIN(1, 18),
  2063. };
  2064. static const unsigned int msiof1_txd_mux[] = {
  2065. MSIOF1_TXD_MARK,
  2066. };
  2067. static const unsigned int msiof1_rxd_pins[] = {
  2068. /* RXD */
  2069. RCAR_GP_PIN(1, 17),
  2070. };
  2071. static const unsigned int msiof1_rxd_mux[] = {
  2072. MSIOF1_RXD_MARK,
  2073. };
  2074. /* - MSIOF2 ----------------------------------------------------------------- */
  2075. static const unsigned int msiof2_clk_a_pins[] = {
  2076. /* SCK */
  2077. RCAR_GP_PIN(0, 8),
  2078. };
  2079. static const unsigned int msiof2_clk_a_mux[] = {
  2080. MSIOF2_SCK_A_MARK,
  2081. };
  2082. static const unsigned int msiof2_sync_a_pins[] = {
  2083. /* SYNC */
  2084. RCAR_GP_PIN(0, 9),
  2085. };
  2086. static const unsigned int msiof2_sync_a_mux[] = {
  2087. MSIOF2_SYNC_A_MARK,
  2088. };
  2089. static const unsigned int msiof2_ss1_a_pins[] = {
  2090. /* SS1 */
  2091. RCAR_GP_PIN(0, 15),
  2092. };
  2093. static const unsigned int msiof2_ss1_a_mux[] = {
  2094. MSIOF2_SS1_A_MARK,
  2095. };
  2096. static const unsigned int msiof2_ss2_a_pins[] = {
  2097. /* SS2 */
  2098. RCAR_GP_PIN(0, 14),
  2099. };
  2100. static const unsigned int msiof2_ss2_a_mux[] = {
  2101. MSIOF2_SS2_A_MARK,
  2102. };
  2103. static const unsigned int msiof2_txd_a_pins[] = {
  2104. /* TXD */
  2105. RCAR_GP_PIN(0, 11),
  2106. };
  2107. static const unsigned int msiof2_txd_a_mux[] = {
  2108. MSIOF2_TXD_A_MARK,
  2109. };
  2110. static const unsigned int msiof2_rxd_a_pins[] = {
  2111. /* RXD */
  2112. RCAR_GP_PIN(0, 10),
  2113. };
  2114. static const unsigned int msiof2_rxd_a_mux[] = {
  2115. MSIOF2_RXD_A_MARK,
  2116. };
  2117. static const unsigned int msiof2_clk_b_pins[] = {
  2118. /* SCK */
  2119. RCAR_GP_PIN(1, 13),
  2120. };
  2121. static const unsigned int msiof2_clk_b_mux[] = {
  2122. MSIOF2_SCK_B_MARK,
  2123. };
  2124. static const unsigned int msiof2_sync_b_pins[] = {
  2125. /* SYNC */
  2126. RCAR_GP_PIN(1, 10),
  2127. };
  2128. static const unsigned int msiof2_sync_b_mux[] = {
  2129. MSIOF2_SYNC_B_MARK,
  2130. };
  2131. static const unsigned int msiof2_ss1_b_pins[] = {
  2132. /* SS1 */
  2133. RCAR_GP_PIN(1, 16),
  2134. };
  2135. static const unsigned int msiof2_ss1_b_mux[] = {
  2136. MSIOF2_SS1_B_MARK,
  2137. };
  2138. static const unsigned int msiof2_ss2_b_pins[] = {
  2139. /* SS2 */
  2140. RCAR_GP_PIN(1, 12),
  2141. };
  2142. static const unsigned int msiof2_ss2_b_mux[] = {
  2143. MSIOF2_SS2_B_MARK,
  2144. };
  2145. static const unsigned int msiof2_txd_b_pins[] = {
  2146. /* TXD */
  2147. RCAR_GP_PIN(1, 15),
  2148. };
  2149. static const unsigned int msiof2_txd_b_mux[] = {
  2150. MSIOF2_TXD_B_MARK,
  2151. };
  2152. static const unsigned int msiof2_rxd_b_pins[] = {
  2153. /* RXD */
  2154. RCAR_GP_PIN(1, 14),
  2155. };
  2156. static const unsigned int msiof2_rxd_b_mux[] = {
  2157. MSIOF2_RXD_B_MARK,
  2158. };
  2159. /* - MSIOF3 ----------------------------------------------------------------- */
  2160. static const unsigned int msiof3_clk_a_pins[] = {
  2161. /* SCK */
  2162. RCAR_GP_PIN(0, 0),
  2163. };
  2164. static const unsigned int msiof3_clk_a_mux[] = {
  2165. MSIOF3_SCK_A_MARK,
  2166. };
  2167. static const unsigned int msiof3_sync_a_pins[] = {
  2168. /* SYNC */
  2169. RCAR_GP_PIN(0, 1),
  2170. };
  2171. static const unsigned int msiof3_sync_a_mux[] = {
  2172. MSIOF3_SYNC_A_MARK,
  2173. };
  2174. static const unsigned int msiof3_ss1_a_pins[] = {
  2175. /* SS1 */
  2176. RCAR_GP_PIN(0, 15),
  2177. };
  2178. static const unsigned int msiof3_ss1_a_mux[] = {
  2179. MSIOF3_SS1_A_MARK,
  2180. };
  2181. static const unsigned int msiof3_ss2_a_pins[] = {
  2182. /* SS2 */
  2183. RCAR_GP_PIN(0, 4),
  2184. };
  2185. static const unsigned int msiof3_ss2_a_mux[] = {
  2186. MSIOF3_SS2_A_MARK,
  2187. };
  2188. static const unsigned int msiof3_txd_a_pins[] = {
  2189. /* TXD */
  2190. RCAR_GP_PIN(0, 3),
  2191. };
  2192. static const unsigned int msiof3_txd_a_mux[] = {
  2193. MSIOF3_TXD_A_MARK,
  2194. };
  2195. static const unsigned int msiof3_rxd_a_pins[] = {
  2196. /* RXD */
  2197. RCAR_GP_PIN(0, 2),
  2198. };
  2199. static const unsigned int msiof3_rxd_a_mux[] = {
  2200. MSIOF3_RXD_A_MARK,
  2201. };
  2202. static const unsigned int msiof3_clk_b_pins[] = {
  2203. /* SCK */
  2204. RCAR_GP_PIN(1, 5),
  2205. };
  2206. static const unsigned int msiof3_clk_b_mux[] = {
  2207. MSIOF3_SCK_B_MARK,
  2208. };
  2209. static const unsigned int msiof3_sync_b_pins[] = {
  2210. /* SYNC */
  2211. RCAR_GP_PIN(1, 4),
  2212. };
  2213. static const unsigned int msiof3_sync_b_mux[] = {
  2214. MSIOF3_SYNC_B_MARK,
  2215. };
  2216. static const unsigned int msiof3_ss1_b_pins[] = {
  2217. /* SS1 */
  2218. RCAR_GP_PIN(1, 0),
  2219. };
  2220. static const unsigned int msiof3_ss1_b_mux[] = {
  2221. MSIOF3_SS1_B_MARK,
  2222. };
  2223. static const unsigned int msiof3_txd_b_pins[] = {
  2224. /* TXD */
  2225. RCAR_GP_PIN(1, 7),
  2226. };
  2227. static const unsigned int msiof3_txd_b_mux[] = {
  2228. MSIOF3_TXD_B_MARK,
  2229. };
  2230. static const unsigned int msiof3_rxd_b_pins[] = {
  2231. /* RXD */
  2232. RCAR_GP_PIN(1, 6),
  2233. };
  2234. static const unsigned int msiof3_rxd_b_mux[] = {
  2235. MSIOF3_RXD_B_MARK,
  2236. };
  2237. /* - PWM0 --------------------------------------------------------------------*/
  2238. static const unsigned int pwm0_a_pins[] = {
  2239. /* PWM */
  2240. RCAR_GP_PIN(2, 22),
  2241. };
  2242. static const unsigned int pwm0_a_mux[] = {
  2243. PWM0_A_MARK,
  2244. };
  2245. static const unsigned int pwm0_b_pins[] = {
  2246. /* PWM */
  2247. RCAR_GP_PIN(6, 3),
  2248. };
  2249. static const unsigned int pwm0_b_mux[] = {
  2250. PWM0_B_MARK,
  2251. };
  2252. /* - PWM1 --------------------------------------------------------------------*/
  2253. static const unsigned int pwm1_a_pins[] = {
  2254. /* PWM */
  2255. RCAR_GP_PIN(2, 23),
  2256. };
  2257. static const unsigned int pwm1_a_mux[] = {
  2258. PWM1_A_MARK,
  2259. };
  2260. static const unsigned int pwm1_b_pins[] = {
  2261. /* PWM */
  2262. RCAR_GP_PIN(6, 4),
  2263. };
  2264. static const unsigned int pwm1_b_mux[] = {
  2265. PWM1_B_MARK,
  2266. };
  2267. /* - PWM2 --------------------------------------------------------------------*/
  2268. static const unsigned int pwm2_a_pins[] = {
  2269. /* PWM */
  2270. RCAR_GP_PIN(1, 0),
  2271. };
  2272. static const unsigned int pwm2_a_mux[] = {
  2273. PWM2_A_MARK,
  2274. };
  2275. static const unsigned int pwm2_b_pins[] = {
  2276. /* PWM */
  2277. RCAR_GP_PIN(1, 4),
  2278. };
  2279. static const unsigned int pwm2_b_mux[] = {
  2280. PWM2_B_MARK,
  2281. };
  2282. static const unsigned int pwm2_c_pins[] = {
  2283. /* PWM */
  2284. RCAR_GP_PIN(6, 5),
  2285. };
  2286. static const unsigned int pwm2_c_mux[] = {
  2287. PWM2_C_MARK,
  2288. };
  2289. /* - PWM3 --------------------------------------------------------------------*/
  2290. static const unsigned int pwm3_a_pins[] = {
  2291. /* PWM */
  2292. RCAR_GP_PIN(1, 1),
  2293. };
  2294. static const unsigned int pwm3_a_mux[] = {
  2295. PWM3_A_MARK,
  2296. };
  2297. static const unsigned int pwm3_b_pins[] = {
  2298. /* PWM */
  2299. RCAR_GP_PIN(1, 5),
  2300. };
  2301. static const unsigned int pwm3_b_mux[] = {
  2302. PWM3_B_MARK,
  2303. };
  2304. static const unsigned int pwm3_c_pins[] = {
  2305. /* PWM */
  2306. RCAR_GP_PIN(6, 6),
  2307. };
  2308. static const unsigned int pwm3_c_mux[] = {
  2309. PWM3_C_MARK,
  2310. };
  2311. /* - PWM4 --------------------------------------------------------------------*/
  2312. static const unsigned int pwm4_a_pins[] = {
  2313. /* PWM */
  2314. RCAR_GP_PIN(1, 3),
  2315. };
  2316. static const unsigned int pwm4_a_mux[] = {
  2317. PWM4_A_MARK,
  2318. };
  2319. static const unsigned int pwm4_b_pins[] = {
  2320. /* PWM */
  2321. RCAR_GP_PIN(6, 7),
  2322. };
  2323. static const unsigned int pwm4_b_mux[] = {
  2324. PWM4_B_MARK,
  2325. };
  2326. /* - PWM5 --------------------------------------------------------------------*/
  2327. static const unsigned int pwm5_a_pins[] = {
  2328. /* PWM */
  2329. RCAR_GP_PIN(2, 24),
  2330. };
  2331. static const unsigned int pwm5_a_mux[] = {
  2332. PWM5_A_MARK,
  2333. };
  2334. static const unsigned int pwm5_b_pins[] = {
  2335. /* PWM */
  2336. RCAR_GP_PIN(6, 10),
  2337. };
  2338. static const unsigned int pwm5_b_mux[] = {
  2339. PWM5_B_MARK,
  2340. };
  2341. /* - PWM6 --------------------------------------------------------------------*/
  2342. static const unsigned int pwm6_a_pins[] = {
  2343. /* PWM */
  2344. RCAR_GP_PIN(2, 25),
  2345. };
  2346. static const unsigned int pwm6_a_mux[] = {
  2347. PWM6_A_MARK,
  2348. };
  2349. static const unsigned int pwm6_b_pins[] = {
  2350. /* PWM */
  2351. RCAR_GP_PIN(6, 11),
  2352. };
  2353. static const unsigned int pwm6_b_mux[] = {
  2354. PWM6_B_MARK,
  2355. };
  2356. /* - QSPI0 ------------------------------------------------------------------ */
  2357. static const unsigned int qspi0_ctrl_pins[] = {
  2358. /* QSPI0_SPCLK, QSPI0_SSL */
  2359. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
  2360. };
  2361. static const unsigned int qspi0_ctrl_mux[] = {
  2362. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  2363. };
  2364. static const unsigned int qspi0_data2_pins[] = {
  2365. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
  2366. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
  2367. };
  2368. static const unsigned int qspi0_data2_mux[] = {
  2369. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  2370. };
  2371. static const unsigned int qspi0_data4_pins[] = {
  2372. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
  2373. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
  2374. /* QSPI0_IO2, QSPI0_IO3 */
  2375. RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
  2376. };
  2377. static const unsigned int qspi0_data4_mux[] = {
  2378. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  2379. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  2380. };
  2381. /* - QSPI1 ------------------------------------------------------------------ */
  2382. static const unsigned int qspi1_ctrl_pins[] = {
  2383. /* QSPI1_SPCLK, QSPI1_SSL */
  2384. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
  2385. };
  2386. static const unsigned int qspi1_ctrl_mux[] = {
  2387. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  2388. };
  2389. static const unsigned int qspi1_data2_pins[] = {
  2390. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
  2391. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2392. };
  2393. static const unsigned int qspi1_data2_mux[] = {
  2394. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  2395. };
  2396. static const unsigned int qspi1_data4_pins[] = {
  2397. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
  2398. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2399. /* QSPI1_IO2, QSPI1_IO3 */
  2400. RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
  2401. };
  2402. static const unsigned int qspi1_data4_mux[] = {
  2403. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  2404. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  2405. };
  2406. /* - SCIF0 ------------------------------------------------------------------ */
  2407. static const unsigned int scif0_data_a_pins[] = {
  2408. /* RX, TX */
  2409. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  2410. };
  2411. static const unsigned int scif0_data_a_mux[] = {
  2412. RX0_A_MARK, TX0_A_MARK,
  2413. };
  2414. static const unsigned int scif0_clk_a_pins[] = {
  2415. /* SCK */
  2416. RCAR_GP_PIN(5, 0),
  2417. };
  2418. static const unsigned int scif0_clk_a_mux[] = {
  2419. SCK0_A_MARK,
  2420. };
  2421. static const unsigned int scif0_ctrl_a_pins[] = {
  2422. /* RTS, CTS */
  2423. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  2424. };
  2425. static const unsigned int scif0_ctrl_a_mux[] = {
  2426. RTS0_N_A_MARK, CTS0_N_A_MARK,
  2427. };
  2428. static const unsigned int scif0_data_b_pins[] = {
  2429. /* RX, TX */
  2430. RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
  2431. };
  2432. static const unsigned int scif0_data_b_mux[] = {
  2433. RX0_B_MARK, TX0_B_MARK,
  2434. };
  2435. static const unsigned int scif0_clk_b_pins[] = {
  2436. /* SCK */
  2437. RCAR_GP_PIN(5, 18),
  2438. };
  2439. static const unsigned int scif0_clk_b_mux[] = {
  2440. SCK0_B_MARK,
  2441. };
  2442. /* - SCIF1 ------------------------------------------------------------------ */
  2443. static const unsigned int scif1_data_pins[] = {
  2444. /* RX, TX */
  2445. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2446. };
  2447. static const unsigned int scif1_data_mux[] = {
  2448. RX1_MARK, TX1_MARK,
  2449. };
  2450. static const unsigned int scif1_clk_pins[] = {
  2451. /* SCK */
  2452. RCAR_GP_PIN(5, 16),
  2453. };
  2454. static const unsigned int scif1_clk_mux[] = {
  2455. SCK1_MARK,
  2456. };
  2457. static const unsigned int scif1_ctrl_pins[] = {
  2458. /* RTS, CTS */
  2459. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
  2460. };
  2461. static const unsigned int scif1_ctrl_mux[] = {
  2462. RTS1_N_MARK, CTS1_N_MARK,
  2463. };
  2464. /* - SCIF2 ------------------------------------------------------------------ */
  2465. static const unsigned int scif2_data_a_pins[] = {
  2466. /* RX, TX */
  2467. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
  2468. };
  2469. static const unsigned int scif2_data_a_mux[] = {
  2470. RX2_A_MARK, TX2_A_MARK,
  2471. };
  2472. static const unsigned int scif2_clk_a_pins[] = {
  2473. /* SCK */
  2474. RCAR_GP_PIN(5, 7),
  2475. };
  2476. static const unsigned int scif2_clk_a_mux[] = {
  2477. SCK2_A_MARK,
  2478. };
  2479. static const unsigned int scif2_data_b_pins[] = {
  2480. /* RX, TX */
  2481. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
  2482. };
  2483. static const unsigned int scif2_data_b_mux[] = {
  2484. RX2_B_MARK, TX2_B_MARK,
  2485. };
  2486. /* - SCIF3 ------------------------------------------------------------------ */
  2487. static const unsigned int scif3_data_a_pins[] = {
  2488. /* RX, TX */
  2489. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  2490. };
  2491. static const unsigned int scif3_data_a_mux[] = {
  2492. RX3_A_MARK, TX3_A_MARK,
  2493. };
  2494. static const unsigned int scif3_clk_a_pins[] = {
  2495. /* SCK */
  2496. RCAR_GP_PIN(0, 1),
  2497. };
  2498. static const unsigned int scif3_clk_a_mux[] = {
  2499. SCK3_A_MARK,
  2500. };
  2501. static const unsigned int scif3_ctrl_a_pins[] = {
  2502. /* RTS, CTS */
  2503. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
  2504. };
  2505. static const unsigned int scif3_ctrl_a_mux[] = {
  2506. RTS3_N_A_MARK, CTS3_N_A_MARK,
  2507. };
  2508. static const unsigned int scif3_data_b_pins[] = {
  2509. /* RX, TX */
  2510. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2511. };
  2512. static const unsigned int scif3_data_b_mux[] = {
  2513. RX3_B_MARK, TX3_B_MARK,
  2514. };
  2515. static const unsigned int scif3_data_c_pins[] = {
  2516. /* RX, TX */
  2517. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
  2518. };
  2519. static const unsigned int scif3_data_c_mux[] = {
  2520. RX3_C_MARK, TX3_C_MARK,
  2521. };
  2522. static const unsigned int scif3_clk_c_pins[] = {
  2523. /* SCK */
  2524. RCAR_GP_PIN(2, 24),
  2525. };
  2526. static const unsigned int scif3_clk_c_mux[] = {
  2527. SCK3_C_MARK,
  2528. };
  2529. /* - SCIF4 ------------------------------------------------------------------ */
  2530. static const unsigned int scif4_data_a_pins[] = {
  2531. /* RX, TX */
  2532. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  2533. };
  2534. static const unsigned int scif4_data_a_mux[] = {
  2535. RX4_A_MARK, TX4_A_MARK,
  2536. };
  2537. static const unsigned int scif4_clk_a_pins[] = {
  2538. /* SCK */
  2539. RCAR_GP_PIN(1, 5),
  2540. };
  2541. static const unsigned int scif4_clk_a_mux[] = {
  2542. SCK4_A_MARK,
  2543. };
  2544. static const unsigned int scif4_ctrl_a_pins[] = {
  2545. /* RTS, CTS */
  2546. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
  2547. };
  2548. static const unsigned int scif4_ctrl_a_mux[] = {
  2549. RTS4_N_A_MARK, CTS4_N_A_MARK,
  2550. };
  2551. static const unsigned int scif4_data_b_pins[] = {
  2552. /* RX, TX */
  2553. RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
  2554. };
  2555. static const unsigned int scif4_data_b_mux[] = {
  2556. RX4_B_MARK, TX4_B_MARK,
  2557. };
  2558. static const unsigned int scif4_clk_b_pins[] = {
  2559. /* SCK */
  2560. RCAR_GP_PIN(0, 8),
  2561. };
  2562. static const unsigned int scif4_clk_b_mux[] = {
  2563. SCK4_B_MARK,
  2564. };
  2565. static const unsigned int scif4_data_c_pins[] = {
  2566. /* RX, TX */
  2567. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  2568. };
  2569. static const unsigned int scif4_data_c_mux[] = {
  2570. RX4_C_MARK, TX4_C_MARK,
  2571. };
  2572. static const unsigned int scif4_ctrl_c_pins[] = {
  2573. /* RTS, CTS */
  2574. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
  2575. };
  2576. static const unsigned int scif4_ctrl_c_mux[] = {
  2577. RTS4_N_C_MARK, CTS4_N_C_MARK,
  2578. };
  2579. /* - SCIF5 ------------------------------------------------------------------ */
  2580. static const unsigned int scif5_data_a_pins[] = {
  2581. /* RX, TX */
  2582. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
  2583. };
  2584. static const unsigned int scif5_data_a_mux[] = {
  2585. RX5_A_MARK, TX5_A_MARK,
  2586. };
  2587. static const unsigned int scif5_clk_a_pins[] = {
  2588. /* SCK */
  2589. RCAR_GP_PIN(1, 13),
  2590. };
  2591. static const unsigned int scif5_clk_a_mux[] = {
  2592. SCK5_A_MARK,
  2593. };
  2594. static const unsigned int scif5_data_b_pins[] = {
  2595. /* RX, TX */
  2596. RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
  2597. };
  2598. static const unsigned int scif5_data_b_mux[] = {
  2599. RX5_B_MARK, TX5_B_MARK,
  2600. };
  2601. static const unsigned int scif5_data_c_pins[] = {
  2602. /* RX, TX */
  2603. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  2604. };
  2605. static const unsigned int scif5_data_c_mux[] = {
  2606. RX5_C_MARK, TX5_C_MARK,
  2607. };
  2608. /* - SCIF Clock ------------------------------------------------------------- */
  2609. static const unsigned int scif_clk_a_pins[] = {
  2610. /* SCIF_CLK */
  2611. RCAR_GP_PIN(5, 3),
  2612. };
  2613. static const unsigned int scif_clk_a_mux[] = {
  2614. SCIF_CLK_A_MARK,
  2615. };
  2616. static const unsigned int scif_clk_b_pins[] = {
  2617. /* SCIF_CLK */
  2618. RCAR_GP_PIN(5, 7),
  2619. };
  2620. static const unsigned int scif_clk_b_mux[] = {
  2621. SCIF_CLK_B_MARK,
  2622. };
  2623. /* - SDHI0 ------------------------------------------------------------------ */
  2624. static const unsigned int sdhi0_data1_pins[] = {
  2625. /* D0 */
  2626. RCAR_GP_PIN(3, 2),
  2627. };
  2628. static const unsigned int sdhi0_data1_mux[] = {
  2629. SD0_DAT0_MARK,
  2630. };
  2631. static const unsigned int sdhi0_data4_pins[] = {
  2632. /* D[0:3] */
  2633. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  2634. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  2635. };
  2636. static const unsigned int sdhi0_data4_mux[] = {
  2637. SD0_DAT0_MARK, SD0_DAT1_MARK,
  2638. SD0_DAT2_MARK, SD0_DAT3_MARK,
  2639. };
  2640. static const unsigned int sdhi0_ctrl_pins[] = {
  2641. /* CLK, CMD */
  2642. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  2643. };
  2644. static const unsigned int sdhi0_ctrl_mux[] = {
  2645. SD0_CLK_MARK, SD0_CMD_MARK,
  2646. };
  2647. static const unsigned int sdhi0_cd_pins[] = {
  2648. /* CD */
  2649. RCAR_GP_PIN(3, 12),
  2650. };
  2651. static const unsigned int sdhi0_cd_mux[] = {
  2652. SD0_CD_MARK,
  2653. };
  2654. static const unsigned int sdhi0_wp_pins[] = {
  2655. /* WP */
  2656. RCAR_GP_PIN(3, 13),
  2657. };
  2658. static const unsigned int sdhi0_wp_mux[] = {
  2659. SD0_WP_MARK,
  2660. };
  2661. /* - SDHI1 ------------------------------------------------------------------ */
  2662. static const unsigned int sdhi1_data1_pins[] = {
  2663. /* D0 */
  2664. RCAR_GP_PIN(3, 8),
  2665. };
  2666. static const unsigned int sdhi1_data1_mux[] = {
  2667. SD1_DAT0_MARK,
  2668. };
  2669. static const unsigned int sdhi1_data4_pins[] = {
  2670. /* D[0:3] */
  2671. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  2672. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  2673. };
  2674. static const unsigned int sdhi1_data4_mux[] = {
  2675. SD1_DAT0_MARK, SD1_DAT1_MARK,
  2676. SD1_DAT2_MARK, SD1_DAT3_MARK,
  2677. };
  2678. static const unsigned int sdhi1_ctrl_pins[] = {
  2679. /* CLK, CMD */
  2680. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  2681. };
  2682. static const unsigned int sdhi1_ctrl_mux[] = {
  2683. SD1_CLK_MARK, SD1_CMD_MARK,
  2684. };
  2685. static const unsigned int sdhi1_cd_pins[] = {
  2686. /* CD */
  2687. RCAR_GP_PIN(3, 14),
  2688. };
  2689. static const unsigned int sdhi1_cd_mux[] = {
  2690. SD1_CD_MARK,
  2691. };
  2692. static const unsigned int sdhi1_wp_pins[] = {
  2693. /* WP */
  2694. RCAR_GP_PIN(3, 15),
  2695. };
  2696. static const unsigned int sdhi1_wp_mux[] = {
  2697. SD1_WP_MARK,
  2698. };
  2699. /* - SDHI3 ------------------------------------------------------------------ */
  2700. static const unsigned int sdhi3_data1_pins[] = {
  2701. /* D0 */
  2702. RCAR_GP_PIN(4, 2),
  2703. };
  2704. static const unsigned int sdhi3_data1_mux[] = {
  2705. SD3_DAT0_MARK,
  2706. };
  2707. static const unsigned int sdhi3_data4_pins[] = {
  2708. /* D[0:3] */
  2709. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  2710. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  2711. };
  2712. static const unsigned int sdhi3_data4_mux[] = {
  2713. SD3_DAT0_MARK, SD3_DAT1_MARK,
  2714. SD3_DAT2_MARK, SD3_DAT3_MARK,
  2715. };
  2716. static const unsigned int sdhi3_data8_pins[] = {
  2717. /* D[0:7] */
  2718. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  2719. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  2720. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
  2721. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  2722. };
  2723. static const unsigned int sdhi3_data8_mux[] = {
  2724. SD3_DAT0_MARK, SD3_DAT1_MARK,
  2725. SD3_DAT2_MARK, SD3_DAT3_MARK,
  2726. SD3_DAT4_MARK, SD3_DAT5_MARK,
  2727. SD3_DAT6_MARK, SD3_DAT7_MARK,
  2728. };
  2729. static const unsigned int sdhi3_ctrl_pins[] = {
  2730. /* CLK, CMD */
  2731. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  2732. };
  2733. static const unsigned int sdhi3_ctrl_mux[] = {
  2734. SD3_CLK_MARK, SD3_CMD_MARK,
  2735. };
  2736. static const unsigned int sdhi3_cd_pins[] = {
  2737. /* CD */
  2738. RCAR_GP_PIN(3, 12),
  2739. };
  2740. static const unsigned int sdhi3_cd_mux[] = {
  2741. SD3_CD_MARK,
  2742. };
  2743. static const unsigned int sdhi3_wp_pins[] = {
  2744. /* WP */
  2745. RCAR_GP_PIN(3, 13),
  2746. };
  2747. static const unsigned int sdhi3_wp_mux[] = {
  2748. SD3_WP_MARK,
  2749. };
  2750. static const unsigned int sdhi3_ds_pins[] = {
  2751. /* DS */
  2752. RCAR_GP_PIN(4, 10),
  2753. };
  2754. static const unsigned int sdhi3_ds_mux[] = {
  2755. SD3_DS_MARK,
  2756. };
  2757. /* - SSI -------------------------------------------------------------------- */
  2758. static const unsigned int ssi0_data_pins[] = {
  2759. /* SDATA */
  2760. RCAR_GP_PIN(6, 2),
  2761. };
  2762. static const unsigned int ssi0_data_mux[] = {
  2763. SSI_SDATA0_MARK,
  2764. };
  2765. static const unsigned int ssi01239_ctrl_pins[] = {
  2766. /* SCK, WS */
  2767. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  2768. };
  2769. static const unsigned int ssi01239_ctrl_mux[] = {
  2770. SSI_SCK01239_MARK, SSI_WS01239_MARK,
  2771. };
  2772. static const unsigned int ssi1_data_pins[] = {
  2773. /* SDATA */
  2774. RCAR_GP_PIN(6, 3),
  2775. };
  2776. static const unsigned int ssi1_data_mux[] = {
  2777. SSI_SDATA1_MARK,
  2778. };
  2779. static const unsigned int ssi1_ctrl_pins[] = {
  2780. /* SCK, WS */
  2781. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2782. };
  2783. static const unsigned int ssi1_ctrl_mux[] = {
  2784. SSI_SCK1_MARK, SSI_WS1_MARK,
  2785. };
  2786. static const unsigned int ssi2_data_pins[] = {
  2787. /* SDATA */
  2788. RCAR_GP_PIN(6, 4),
  2789. };
  2790. static const unsigned int ssi2_data_mux[] = {
  2791. SSI_SDATA2_MARK,
  2792. };
  2793. static const unsigned int ssi2_ctrl_a_pins[] = {
  2794. /* SCK, WS */
  2795. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  2796. };
  2797. static const unsigned int ssi2_ctrl_a_mux[] = {
  2798. SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
  2799. };
  2800. static const unsigned int ssi2_ctrl_b_pins[] = {
  2801. /* SCK, WS */
  2802. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
  2803. };
  2804. static const unsigned int ssi2_ctrl_b_mux[] = {
  2805. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  2806. };
  2807. static const unsigned int ssi3_data_pins[] = {
  2808. /* SDATA */
  2809. RCAR_GP_PIN(6, 7),
  2810. };
  2811. static const unsigned int ssi3_data_mux[] = {
  2812. SSI_SDATA3_MARK,
  2813. };
  2814. static const unsigned int ssi349_ctrl_pins[] = {
  2815. /* SCK, WS */
  2816. RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
  2817. };
  2818. static const unsigned int ssi349_ctrl_mux[] = {
  2819. SSI_SCK349_MARK, SSI_WS349_MARK,
  2820. };
  2821. static const unsigned int ssi4_data_pins[] = {
  2822. /* SDATA */
  2823. RCAR_GP_PIN(6, 10),
  2824. };
  2825. static const unsigned int ssi4_data_mux[] = {
  2826. SSI_SDATA4_MARK,
  2827. };
  2828. static const unsigned int ssi4_ctrl_pins[] = {
  2829. /* SCK, WS */
  2830. RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
  2831. };
  2832. static const unsigned int ssi4_ctrl_mux[] = {
  2833. SSI_SCK4_MARK, SSI_WS4_MARK,
  2834. };
  2835. static const unsigned int ssi5_data_pins[] = {
  2836. /* SDATA */
  2837. RCAR_GP_PIN(6, 13),
  2838. };
  2839. static const unsigned int ssi5_data_mux[] = {
  2840. SSI_SDATA5_MARK,
  2841. };
  2842. static const unsigned int ssi5_ctrl_pins[] = {
  2843. /* SCK, WS */
  2844. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  2845. };
  2846. static const unsigned int ssi5_ctrl_mux[] = {
  2847. SSI_SCK5_MARK, SSI_WS5_MARK,
  2848. };
  2849. static const unsigned int ssi6_data_pins[] = {
  2850. /* SDATA */
  2851. RCAR_GP_PIN(6, 16),
  2852. };
  2853. static const unsigned int ssi6_data_mux[] = {
  2854. SSI_SDATA6_MARK,
  2855. };
  2856. static const unsigned int ssi6_ctrl_pins[] = {
  2857. /* SCK, WS */
  2858. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  2859. };
  2860. static const unsigned int ssi6_ctrl_mux[] = {
  2861. SSI_SCK6_MARK, SSI_WS6_MARK,
  2862. };
  2863. static const unsigned int ssi7_data_pins[] = {
  2864. /* SDATA */
  2865. RCAR_GP_PIN(5, 12),
  2866. };
  2867. static const unsigned int ssi7_data_mux[] = {
  2868. SSI_SDATA7_MARK,
  2869. };
  2870. static const unsigned int ssi78_ctrl_pins[] = {
  2871. /* SCK, WS */
  2872. RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
  2873. };
  2874. static const unsigned int ssi78_ctrl_mux[] = {
  2875. SSI_SCK78_MARK, SSI_WS78_MARK,
  2876. };
  2877. static const unsigned int ssi8_data_pins[] = {
  2878. /* SDATA */
  2879. RCAR_GP_PIN(5, 13),
  2880. };
  2881. static const unsigned int ssi8_data_mux[] = {
  2882. SSI_SDATA8_MARK,
  2883. };
  2884. static const unsigned int ssi9_data_pins[] = {
  2885. /* SDATA */
  2886. RCAR_GP_PIN(5, 16),
  2887. };
  2888. static const unsigned int ssi9_data_mux[] = {
  2889. SSI_SDATA9_MARK,
  2890. };
  2891. static const unsigned int ssi9_ctrl_a_pins[] = {
  2892. /* SCK, WS */
  2893. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
  2894. };
  2895. static const unsigned int ssi9_ctrl_a_mux[] = {
  2896. SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
  2897. };
  2898. static const unsigned int ssi9_ctrl_b_pins[] = {
  2899. /* SCK, WS */
  2900. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2901. };
  2902. static const unsigned int ssi9_ctrl_b_mux[] = {
  2903. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  2904. };
  2905. /* - TMU -------------------------------------------------------------------- */
  2906. static const unsigned int tmu_tclk1_a_pins[] = {
  2907. /* TCLK */
  2908. RCAR_GP_PIN(3, 12),
  2909. };
  2910. static const unsigned int tmu_tclk1_a_mux[] = {
  2911. TCLK1_A_MARK,
  2912. };
  2913. static const unsigned int tmu_tclk1_b_pins[] = {
  2914. /* TCLK */
  2915. RCAR_GP_PIN(5, 17),
  2916. };
  2917. static const unsigned int tmu_tclk1_b_mux[] = {
  2918. TCLK1_B_MARK,
  2919. };
  2920. static const unsigned int tmu_tclk2_a_pins[] = {
  2921. /* TCLK */
  2922. RCAR_GP_PIN(3, 13),
  2923. };
  2924. static const unsigned int tmu_tclk2_a_mux[] = {
  2925. TCLK2_A_MARK,
  2926. };
  2927. static const unsigned int tmu_tclk2_b_pins[] = {
  2928. /* TCLK */
  2929. RCAR_GP_PIN(5, 18),
  2930. };
  2931. static const unsigned int tmu_tclk2_b_mux[] = {
  2932. TCLK2_B_MARK,
  2933. };
  2934. /* - USB0 ------------------------------------------------------------------- */
  2935. static const unsigned int usb0_a_pins[] = {
  2936. /* PWEN, OVC */
  2937. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
  2938. };
  2939. static const unsigned int usb0_a_mux[] = {
  2940. USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
  2941. };
  2942. static const unsigned int usb0_b_pins[] = {
  2943. /* PWEN, OVC */
  2944. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  2945. };
  2946. static const unsigned int usb0_b_mux[] = {
  2947. USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
  2948. };
  2949. static const unsigned int usb0_id_pins[] = {
  2950. /* ID */
  2951. RCAR_GP_PIN(5, 0)
  2952. };
  2953. static const unsigned int usb0_id_mux[] = {
  2954. USB0_ID_MARK,
  2955. };
  2956. /* - USB30 ------------------------------------------------------------------ */
  2957. static const unsigned int usb30_pins[] = {
  2958. /* PWEN, OVC */
  2959. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
  2960. };
  2961. static const unsigned int usb30_mux[] = {
  2962. USB30_PWEN_MARK, USB30_OVC_MARK,
  2963. };
  2964. static const unsigned int usb30_id_pins[] = {
  2965. /* ID */
  2966. RCAR_GP_PIN(5, 0),
  2967. };
  2968. static const unsigned int usb30_id_mux[] = {
  2969. USB3HS0_ID_MARK,
  2970. };
  2971. /* - VIN4 ------------------------------------------------------------------- */
  2972. static const unsigned int vin4_data18_a_pins[] = {
  2973. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  2974. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  2975. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
  2976. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  2977. RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
  2978. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  2979. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
  2980. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
  2981. RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
  2982. };
  2983. static const unsigned int vin4_data18_a_mux[] = {
  2984. VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
  2985. VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
  2986. VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
  2987. VI4_DATA10_MARK, VI4_DATA11_MARK,
  2988. VI4_DATA12_MARK, VI4_DATA13_MARK,
  2989. VI4_DATA14_MARK, VI4_DATA15_MARK,
  2990. VI4_DATA18_MARK, VI4_DATA19_MARK,
  2991. VI4_DATA20_MARK, VI4_DATA21_MARK,
  2992. VI4_DATA22_MARK, VI4_DATA23_MARK,
  2993. };
  2994. static const union vin_data vin4_data_a_pins = {
  2995. .data24 = {
  2996. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  2997. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  2998. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  2999. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
  3000. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3001. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3002. RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
  3003. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  3004. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
  3005. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
  3006. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
  3007. RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
  3008. },
  3009. };
  3010. static const union vin_data vin4_data_a_mux = {
  3011. .data24 = {
  3012. VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
  3013. VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
  3014. VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
  3015. VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
  3016. VI4_DATA8_MARK, VI4_DATA9_MARK,
  3017. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3018. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3019. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3020. VI4_DATA16_MARK, VI4_DATA17_MARK,
  3021. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3022. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3023. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3024. },
  3025. };
  3026. static const unsigned int vin4_data18_b_pins[] = {
  3027. RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
  3028. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  3029. RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
  3030. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3031. RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
  3032. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  3033. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
  3034. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
  3035. RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
  3036. };
  3037. static const unsigned int vin4_data18_b_mux[] = {
  3038. VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
  3039. VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
  3040. VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
  3041. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3042. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3043. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3044. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3045. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3046. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3047. };
  3048. static const union vin_data vin4_data_b_pins = {
  3049. .data24 = {
  3050. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  3051. RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
  3052. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  3053. RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
  3054. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3055. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3056. RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
  3057. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  3058. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
  3059. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
  3060. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
  3061. RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
  3062. },
  3063. };
  3064. static const union vin_data vin4_data_b_mux = {
  3065. .data24 = {
  3066. VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
  3067. VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
  3068. VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
  3069. VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
  3070. VI4_DATA8_MARK, VI4_DATA9_MARK,
  3071. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3072. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3073. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3074. VI4_DATA16_MARK, VI4_DATA17_MARK,
  3075. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3076. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3077. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3078. },
  3079. };
  3080. static const unsigned int vin4_sync_pins[] = {
  3081. /* HSYNC, VSYNC */
  3082. RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
  3083. };
  3084. static const unsigned int vin4_sync_mux[] = {
  3085. VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
  3086. };
  3087. static const unsigned int vin4_field_pins[] = {
  3088. RCAR_GP_PIN(2, 23),
  3089. };
  3090. static const unsigned int vin4_field_mux[] = {
  3091. VI4_FIELD_MARK,
  3092. };
  3093. static const unsigned int vin4_clkenb_pins[] = {
  3094. RCAR_GP_PIN(1, 2),
  3095. };
  3096. static const unsigned int vin4_clkenb_mux[] = {
  3097. VI4_CLKENB_MARK,
  3098. };
  3099. static const unsigned int vin4_clk_pins[] = {
  3100. RCAR_GP_PIN(2, 22),
  3101. };
  3102. static const unsigned int vin4_clk_mux[] = {
  3103. VI4_CLK_MARK,
  3104. };
  3105. /* - VIN5 ------------------------------------------------------------------- */
  3106. static const union vin_data16 vin5_data_a_pins = {
  3107. .data16 = {
  3108. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
  3109. RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
  3110. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
  3111. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
  3112. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3113. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
  3114. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
  3115. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3116. },
  3117. };
  3118. static const union vin_data16 vin5_data_a_mux = {
  3119. .data16 = {
  3120. VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
  3121. VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
  3122. VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
  3123. VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
  3124. VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
  3125. VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
  3126. VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
  3127. VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
  3128. },
  3129. };
  3130. static const unsigned int vin5_data8_b_pins[] = {
  3131. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
  3132. RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
  3133. RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
  3134. RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
  3135. };
  3136. static const unsigned int vin5_data8_b_mux[] = {
  3137. VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
  3138. VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
  3139. VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
  3140. VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
  3141. };
  3142. static const unsigned int vin5_sync_a_pins[] = {
  3143. /* HSYNC_N, VSYNC_N */
  3144. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
  3145. };
  3146. static const unsigned int vin5_sync_a_mux[] = {
  3147. VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
  3148. };
  3149. static const unsigned int vin5_field_a_pins[] = {
  3150. RCAR_GP_PIN(1, 10),
  3151. };
  3152. static const unsigned int vin5_field_a_mux[] = {
  3153. VI5_FIELD_A_MARK,
  3154. };
  3155. static const unsigned int vin5_clkenb_a_pins[] = {
  3156. RCAR_GP_PIN(0, 1),
  3157. };
  3158. static const unsigned int vin5_clkenb_a_mux[] = {
  3159. VI5_CLKENB_A_MARK,
  3160. };
  3161. static const unsigned int vin5_clk_a_pins[] = {
  3162. RCAR_GP_PIN(1, 0),
  3163. };
  3164. static const unsigned int vin5_clk_a_mux[] = {
  3165. VI5_CLK_A_MARK,
  3166. };
  3167. static const unsigned int vin5_clk_b_pins[] = {
  3168. RCAR_GP_PIN(2, 22),
  3169. };
  3170. static const unsigned int vin5_clk_b_mux[] = {
  3171. VI5_CLK_B_MARK,
  3172. };
  3173. static const struct {
  3174. struct sh_pfc_pin_group common[253];
  3175. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  3176. struct sh_pfc_pin_group automotive[21];
  3177. #endif
  3178. } pinmux_groups = {
  3179. .common = {
  3180. SH_PFC_PIN_GROUP(audio_clk_a),
  3181. SH_PFC_PIN_GROUP(audio_clk_b_a),
  3182. SH_PFC_PIN_GROUP(audio_clk_b_b),
  3183. SH_PFC_PIN_GROUP(audio_clk_b_c),
  3184. SH_PFC_PIN_GROUP(audio_clk_c_a),
  3185. SH_PFC_PIN_GROUP(audio_clk_c_b),
  3186. SH_PFC_PIN_GROUP(audio_clk_c_c),
  3187. SH_PFC_PIN_GROUP(audio_clkout_a),
  3188. SH_PFC_PIN_GROUP(audio_clkout_b),
  3189. SH_PFC_PIN_GROUP(audio_clkout1_a),
  3190. SH_PFC_PIN_GROUP(audio_clkout1_b),
  3191. SH_PFC_PIN_GROUP(audio_clkout1_c),
  3192. SH_PFC_PIN_GROUP(audio_clkout2_a),
  3193. SH_PFC_PIN_GROUP(audio_clkout2_b),
  3194. SH_PFC_PIN_GROUP(audio_clkout2_c),
  3195. SH_PFC_PIN_GROUP(audio_clkout3_a),
  3196. SH_PFC_PIN_GROUP(audio_clkout3_b),
  3197. SH_PFC_PIN_GROUP(audio_clkout3_c),
  3198. SH_PFC_PIN_GROUP(avb_link),
  3199. SH_PFC_PIN_GROUP(avb_magic),
  3200. SH_PFC_PIN_GROUP(avb_phy_int),
  3201. SH_PFC_PIN_GROUP(avb_mii),
  3202. SH_PFC_PIN_GROUP(avb_avtp_pps),
  3203. SH_PFC_PIN_GROUP(avb_avtp_match),
  3204. SH_PFC_PIN_GROUP(avb_avtp_capture),
  3205. SH_PFC_PIN_GROUP(can0_data),
  3206. SH_PFC_PIN_GROUP(can1_data),
  3207. SH_PFC_PIN_GROUP(can_clk),
  3208. SH_PFC_PIN_GROUP(canfd0_data),
  3209. SH_PFC_PIN_GROUP(canfd1_data),
  3210. SH_PFC_PIN_GROUP(du_rgb666),
  3211. SH_PFC_PIN_GROUP(du_rgb888),
  3212. SH_PFC_PIN_GROUP(du_clk_in_0),
  3213. SH_PFC_PIN_GROUP(du_clk_in_1),
  3214. SH_PFC_PIN_GROUP(du_clk_out_0),
  3215. SH_PFC_PIN_GROUP(du_sync),
  3216. SH_PFC_PIN_GROUP(du_disp_cde),
  3217. SH_PFC_PIN_GROUP(du_cde),
  3218. SH_PFC_PIN_GROUP(du_disp),
  3219. SH_PFC_PIN_GROUP(hscif0_data_a),
  3220. SH_PFC_PIN_GROUP(hscif0_clk_a),
  3221. SH_PFC_PIN_GROUP(hscif0_ctrl_a),
  3222. SH_PFC_PIN_GROUP(hscif0_data_b),
  3223. SH_PFC_PIN_GROUP(hscif0_clk_b),
  3224. SH_PFC_PIN_GROUP(hscif1_data_a),
  3225. SH_PFC_PIN_GROUP(hscif1_clk_a),
  3226. SH_PFC_PIN_GROUP(hscif1_data_b),
  3227. SH_PFC_PIN_GROUP(hscif1_clk_b),
  3228. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3229. SH_PFC_PIN_GROUP(hscif2_data_a),
  3230. SH_PFC_PIN_GROUP(hscif2_clk_a),
  3231. SH_PFC_PIN_GROUP(hscif2_ctrl_a),
  3232. SH_PFC_PIN_GROUP(hscif2_data_b),
  3233. SH_PFC_PIN_GROUP(hscif3_data_a),
  3234. SH_PFC_PIN_GROUP(hscif3_data_b),
  3235. SH_PFC_PIN_GROUP(hscif3_clk_b),
  3236. SH_PFC_PIN_GROUP(hscif3_data_c),
  3237. SH_PFC_PIN_GROUP(hscif3_clk_c),
  3238. SH_PFC_PIN_GROUP(hscif3_ctrl_c),
  3239. SH_PFC_PIN_GROUP(hscif3_data_d),
  3240. SH_PFC_PIN_GROUP(hscif3_data_e),
  3241. SH_PFC_PIN_GROUP(hscif3_ctrl_e),
  3242. SH_PFC_PIN_GROUP(hscif4_data_a),
  3243. SH_PFC_PIN_GROUP(hscif4_clk_a),
  3244. SH_PFC_PIN_GROUP(hscif4_ctrl_a),
  3245. SH_PFC_PIN_GROUP(hscif4_data_b),
  3246. SH_PFC_PIN_GROUP(hscif4_clk_b),
  3247. SH_PFC_PIN_GROUP(hscif4_data_c),
  3248. SH_PFC_PIN_GROUP(hscif4_data_d),
  3249. SH_PFC_PIN_GROUP(hscif4_data_e),
  3250. SH_PFC_PIN_GROUP(i2c1_a),
  3251. SH_PFC_PIN_GROUP(i2c1_b),
  3252. SH_PFC_PIN_GROUP(i2c1_c),
  3253. SH_PFC_PIN_GROUP(i2c1_d),
  3254. SH_PFC_PIN_GROUP(i2c2_a),
  3255. SH_PFC_PIN_GROUP(i2c2_b),
  3256. SH_PFC_PIN_GROUP(i2c2_c),
  3257. SH_PFC_PIN_GROUP(i2c2_d),
  3258. SH_PFC_PIN_GROUP(i2c2_e),
  3259. SH_PFC_PIN_GROUP(i2c4),
  3260. SH_PFC_PIN_GROUP(i2c5),
  3261. SH_PFC_PIN_GROUP(i2c6_a),
  3262. SH_PFC_PIN_GROUP(i2c6_b),
  3263. SH_PFC_PIN_GROUP(i2c7_a),
  3264. SH_PFC_PIN_GROUP(i2c7_b),
  3265. SH_PFC_PIN_GROUP(intc_ex_irq0),
  3266. SH_PFC_PIN_GROUP(intc_ex_irq1),
  3267. SH_PFC_PIN_GROUP(intc_ex_irq2),
  3268. SH_PFC_PIN_GROUP(intc_ex_irq3),
  3269. SH_PFC_PIN_GROUP(intc_ex_irq4),
  3270. SH_PFC_PIN_GROUP(intc_ex_irq5),
  3271. SH_PFC_PIN_GROUP(msiof0_clk),
  3272. SH_PFC_PIN_GROUP(msiof0_sync),
  3273. SH_PFC_PIN_GROUP(msiof0_ss1),
  3274. SH_PFC_PIN_GROUP(msiof0_ss2),
  3275. SH_PFC_PIN_GROUP(msiof0_txd),
  3276. SH_PFC_PIN_GROUP(msiof0_rxd),
  3277. SH_PFC_PIN_GROUP(msiof1_clk),
  3278. SH_PFC_PIN_GROUP(msiof1_sync),
  3279. SH_PFC_PIN_GROUP(msiof1_ss1),
  3280. SH_PFC_PIN_GROUP(msiof1_ss2),
  3281. SH_PFC_PIN_GROUP(msiof1_txd),
  3282. SH_PFC_PIN_GROUP(msiof1_rxd),
  3283. SH_PFC_PIN_GROUP(msiof2_clk_a),
  3284. SH_PFC_PIN_GROUP(msiof2_sync_a),
  3285. SH_PFC_PIN_GROUP(msiof2_ss1_a),
  3286. SH_PFC_PIN_GROUP(msiof2_ss2_a),
  3287. SH_PFC_PIN_GROUP(msiof2_txd_a),
  3288. SH_PFC_PIN_GROUP(msiof2_rxd_a),
  3289. SH_PFC_PIN_GROUP(msiof2_clk_b),
  3290. SH_PFC_PIN_GROUP(msiof2_sync_b),
  3291. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  3292. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  3293. SH_PFC_PIN_GROUP(msiof2_txd_b),
  3294. SH_PFC_PIN_GROUP(msiof2_rxd_b),
  3295. SH_PFC_PIN_GROUP(msiof3_clk_a),
  3296. SH_PFC_PIN_GROUP(msiof3_sync_a),
  3297. SH_PFC_PIN_GROUP(msiof3_ss1_a),
  3298. SH_PFC_PIN_GROUP(msiof3_ss2_a),
  3299. SH_PFC_PIN_GROUP(msiof3_txd_a),
  3300. SH_PFC_PIN_GROUP(msiof3_rxd_a),
  3301. SH_PFC_PIN_GROUP(msiof3_clk_b),
  3302. SH_PFC_PIN_GROUP(msiof3_sync_b),
  3303. SH_PFC_PIN_GROUP(msiof3_ss1_b),
  3304. SH_PFC_PIN_GROUP(msiof3_txd_b),
  3305. SH_PFC_PIN_GROUP(msiof3_rxd_b),
  3306. SH_PFC_PIN_GROUP(pwm0_a),
  3307. SH_PFC_PIN_GROUP(pwm0_b),
  3308. SH_PFC_PIN_GROUP(pwm1_a),
  3309. SH_PFC_PIN_GROUP(pwm1_b),
  3310. SH_PFC_PIN_GROUP(pwm2_a),
  3311. SH_PFC_PIN_GROUP(pwm2_b),
  3312. SH_PFC_PIN_GROUP(pwm2_c),
  3313. SH_PFC_PIN_GROUP(pwm3_a),
  3314. SH_PFC_PIN_GROUP(pwm3_b),
  3315. SH_PFC_PIN_GROUP(pwm3_c),
  3316. SH_PFC_PIN_GROUP(pwm4_a),
  3317. SH_PFC_PIN_GROUP(pwm4_b),
  3318. SH_PFC_PIN_GROUP(pwm5_a),
  3319. SH_PFC_PIN_GROUP(pwm5_b),
  3320. SH_PFC_PIN_GROUP(pwm6_a),
  3321. SH_PFC_PIN_GROUP(pwm6_b),
  3322. SH_PFC_PIN_GROUP(qspi0_ctrl),
  3323. SH_PFC_PIN_GROUP(qspi0_data2),
  3324. SH_PFC_PIN_GROUP(qspi0_data4),
  3325. SH_PFC_PIN_GROUP(qspi1_ctrl),
  3326. SH_PFC_PIN_GROUP(qspi1_data2),
  3327. SH_PFC_PIN_GROUP(qspi1_data4),
  3328. SH_PFC_PIN_GROUP(scif0_data_a),
  3329. SH_PFC_PIN_GROUP(scif0_clk_a),
  3330. SH_PFC_PIN_GROUP(scif0_ctrl_a),
  3331. SH_PFC_PIN_GROUP(scif0_data_b),
  3332. SH_PFC_PIN_GROUP(scif0_clk_b),
  3333. SH_PFC_PIN_GROUP(scif1_data),
  3334. SH_PFC_PIN_GROUP(scif1_clk),
  3335. SH_PFC_PIN_GROUP(scif1_ctrl),
  3336. SH_PFC_PIN_GROUP(scif2_data_a),
  3337. SH_PFC_PIN_GROUP(scif2_clk_a),
  3338. SH_PFC_PIN_GROUP(scif2_data_b),
  3339. SH_PFC_PIN_GROUP(scif3_data_a),
  3340. SH_PFC_PIN_GROUP(scif3_clk_a),
  3341. SH_PFC_PIN_GROUP(scif3_ctrl_a),
  3342. SH_PFC_PIN_GROUP(scif3_data_b),
  3343. SH_PFC_PIN_GROUP(scif3_data_c),
  3344. SH_PFC_PIN_GROUP(scif3_clk_c),
  3345. SH_PFC_PIN_GROUP(scif4_data_a),
  3346. SH_PFC_PIN_GROUP(scif4_clk_a),
  3347. SH_PFC_PIN_GROUP(scif4_ctrl_a),
  3348. SH_PFC_PIN_GROUP(scif4_data_b),
  3349. SH_PFC_PIN_GROUP(scif4_clk_b),
  3350. SH_PFC_PIN_GROUP(scif4_data_c),
  3351. SH_PFC_PIN_GROUP(scif4_ctrl_c),
  3352. SH_PFC_PIN_GROUP(scif5_data_a),
  3353. SH_PFC_PIN_GROUP(scif5_clk_a),
  3354. SH_PFC_PIN_GROUP(scif5_data_b),
  3355. SH_PFC_PIN_GROUP(scif5_data_c),
  3356. SH_PFC_PIN_GROUP(scif_clk_a),
  3357. SH_PFC_PIN_GROUP(scif_clk_b),
  3358. SH_PFC_PIN_GROUP(sdhi0_data1),
  3359. SH_PFC_PIN_GROUP(sdhi0_data4),
  3360. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  3361. SH_PFC_PIN_GROUP(sdhi0_cd),
  3362. SH_PFC_PIN_GROUP(sdhi0_wp),
  3363. SH_PFC_PIN_GROUP(sdhi1_data1),
  3364. SH_PFC_PIN_GROUP(sdhi1_data4),
  3365. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  3366. SH_PFC_PIN_GROUP(sdhi1_cd),
  3367. SH_PFC_PIN_GROUP(sdhi1_wp),
  3368. SH_PFC_PIN_GROUP(sdhi3_data1),
  3369. SH_PFC_PIN_GROUP(sdhi3_data4),
  3370. SH_PFC_PIN_GROUP(sdhi3_data8),
  3371. SH_PFC_PIN_GROUP(sdhi3_ctrl),
  3372. SH_PFC_PIN_GROUP(sdhi3_cd),
  3373. SH_PFC_PIN_GROUP(sdhi3_wp),
  3374. SH_PFC_PIN_GROUP(sdhi3_ds),
  3375. SH_PFC_PIN_GROUP(ssi0_data),
  3376. SH_PFC_PIN_GROUP(ssi01239_ctrl),
  3377. SH_PFC_PIN_GROUP(ssi1_data),
  3378. SH_PFC_PIN_GROUP(ssi1_ctrl),
  3379. SH_PFC_PIN_GROUP(ssi2_data),
  3380. SH_PFC_PIN_GROUP(ssi2_ctrl_a),
  3381. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  3382. SH_PFC_PIN_GROUP(ssi3_data),
  3383. SH_PFC_PIN_GROUP(ssi349_ctrl),
  3384. SH_PFC_PIN_GROUP(ssi4_data),
  3385. SH_PFC_PIN_GROUP(ssi4_ctrl),
  3386. SH_PFC_PIN_GROUP(ssi5_data),
  3387. SH_PFC_PIN_GROUP(ssi5_ctrl),
  3388. SH_PFC_PIN_GROUP(ssi6_data),
  3389. SH_PFC_PIN_GROUP(ssi6_ctrl),
  3390. SH_PFC_PIN_GROUP(ssi7_data),
  3391. SH_PFC_PIN_GROUP(ssi78_ctrl),
  3392. SH_PFC_PIN_GROUP(ssi8_data),
  3393. SH_PFC_PIN_GROUP(ssi9_data),
  3394. SH_PFC_PIN_GROUP(ssi9_ctrl_a),
  3395. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  3396. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  3397. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  3398. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  3399. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  3400. SH_PFC_PIN_GROUP(usb0_a),
  3401. SH_PFC_PIN_GROUP(usb0_b),
  3402. SH_PFC_PIN_GROUP(usb0_id),
  3403. SH_PFC_PIN_GROUP(usb30),
  3404. SH_PFC_PIN_GROUP(usb30_id),
  3405. VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
  3406. VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
  3407. VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
  3408. VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
  3409. SH_PFC_PIN_GROUP(vin4_data18_a),
  3410. VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
  3411. VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
  3412. VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
  3413. VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
  3414. VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
  3415. VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
  3416. SH_PFC_PIN_GROUP(vin4_data18_b),
  3417. VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
  3418. VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
  3419. SH_PFC_PIN_GROUP(vin4_sync),
  3420. SH_PFC_PIN_GROUP(vin4_field),
  3421. SH_PFC_PIN_GROUP(vin4_clkenb),
  3422. SH_PFC_PIN_GROUP(vin4_clk),
  3423. VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
  3424. VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
  3425. VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
  3426. VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
  3427. SH_PFC_PIN_GROUP(vin5_data8_b),
  3428. SH_PFC_PIN_GROUP(vin5_sync_a),
  3429. SH_PFC_PIN_GROUP(vin5_field_a),
  3430. SH_PFC_PIN_GROUP(vin5_clkenb_a),
  3431. SH_PFC_PIN_GROUP(vin5_clk_a),
  3432. SH_PFC_PIN_GROUP(vin5_clk_b),
  3433. },
  3434. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  3435. .automotive = {
  3436. SH_PFC_PIN_GROUP(drif0_ctrl_a),
  3437. SH_PFC_PIN_GROUP(drif0_data0_a),
  3438. SH_PFC_PIN_GROUP(drif0_data1_a),
  3439. SH_PFC_PIN_GROUP(drif0_ctrl_b),
  3440. SH_PFC_PIN_GROUP(drif0_data0_b),
  3441. SH_PFC_PIN_GROUP(drif0_data1_b),
  3442. SH_PFC_PIN_GROUP(drif1_ctrl),
  3443. SH_PFC_PIN_GROUP(drif1_data0),
  3444. SH_PFC_PIN_GROUP(drif1_data1),
  3445. SH_PFC_PIN_GROUP(drif2_ctrl_a),
  3446. SH_PFC_PIN_GROUP(drif2_data0_a),
  3447. SH_PFC_PIN_GROUP(drif2_data1_a),
  3448. SH_PFC_PIN_GROUP(drif2_ctrl_b),
  3449. SH_PFC_PIN_GROUP(drif2_data0_b),
  3450. SH_PFC_PIN_GROUP(drif2_data1_b),
  3451. SH_PFC_PIN_GROUP(drif3_ctrl_a),
  3452. SH_PFC_PIN_GROUP(drif3_data0_a),
  3453. SH_PFC_PIN_GROUP(drif3_data1_a),
  3454. SH_PFC_PIN_GROUP(drif3_ctrl_b),
  3455. SH_PFC_PIN_GROUP(drif3_data0_b),
  3456. SH_PFC_PIN_GROUP(drif3_data1_b),
  3457. }
  3458. #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
  3459. };
  3460. static const char * const audio_clk_groups[] = {
  3461. "audio_clk_a",
  3462. "audio_clk_b_a",
  3463. "audio_clk_b_b",
  3464. "audio_clk_b_c",
  3465. "audio_clk_c_a",
  3466. "audio_clk_c_b",
  3467. "audio_clk_c_c",
  3468. "audio_clkout_a",
  3469. "audio_clkout_b",
  3470. "audio_clkout1_a",
  3471. "audio_clkout1_b",
  3472. "audio_clkout1_c",
  3473. "audio_clkout2_a",
  3474. "audio_clkout2_b",
  3475. "audio_clkout2_c",
  3476. "audio_clkout3_a",
  3477. "audio_clkout3_b",
  3478. "audio_clkout3_c",
  3479. };
  3480. static const char * const avb_groups[] = {
  3481. "avb_link",
  3482. "avb_magic",
  3483. "avb_phy_int",
  3484. "avb_mii",
  3485. "avb_avtp_pps",
  3486. "avb_avtp_match",
  3487. "avb_avtp_capture",
  3488. };
  3489. static const char * const can0_groups[] = {
  3490. "can0_data",
  3491. };
  3492. static const char * const can1_groups[] = {
  3493. "can1_data",
  3494. };
  3495. static const char * const can_clk_groups[] = {
  3496. "can_clk",
  3497. };
  3498. static const char * const canfd0_groups[] = {
  3499. "canfd0_data",
  3500. };
  3501. static const char * const canfd1_groups[] = {
  3502. "canfd1_data",
  3503. };
  3504. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  3505. static const char * const drif0_groups[] = {
  3506. "drif0_ctrl_a",
  3507. "drif0_data0_a",
  3508. "drif0_data1_a",
  3509. "drif0_ctrl_b",
  3510. "drif0_data0_b",
  3511. "drif0_data1_b",
  3512. };
  3513. static const char * const drif1_groups[] = {
  3514. "drif1_ctrl",
  3515. "drif1_data0",
  3516. "drif1_data1",
  3517. };
  3518. static const char * const drif2_groups[] = {
  3519. "drif2_ctrl_a",
  3520. "drif2_data0_a",
  3521. "drif2_data1_a",
  3522. "drif2_ctrl_b",
  3523. "drif2_data0_b",
  3524. "drif2_data1_b",
  3525. };
  3526. static const char * const drif3_groups[] = {
  3527. "drif3_ctrl_a",
  3528. "drif3_data0_a",
  3529. "drif3_data1_a",
  3530. "drif3_ctrl_b",
  3531. "drif3_data0_b",
  3532. "drif3_data1_b",
  3533. };
  3534. #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
  3535. static const char * const du_groups[] = {
  3536. "du_rgb666",
  3537. "du_rgb888",
  3538. "du_clk_in_0",
  3539. "du_clk_in_1",
  3540. "du_clk_out_0",
  3541. "du_sync",
  3542. "du_disp_cde",
  3543. "du_cde",
  3544. "du_disp",
  3545. };
  3546. static const char * const hscif0_groups[] = {
  3547. "hscif0_data_a",
  3548. "hscif0_clk_a",
  3549. "hscif0_ctrl_a",
  3550. "hscif0_data_b",
  3551. "hscif0_clk_b",
  3552. };
  3553. static const char * const hscif1_groups[] = {
  3554. "hscif1_data_a",
  3555. "hscif1_clk_a",
  3556. "hscif1_data_b",
  3557. "hscif1_clk_b",
  3558. "hscif1_ctrl_b",
  3559. };
  3560. static const char * const hscif2_groups[] = {
  3561. "hscif2_data_a",
  3562. "hscif2_clk_a",
  3563. "hscif2_ctrl_a",
  3564. "hscif2_data_b",
  3565. };
  3566. static const char * const hscif3_groups[] = {
  3567. "hscif3_data_a",
  3568. "hscif3_data_b",
  3569. "hscif3_clk_b",
  3570. "hscif3_data_c",
  3571. "hscif3_clk_c",
  3572. "hscif3_ctrl_c",
  3573. "hscif3_data_d",
  3574. "hscif3_data_e",
  3575. "hscif3_ctrl_e",
  3576. };
  3577. static const char * const hscif4_groups[] = {
  3578. "hscif4_data_a",
  3579. "hscif4_clk_a",
  3580. "hscif4_ctrl_a",
  3581. "hscif4_data_b",
  3582. "hscif4_clk_b",
  3583. "hscif4_data_c",
  3584. "hscif4_data_d",
  3585. "hscif4_data_e",
  3586. };
  3587. static const char * const i2c1_groups[] = {
  3588. "i2c1_a",
  3589. "i2c1_b",
  3590. "i2c1_c",
  3591. "i2c1_d",
  3592. };
  3593. static const char * const i2c2_groups[] = {
  3594. "i2c2_a",
  3595. "i2c2_b",
  3596. "i2c2_c",
  3597. "i2c2_d",
  3598. "i2c2_e",
  3599. };
  3600. static const char * const i2c4_groups[] = {
  3601. "i2c4",
  3602. };
  3603. static const char * const i2c5_groups[] = {
  3604. "i2c5",
  3605. };
  3606. static const char * const i2c6_groups[] = {
  3607. "i2c6_a",
  3608. "i2c6_b",
  3609. };
  3610. static const char * const i2c7_groups[] = {
  3611. "i2c7_a",
  3612. "i2c7_b",
  3613. };
  3614. static const char * const intc_ex_groups[] = {
  3615. "intc_ex_irq0",
  3616. "intc_ex_irq1",
  3617. "intc_ex_irq2",
  3618. "intc_ex_irq3",
  3619. "intc_ex_irq4",
  3620. "intc_ex_irq5",
  3621. };
  3622. static const char * const msiof0_groups[] = {
  3623. "msiof0_clk",
  3624. "msiof0_sync",
  3625. "msiof0_ss1",
  3626. "msiof0_ss2",
  3627. "msiof0_txd",
  3628. "msiof0_rxd",
  3629. };
  3630. static const char * const msiof1_groups[] = {
  3631. "msiof1_clk",
  3632. "msiof1_sync",
  3633. "msiof1_ss1",
  3634. "msiof1_ss2",
  3635. "msiof1_txd",
  3636. "msiof1_rxd",
  3637. };
  3638. static const char * const msiof2_groups[] = {
  3639. "msiof2_clk_a",
  3640. "msiof2_sync_a",
  3641. "msiof2_ss1_a",
  3642. "msiof2_ss2_a",
  3643. "msiof2_txd_a",
  3644. "msiof2_rxd_a",
  3645. "msiof2_clk_b",
  3646. "msiof2_sync_b",
  3647. "msiof2_ss1_b",
  3648. "msiof2_ss2_b",
  3649. "msiof2_txd_b",
  3650. "msiof2_rxd_b",
  3651. };
  3652. static const char * const msiof3_groups[] = {
  3653. "msiof3_clk_a",
  3654. "msiof3_sync_a",
  3655. "msiof3_ss1_a",
  3656. "msiof3_ss2_a",
  3657. "msiof3_txd_a",
  3658. "msiof3_rxd_a",
  3659. "msiof3_clk_b",
  3660. "msiof3_sync_b",
  3661. "msiof3_ss1_b",
  3662. "msiof3_txd_b",
  3663. "msiof3_rxd_b",
  3664. };
  3665. static const char * const pwm0_groups[] = {
  3666. "pwm0_a",
  3667. "pwm0_b",
  3668. };
  3669. static const char * const pwm1_groups[] = {
  3670. "pwm1_a",
  3671. "pwm1_b",
  3672. };
  3673. static const char * const pwm2_groups[] = {
  3674. "pwm2_a",
  3675. "pwm2_b",
  3676. "pwm2_c",
  3677. };
  3678. static const char * const pwm3_groups[] = {
  3679. "pwm3_a",
  3680. "pwm3_b",
  3681. "pwm3_c",
  3682. };
  3683. static const char * const pwm4_groups[] = {
  3684. "pwm4_a",
  3685. "pwm4_b",
  3686. };
  3687. static const char * const pwm5_groups[] = {
  3688. "pwm5_a",
  3689. "pwm5_b",
  3690. };
  3691. static const char * const pwm6_groups[] = {
  3692. "pwm6_a",
  3693. "pwm6_b",
  3694. };
  3695. static const char * const qspi0_groups[] = {
  3696. "qspi0_ctrl",
  3697. "qspi0_data2",
  3698. "qspi0_data4",
  3699. };
  3700. static const char * const qspi1_groups[] = {
  3701. "qspi1_ctrl",
  3702. "qspi1_data2",
  3703. "qspi1_data4",
  3704. };
  3705. static const char * const scif0_groups[] = {
  3706. "scif0_data_a",
  3707. "scif0_clk_a",
  3708. "scif0_ctrl_a",
  3709. "scif0_data_b",
  3710. "scif0_clk_b",
  3711. };
  3712. static const char * const scif1_groups[] = {
  3713. "scif1_data",
  3714. "scif1_clk",
  3715. "scif1_ctrl",
  3716. };
  3717. static const char * const scif2_groups[] = {
  3718. "scif2_data_a",
  3719. "scif2_clk_a",
  3720. "scif2_data_b",
  3721. };
  3722. static const char * const scif3_groups[] = {
  3723. "scif3_data_a",
  3724. "scif3_clk_a",
  3725. "scif3_ctrl_a",
  3726. "scif3_data_b",
  3727. "scif3_data_c",
  3728. "scif3_clk_c",
  3729. };
  3730. static const char * const scif4_groups[] = {
  3731. "scif4_data_a",
  3732. "scif4_clk_a",
  3733. "scif4_ctrl_a",
  3734. "scif4_data_b",
  3735. "scif4_clk_b",
  3736. "scif4_data_c",
  3737. "scif4_ctrl_c",
  3738. };
  3739. static const char * const scif5_groups[] = {
  3740. "scif5_data_a",
  3741. "scif5_clk_a",
  3742. "scif5_data_b",
  3743. "scif5_data_c",
  3744. };
  3745. static const char * const scif_clk_groups[] = {
  3746. "scif_clk_a",
  3747. "scif_clk_b",
  3748. };
  3749. static const char * const sdhi0_groups[] = {
  3750. "sdhi0_data1",
  3751. "sdhi0_data4",
  3752. "sdhi0_ctrl",
  3753. "sdhi0_cd",
  3754. "sdhi0_wp",
  3755. };
  3756. static const char * const sdhi1_groups[] = {
  3757. "sdhi1_data1",
  3758. "sdhi1_data4",
  3759. "sdhi1_ctrl",
  3760. "sdhi1_cd",
  3761. "sdhi1_wp",
  3762. };
  3763. static const char * const sdhi3_groups[] = {
  3764. "sdhi3_data1",
  3765. "sdhi3_data4",
  3766. "sdhi3_data8",
  3767. "sdhi3_ctrl",
  3768. "sdhi3_cd",
  3769. "sdhi3_wp",
  3770. "sdhi3_ds",
  3771. };
  3772. static const char * const ssi_groups[] = {
  3773. "ssi0_data",
  3774. "ssi01239_ctrl",
  3775. "ssi1_data",
  3776. "ssi1_ctrl",
  3777. "ssi2_data",
  3778. "ssi2_ctrl_a",
  3779. "ssi2_ctrl_b",
  3780. "ssi3_data",
  3781. "ssi349_ctrl",
  3782. "ssi4_data",
  3783. "ssi4_ctrl",
  3784. "ssi5_data",
  3785. "ssi5_ctrl",
  3786. "ssi6_data",
  3787. "ssi6_ctrl",
  3788. "ssi7_data",
  3789. "ssi78_ctrl",
  3790. "ssi8_data",
  3791. "ssi9_data",
  3792. "ssi9_ctrl_a",
  3793. "ssi9_ctrl_b",
  3794. };
  3795. static const char * const tmu_groups[] = {
  3796. "tmu_tclk1_a",
  3797. "tmu_tclk1_b",
  3798. "tmu_tclk2_a",
  3799. "tmu_tclk2_b",
  3800. };
  3801. static const char * const usb0_groups[] = {
  3802. "usb0_a",
  3803. "usb0_b",
  3804. "usb0_id",
  3805. };
  3806. static const char * const usb30_groups[] = {
  3807. "usb30",
  3808. "usb30_id",
  3809. };
  3810. static const char * const vin4_groups[] = {
  3811. "vin4_data8_a",
  3812. "vin4_data10_a",
  3813. "vin4_data12_a",
  3814. "vin4_data16_a",
  3815. "vin4_data18_a",
  3816. "vin4_data20_a",
  3817. "vin4_data24_a",
  3818. "vin4_data8_b",
  3819. "vin4_data10_b",
  3820. "vin4_data12_b",
  3821. "vin4_data16_b",
  3822. "vin4_data18_b",
  3823. "vin4_data20_b",
  3824. "vin4_data24_b",
  3825. "vin4_sync",
  3826. "vin4_field",
  3827. "vin4_clkenb",
  3828. "vin4_clk",
  3829. };
  3830. static const char * const vin5_groups[] = {
  3831. "vin5_data8_a",
  3832. "vin5_data10_a",
  3833. "vin5_data12_a",
  3834. "vin5_data16_a",
  3835. "vin5_data8_b",
  3836. "vin5_sync_a",
  3837. "vin5_field_a",
  3838. "vin5_clkenb_a",
  3839. "vin5_clk_a",
  3840. "vin5_clk_b",
  3841. };
  3842. static const struct {
  3843. struct sh_pfc_function common[49];
  3844. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  3845. struct sh_pfc_function automotive[4];
  3846. #endif
  3847. } pinmux_functions = {
  3848. .common = {
  3849. SH_PFC_FUNCTION(audio_clk),
  3850. SH_PFC_FUNCTION(avb),
  3851. SH_PFC_FUNCTION(can0),
  3852. SH_PFC_FUNCTION(can1),
  3853. SH_PFC_FUNCTION(can_clk),
  3854. SH_PFC_FUNCTION(canfd0),
  3855. SH_PFC_FUNCTION(canfd1),
  3856. SH_PFC_FUNCTION(du),
  3857. SH_PFC_FUNCTION(hscif0),
  3858. SH_PFC_FUNCTION(hscif1),
  3859. SH_PFC_FUNCTION(hscif2),
  3860. SH_PFC_FUNCTION(hscif3),
  3861. SH_PFC_FUNCTION(hscif4),
  3862. SH_PFC_FUNCTION(i2c1),
  3863. SH_PFC_FUNCTION(i2c2),
  3864. SH_PFC_FUNCTION(i2c4),
  3865. SH_PFC_FUNCTION(i2c5),
  3866. SH_PFC_FUNCTION(i2c6),
  3867. SH_PFC_FUNCTION(i2c7),
  3868. SH_PFC_FUNCTION(intc_ex),
  3869. SH_PFC_FUNCTION(msiof0),
  3870. SH_PFC_FUNCTION(msiof1),
  3871. SH_PFC_FUNCTION(msiof2),
  3872. SH_PFC_FUNCTION(msiof3),
  3873. SH_PFC_FUNCTION(pwm0),
  3874. SH_PFC_FUNCTION(pwm1),
  3875. SH_PFC_FUNCTION(pwm2),
  3876. SH_PFC_FUNCTION(pwm3),
  3877. SH_PFC_FUNCTION(pwm4),
  3878. SH_PFC_FUNCTION(pwm5),
  3879. SH_PFC_FUNCTION(pwm6),
  3880. SH_PFC_FUNCTION(qspi0),
  3881. SH_PFC_FUNCTION(qspi1),
  3882. SH_PFC_FUNCTION(scif0),
  3883. SH_PFC_FUNCTION(scif1),
  3884. SH_PFC_FUNCTION(scif2),
  3885. SH_PFC_FUNCTION(scif3),
  3886. SH_PFC_FUNCTION(scif4),
  3887. SH_PFC_FUNCTION(scif5),
  3888. SH_PFC_FUNCTION(scif_clk),
  3889. SH_PFC_FUNCTION(sdhi0),
  3890. SH_PFC_FUNCTION(sdhi1),
  3891. SH_PFC_FUNCTION(sdhi3),
  3892. SH_PFC_FUNCTION(ssi),
  3893. SH_PFC_FUNCTION(tmu),
  3894. SH_PFC_FUNCTION(usb0),
  3895. SH_PFC_FUNCTION(usb30),
  3896. SH_PFC_FUNCTION(vin4),
  3897. SH_PFC_FUNCTION(vin5),
  3898. },
  3899. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  3900. .automotive = {
  3901. SH_PFC_FUNCTION(drif0),
  3902. SH_PFC_FUNCTION(drif1),
  3903. SH_PFC_FUNCTION(drif2),
  3904. SH_PFC_FUNCTION(drif3),
  3905. }
  3906. #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
  3907. };
  3908. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  3909. #define F_(x, y) FN_##y
  3910. #define FM(x) FN_##x
  3911. { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
  3912. 0, 0,
  3913. 0, 0,
  3914. 0, 0,
  3915. 0, 0,
  3916. 0, 0,
  3917. 0, 0,
  3918. 0, 0,
  3919. 0, 0,
  3920. 0, 0,
  3921. 0, 0,
  3922. 0, 0,
  3923. 0, 0,
  3924. 0, 0,
  3925. 0, 0,
  3926. GP_0_17_FN, GPSR0_17,
  3927. GP_0_16_FN, GPSR0_16,
  3928. GP_0_15_FN, GPSR0_15,
  3929. GP_0_14_FN, GPSR0_14,
  3930. GP_0_13_FN, GPSR0_13,
  3931. GP_0_12_FN, GPSR0_12,
  3932. GP_0_11_FN, GPSR0_11,
  3933. GP_0_10_FN, GPSR0_10,
  3934. GP_0_9_FN, GPSR0_9,
  3935. GP_0_8_FN, GPSR0_8,
  3936. GP_0_7_FN, GPSR0_7,
  3937. GP_0_6_FN, GPSR0_6,
  3938. GP_0_5_FN, GPSR0_5,
  3939. GP_0_4_FN, GPSR0_4,
  3940. GP_0_3_FN, GPSR0_3,
  3941. GP_0_2_FN, GPSR0_2,
  3942. GP_0_1_FN, GPSR0_1,
  3943. GP_0_0_FN, GPSR0_0, ))
  3944. },
  3945. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  3946. 0, 0,
  3947. 0, 0,
  3948. 0, 0,
  3949. 0, 0,
  3950. 0, 0,
  3951. 0, 0,
  3952. 0, 0,
  3953. 0, 0,
  3954. 0, 0,
  3955. GP_1_22_FN, GPSR1_22,
  3956. GP_1_21_FN, GPSR1_21,
  3957. GP_1_20_FN, GPSR1_20,
  3958. GP_1_19_FN, GPSR1_19,
  3959. GP_1_18_FN, GPSR1_18,
  3960. GP_1_17_FN, GPSR1_17,
  3961. GP_1_16_FN, GPSR1_16,
  3962. GP_1_15_FN, GPSR1_15,
  3963. GP_1_14_FN, GPSR1_14,
  3964. GP_1_13_FN, GPSR1_13,
  3965. GP_1_12_FN, GPSR1_12,
  3966. GP_1_11_FN, GPSR1_11,
  3967. GP_1_10_FN, GPSR1_10,
  3968. GP_1_9_FN, GPSR1_9,
  3969. GP_1_8_FN, GPSR1_8,
  3970. GP_1_7_FN, GPSR1_7,
  3971. GP_1_6_FN, GPSR1_6,
  3972. GP_1_5_FN, GPSR1_5,
  3973. GP_1_4_FN, GPSR1_4,
  3974. GP_1_3_FN, GPSR1_3,
  3975. GP_1_2_FN, GPSR1_2,
  3976. GP_1_1_FN, GPSR1_1,
  3977. GP_1_0_FN, GPSR1_0, ))
  3978. },
  3979. { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
  3980. 0, 0,
  3981. 0, 0,
  3982. 0, 0,
  3983. 0, 0,
  3984. 0, 0,
  3985. 0, 0,
  3986. GP_2_25_FN, GPSR2_25,
  3987. GP_2_24_FN, GPSR2_24,
  3988. GP_2_23_FN, GPSR2_23,
  3989. GP_2_22_FN, GPSR2_22,
  3990. GP_2_21_FN, GPSR2_21,
  3991. GP_2_20_FN, GPSR2_20,
  3992. GP_2_19_FN, GPSR2_19,
  3993. GP_2_18_FN, GPSR2_18,
  3994. GP_2_17_FN, GPSR2_17,
  3995. GP_2_16_FN, GPSR2_16,
  3996. GP_2_15_FN, GPSR2_15,
  3997. GP_2_14_FN, GPSR2_14,
  3998. GP_2_13_FN, GPSR2_13,
  3999. GP_2_12_FN, GPSR2_12,
  4000. GP_2_11_FN, GPSR2_11,
  4001. GP_2_10_FN, GPSR2_10,
  4002. GP_2_9_FN, GPSR2_9,
  4003. GP_2_8_FN, GPSR2_8,
  4004. GP_2_7_FN, GPSR2_7,
  4005. GP_2_6_FN, GPSR2_6,
  4006. GP_2_5_FN, GPSR2_5,
  4007. GP_2_4_FN, GPSR2_4,
  4008. GP_2_3_FN, GPSR2_3,
  4009. GP_2_2_FN, GPSR2_2,
  4010. GP_2_1_FN, GPSR2_1,
  4011. GP_2_0_FN, GPSR2_0, ))
  4012. },
  4013. { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
  4014. 0, 0,
  4015. 0, 0,
  4016. 0, 0,
  4017. 0, 0,
  4018. 0, 0,
  4019. 0, 0,
  4020. 0, 0,
  4021. 0, 0,
  4022. 0, 0,
  4023. 0, 0,
  4024. 0, 0,
  4025. 0, 0,
  4026. 0, 0,
  4027. 0, 0,
  4028. 0, 0,
  4029. 0, 0,
  4030. GP_3_15_FN, GPSR3_15,
  4031. GP_3_14_FN, GPSR3_14,
  4032. GP_3_13_FN, GPSR3_13,
  4033. GP_3_12_FN, GPSR3_12,
  4034. GP_3_11_FN, GPSR3_11,
  4035. GP_3_10_FN, GPSR3_10,
  4036. GP_3_9_FN, GPSR3_9,
  4037. GP_3_8_FN, GPSR3_8,
  4038. GP_3_7_FN, GPSR3_7,
  4039. GP_3_6_FN, GPSR3_6,
  4040. GP_3_5_FN, GPSR3_5,
  4041. GP_3_4_FN, GPSR3_4,
  4042. GP_3_3_FN, GPSR3_3,
  4043. GP_3_2_FN, GPSR3_2,
  4044. GP_3_1_FN, GPSR3_1,
  4045. GP_3_0_FN, GPSR3_0, ))
  4046. },
  4047. { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
  4048. 0, 0,
  4049. 0, 0,
  4050. 0, 0,
  4051. 0, 0,
  4052. 0, 0,
  4053. 0, 0,
  4054. 0, 0,
  4055. 0, 0,
  4056. 0, 0,
  4057. 0, 0,
  4058. 0, 0,
  4059. 0, 0,
  4060. 0, 0,
  4061. 0, 0,
  4062. 0, 0,
  4063. 0, 0,
  4064. 0, 0,
  4065. 0, 0,
  4066. 0, 0,
  4067. 0, 0,
  4068. 0, 0,
  4069. GP_4_10_FN, GPSR4_10,
  4070. GP_4_9_FN, GPSR4_9,
  4071. GP_4_8_FN, GPSR4_8,
  4072. GP_4_7_FN, GPSR4_7,
  4073. GP_4_6_FN, GPSR4_6,
  4074. GP_4_5_FN, GPSR4_5,
  4075. GP_4_4_FN, GPSR4_4,
  4076. GP_4_3_FN, GPSR4_3,
  4077. GP_4_2_FN, GPSR4_2,
  4078. GP_4_1_FN, GPSR4_1,
  4079. GP_4_0_FN, GPSR4_0, ))
  4080. },
  4081. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  4082. 0, 0,
  4083. 0, 0,
  4084. 0, 0,
  4085. 0, 0,
  4086. 0, 0,
  4087. 0, 0,
  4088. 0, 0,
  4089. 0, 0,
  4090. 0, 0,
  4091. 0, 0,
  4092. 0, 0,
  4093. 0, 0,
  4094. GP_5_19_FN, GPSR5_19,
  4095. GP_5_18_FN, GPSR5_18,
  4096. GP_5_17_FN, GPSR5_17,
  4097. GP_5_16_FN, GPSR5_16,
  4098. GP_5_15_FN, GPSR5_15,
  4099. GP_5_14_FN, GPSR5_14,
  4100. GP_5_13_FN, GPSR5_13,
  4101. GP_5_12_FN, GPSR5_12,
  4102. GP_5_11_FN, GPSR5_11,
  4103. GP_5_10_FN, GPSR5_10,
  4104. GP_5_9_FN, GPSR5_9,
  4105. GP_5_8_FN, GPSR5_8,
  4106. GP_5_7_FN, GPSR5_7,
  4107. GP_5_6_FN, GPSR5_6,
  4108. GP_5_5_FN, GPSR5_5,
  4109. GP_5_4_FN, GPSR5_4,
  4110. GP_5_3_FN, GPSR5_3,
  4111. GP_5_2_FN, GPSR5_2,
  4112. GP_5_1_FN, GPSR5_1,
  4113. GP_5_0_FN, GPSR5_0, ))
  4114. },
  4115. { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
  4116. 0, 0,
  4117. 0, 0,
  4118. 0, 0,
  4119. 0, 0,
  4120. 0, 0,
  4121. 0, 0,
  4122. 0, 0,
  4123. 0, 0,
  4124. 0, 0,
  4125. 0, 0,
  4126. 0, 0,
  4127. 0, 0,
  4128. 0, 0,
  4129. 0, 0,
  4130. GP_6_17_FN, GPSR6_17,
  4131. GP_6_16_FN, GPSR6_16,
  4132. GP_6_15_FN, GPSR6_15,
  4133. GP_6_14_FN, GPSR6_14,
  4134. GP_6_13_FN, GPSR6_13,
  4135. GP_6_12_FN, GPSR6_12,
  4136. GP_6_11_FN, GPSR6_11,
  4137. GP_6_10_FN, GPSR6_10,
  4138. GP_6_9_FN, GPSR6_9,
  4139. GP_6_8_FN, GPSR6_8,
  4140. GP_6_7_FN, GPSR6_7,
  4141. GP_6_6_FN, GPSR6_6,
  4142. GP_6_5_FN, GPSR6_5,
  4143. GP_6_4_FN, GPSR6_4,
  4144. GP_6_3_FN, GPSR6_3,
  4145. GP_6_2_FN, GPSR6_2,
  4146. GP_6_1_FN, GPSR6_1,
  4147. GP_6_0_FN, GPSR6_0, ))
  4148. },
  4149. #undef F_
  4150. #undef FM
  4151. #define F_(x, y) x,
  4152. #define FM(x) FN_##x,
  4153. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  4154. IP0_31_28
  4155. IP0_27_24
  4156. IP0_23_20
  4157. IP0_19_16
  4158. IP0_15_12
  4159. IP0_11_8
  4160. IP0_7_4
  4161. IP0_3_0 ))
  4162. },
  4163. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  4164. IP1_31_28
  4165. IP1_27_24
  4166. IP1_23_20
  4167. IP1_19_16
  4168. IP1_15_12
  4169. IP1_11_8
  4170. IP1_7_4
  4171. IP1_3_0 ))
  4172. },
  4173. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  4174. IP2_31_28
  4175. IP2_27_24
  4176. IP2_23_20
  4177. IP2_19_16
  4178. IP2_15_12
  4179. IP2_11_8
  4180. IP2_7_4
  4181. IP2_3_0 ))
  4182. },
  4183. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  4184. IP3_31_28
  4185. IP3_27_24
  4186. IP3_23_20
  4187. IP3_19_16
  4188. IP3_15_12
  4189. IP3_11_8
  4190. IP3_7_4
  4191. IP3_3_0 ))
  4192. },
  4193. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  4194. IP4_31_28
  4195. IP4_27_24
  4196. IP4_23_20
  4197. IP4_19_16
  4198. IP4_15_12
  4199. IP4_11_8
  4200. IP4_7_4
  4201. IP4_3_0 ))
  4202. },
  4203. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  4204. IP5_31_28
  4205. IP5_27_24
  4206. IP5_23_20
  4207. IP5_19_16
  4208. IP5_15_12
  4209. IP5_11_8
  4210. IP5_7_4
  4211. IP5_3_0 ))
  4212. },
  4213. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  4214. IP6_31_28
  4215. IP6_27_24
  4216. IP6_23_20
  4217. IP6_19_16
  4218. IP6_15_12
  4219. IP6_11_8
  4220. IP6_7_4
  4221. IP6_3_0 ))
  4222. },
  4223. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  4224. IP7_31_28
  4225. IP7_27_24
  4226. IP7_23_20
  4227. IP7_19_16
  4228. IP7_15_12
  4229. IP7_11_8
  4230. IP7_7_4
  4231. IP7_3_0 ))
  4232. },
  4233. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  4234. IP8_31_28
  4235. IP8_27_24
  4236. IP8_23_20
  4237. IP8_19_16
  4238. IP8_15_12
  4239. IP8_11_8
  4240. IP8_7_4
  4241. IP8_3_0 ))
  4242. },
  4243. { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
  4244. IP9_31_28
  4245. IP9_27_24
  4246. IP9_23_20
  4247. IP9_19_16
  4248. IP9_15_12
  4249. IP9_11_8
  4250. IP9_7_4
  4251. IP9_3_0 ))
  4252. },
  4253. { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
  4254. IP10_31_28
  4255. IP10_27_24
  4256. IP10_23_20
  4257. IP10_19_16
  4258. IP10_15_12
  4259. IP10_11_8
  4260. IP10_7_4
  4261. IP10_3_0 ))
  4262. },
  4263. { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
  4264. IP11_31_28
  4265. IP11_27_24
  4266. IP11_23_20
  4267. IP11_19_16
  4268. IP11_15_12
  4269. IP11_11_8
  4270. IP11_7_4
  4271. IP11_3_0 ))
  4272. },
  4273. { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
  4274. IP12_31_28
  4275. IP12_27_24
  4276. IP12_23_20
  4277. IP12_19_16
  4278. IP12_15_12
  4279. IP12_11_8
  4280. IP12_7_4
  4281. IP12_3_0 ))
  4282. },
  4283. { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
  4284. IP13_31_28
  4285. IP13_27_24
  4286. IP13_23_20
  4287. IP13_19_16
  4288. IP13_15_12
  4289. IP13_11_8
  4290. IP13_7_4
  4291. IP13_3_0 ))
  4292. },
  4293. { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
  4294. IP14_31_28
  4295. IP14_27_24
  4296. IP14_23_20
  4297. IP14_19_16
  4298. IP14_15_12
  4299. IP14_11_8
  4300. IP14_7_4
  4301. IP14_3_0 ))
  4302. },
  4303. { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
  4304. IP15_31_28
  4305. IP15_27_24
  4306. IP15_23_20
  4307. IP15_19_16
  4308. IP15_15_12
  4309. IP15_11_8
  4310. IP15_7_4
  4311. IP15_3_0 ))
  4312. },
  4313. #undef F_
  4314. #undef FM
  4315. #define F_(x, y) x,
  4316. #define FM(x) FN_##x,
  4317. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  4318. GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
  4319. 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
  4320. GROUP(
  4321. /* RESERVED 31 */
  4322. 0, 0,
  4323. MOD_SEL0_30_29
  4324. MOD_SEL0_28
  4325. MOD_SEL0_27_26
  4326. MOD_SEL0_25
  4327. MOD_SEL0_24
  4328. MOD_SEL0_23
  4329. MOD_SEL0_22
  4330. MOD_SEL0_21_20
  4331. MOD_SEL0_19_18_17
  4332. MOD_SEL0_16
  4333. MOD_SEL0_15
  4334. MOD_SEL0_14
  4335. MOD_SEL0_13_12
  4336. MOD_SEL0_11_10
  4337. MOD_SEL0_9
  4338. MOD_SEL0_8
  4339. MOD_SEL0_7
  4340. MOD_SEL0_6_5
  4341. MOD_SEL0_4
  4342. MOD_SEL0_3
  4343. MOD_SEL0_2
  4344. MOD_SEL0_1_0 ))
  4345. },
  4346. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
  4347. GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
  4348. 1, 2, 2, 2, 1, 1, 2, 1, 4),
  4349. GROUP(
  4350. MOD_SEL1_31
  4351. MOD_SEL1_30
  4352. MOD_SEL1_29
  4353. MOD_SEL1_28
  4354. /* RESERVED 27 */
  4355. 0, 0,
  4356. MOD_SEL1_26
  4357. MOD_SEL1_25
  4358. MOD_SEL1_24_23_22
  4359. MOD_SEL1_21_20_19
  4360. MOD_SEL1_18
  4361. MOD_SEL1_17
  4362. MOD_SEL1_16
  4363. MOD_SEL1_15
  4364. MOD_SEL1_14_13
  4365. MOD_SEL1_12_11
  4366. MOD_SEL1_10_9
  4367. MOD_SEL1_8
  4368. MOD_SEL1_7
  4369. MOD_SEL1_6_5
  4370. MOD_SEL1_4
  4371. /* RESERVED 3, 2, 1, 0 */
  4372. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
  4373. },
  4374. { },
  4375. };
  4376. enum ioctrl_regs {
  4377. POCCTRL0,
  4378. TDSELCTRL,
  4379. };
  4380. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  4381. [POCCTRL0] = { 0xe6060380, },
  4382. [TDSELCTRL] = { 0xe60603c0, },
  4383. { /* sentinel */ },
  4384. };
  4385. static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
  4386. u32 *pocctrl)
  4387. {
  4388. int bit = -EINVAL;
  4389. *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
  4390. if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
  4391. bit = pin & 0x1f;
  4392. if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
  4393. bit = (pin & 0x1f) + 19;
  4394. return bit;
  4395. }
  4396. static const struct pinmux_bias_reg pinmux_bias_regs[] = {
  4397. { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
  4398. [0] = RCAR_GP_PIN(2, 23), /* RD# */
  4399. [1] = RCAR_GP_PIN(2, 22), /* BS# */
  4400. [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
  4401. [3] = PIN_AVB_MDC, /* AVB_MDC */
  4402. [4] = PIN_AVB_MDIO, /* AVB_MDIO */
  4403. [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
  4404. [6] = PIN_AVB_TD3, /* AVB_TD3 */
  4405. [7] = PIN_AVB_TD2, /* AVB_TD2 */
  4406. [8] = PIN_AVB_TD1, /* AVB_TD1 */
  4407. [9] = PIN_AVB_TD0, /* AVB_TD0 */
  4408. [10] = PIN_AVB_TXC, /* AVB_TXC */
  4409. [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
  4410. [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
  4411. [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
  4412. [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
  4413. [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */
  4414. [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */
  4415. [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */
  4416. [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */
  4417. [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */
  4418. [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */
  4419. [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */
  4420. [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */
  4421. [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */
  4422. [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */
  4423. [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */
  4424. [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */
  4425. [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */
  4426. [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */
  4427. [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */
  4428. [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */
  4429. [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */
  4430. } },
  4431. { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
  4432. [0] = RCAR_GP_PIN(0, 4), /* D4 */
  4433. [1] = RCAR_GP_PIN(0, 3), /* D3 */
  4434. [2] = RCAR_GP_PIN(0, 2), /* D2 */
  4435. [3] = RCAR_GP_PIN(0, 1), /* D1 */
  4436. [4] = RCAR_GP_PIN(0, 0), /* D0 */
  4437. [5] = RCAR_GP_PIN(1, 22), /* WE0# */
  4438. [6] = RCAR_GP_PIN(1, 21), /* CS0# */
  4439. [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */
  4440. [8] = RCAR_GP_PIN(1, 19), /* A19 */
  4441. [9] = RCAR_GP_PIN(1, 18), /* A18 */
  4442. [10] = RCAR_GP_PIN(1, 17), /* A17 */
  4443. [11] = RCAR_GP_PIN(1, 16), /* A16 */
  4444. [12] = RCAR_GP_PIN(1, 15), /* A15 */
  4445. [13] = RCAR_GP_PIN(1, 14), /* A14 */
  4446. [14] = RCAR_GP_PIN(1, 13), /* A13 */
  4447. [15] = RCAR_GP_PIN(1, 12), /* A12 */
  4448. [16] = RCAR_GP_PIN(1, 11), /* A11 */
  4449. [17] = RCAR_GP_PIN(1, 10), /* A10 */
  4450. [18] = RCAR_GP_PIN(1, 9), /* A9 */
  4451. [19] = RCAR_GP_PIN(1, 8), /* A8 */
  4452. [20] = RCAR_GP_PIN(1, 7), /* A7 */
  4453. [21] = RCAR_GP_PIN(1, 6), /* A6 */
  4454. [22] = RCAR_GP_PIN(1, 5), /* A5 */
  4455. [23] = RCAR_GP_PIN(1, 4), /* A4 */
  4456. [24] = RCAR_GP_PIN(1, 3), /* A3 */
  4457. [25] = RCAR_GP_PIN(1, 2), /* A2 */
  4458. [26] = RCAR_GP_PIN(1, 1), /* A1 */
  4459. [27] = RCAR_GP_PIN(1, 0), /* A0 */
  4460. [28] = SH_PFC_PIN_NONE,
  4461. [29] = SH_PFC_PIN_NONE,
  4462. [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
  4463. [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
  4464. } },
  4465. { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
  4466. [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
  4467. [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
  4468. [2] = PIN_ASEBRK, /* ASEBRK */
  4469. [3] = SH_PFC_PIN_NONE,
  4470. [4] = PIN_TDI, /* TDI */
  4471. [5] = PIN_TMS, /* TMS */
  4472. [6] = PIN_TCK, /* TCK */
  4473. [7] = PIN_TRST_N, /* TRST# */
  4474. [8] = SH_PFC_PIN_NONE,
  4475. [9] = SH_PFC_PIN_NONE,
  4476. [10] = SH_PFC_PIN_NONE,
  4477. [11] = SH_PFC_PIN_NONE,
  4478. [12] = SH_PFC_PIN_NONE,
  4479. [13] = SH_PFC_PIN_NONE,
  4480. [14] = SH_PFC_PIN_NONE,
  4481. [15] = PIN_FSCLKST_N, /* FSCLKST# */
  4482. [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
  4483. [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
  4484. [18] = SH_PFC_PIN_NONE,
  4485. [19] = SH_PFC_PIN_NONE,
  4486. [20] = PIN_PRESETOUT_N, /* PRESETOUT# */
  4487. [21] = RCAR_GP_PIN(0, 15), /* D15 */
  4488. [22] = RCAR_GP_PIN(0, 14), /* D14 */
  4489. [23] = RCAR_GP_PIN(0, 13), /* D13 */
  4490. [24] = RCAR_GP_PIN(0, 12), /* D12 */
  4491. [25] = RCAR_GP_PIN(0, 11), /* D11 */
  4492. [26] = RCAR_GP_PIN(0, 10), /* D10 */
  4493. [27] = RCAR_GP_PIN(0, 9), /* D9 */
  4494. [28] = RCAR_GP_PIN(0, 8), /* D8 */
  4495. [29] = RCAR_GP_PIN(0, 7), /* D7 */
  4496. [30] = RCAR_GP_PIN(0, 6), /* D6 */
  4497. [31] = RCAR_GP_PIN(0, 5), /* D5 */
  4498. } },
  4499. { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
  4500. [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
  4501. [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
  4502. [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
  4503. [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
  4504. [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
  4505. [5] = SH_PFC_PIN_NONE,
  4506. [6] = SH_PFC_PIN_NONE,
  4507. [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
  4508. [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
  4509. [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
  4510. [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */
  4511. [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */
  4512. [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */
  4513. [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */
  4514. [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */
  4515. [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */
  4516. [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */
  4517. [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */
  4518. [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
  4519. [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */
  4520. [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */
  4521. [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */
  4522. [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
  4523. [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
  4524. [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
  4525. [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
  4526. [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
  4527. [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
  4528. [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
  4529. [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
  4530. [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
  4531. [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
  4532. } },
  4533. { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
  4534. [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */
  4535. [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
  4536. [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
  4537. [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
  4538. [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
  4539. [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
  4540. [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
  4541. [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
  4542. [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
  4543. [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
  4544. [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
  4545. [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */
  4546. [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */
  4547. [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
  4548. [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
  4549. [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
  4550. [16] = PIN_MLB_REF, /* MLB_REF */
  4551. [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
  4552. [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
  4553. [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
  4554. [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */
  4555. [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */
  4556. [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
  4557. [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
  4558. [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */
  4559. [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */
  4560. [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */
  4561. [27] = RCAR_GP_PIN(5, 9), /* RX2_A */
  4562. [28] = RCAR_GP_PIN(5, 8), /* TX2_A */
  4563. [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */
  4564. [30] = RCAR_GP_PIN(5, 6), /* TX1 */
  4565. [31] = RCAR_GP_PIN(5, 5), /* RX1 */
  4566. } },
  4567. { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
  4568. [0] = SH_PFC_PIN_NONE,
  4569. [1] = SH_PFC_PIN_NONE,
  4570. [2] = SH_PFC_PIN_NONE,
  4571. [3] = SH_PFC_PIN_NONE,
  4572. [4] = SH_PFC_PIN_NONE,
  4573. [5] = SH_PFC_PIN_NONE,
  4574. [6] = SH_PFC_PIN_NONE,
  4575. [7] = SH_PFC_PIN_NONE,
  4576. [8] = SH_PFC_PIN_NONE,
  4577. [9] = SH_PFC_PIN_NONE,
  4578. [10] = SH_PFC_PIN_NONE,
  4579. [11] = SH_PFC_PIN_NONE,
  4580. [12] = SH_PFC_PIN_NONE,
  4581. [13] = SH_PFC_PIN_NONE,
  4582. [14] = SH_PFC_PIN_NONE,
  4583. [15] = SH_PFC_PIN_NONE,
  4584. [16] = SH_PFC_PIN_NONE,
  4585. [17] = SH_PFC_PIN_NONE,
  4586. [18] = SH_PFC_PIN_NONE,
  4587. [19] = SH_PFC_PIN_NONE,
  4588. [20] = SH_PFC_PIN_NONE,
  4589. [21] = SH_PFC_PIN_NONE,
  4590. [22] = SH_PFC_PIN_NONE,
  4591. [23] = SH_PFC_PIN_NONE,
  4592. [24] = SH_PFC_PIN_NONE,
  4593. [25] = SH_PFC_PIN_NONE,
  4594. [26] = SH_PFC_PIN_NONE,
  4595. [27] = SH_PFC_PIN_NONE,
  4596. [28] = SH_PFC_PIN_NONE,
  4597. [29] = SH_PFC_PIN_NONE,
  4598. [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
  4599. [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
  4600. } },
  4601. { /* sentinel */ },
  4602. };
  4603. static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
  4604. unsigned int pin)
  4605. {
  4606. const struct pinmux_bias_reg *reg;
  4607. unsigned int bit;
  4608. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  4609. if (!reg)
  4610. return PIN_CONFIG_BIAS_DISABLE;
  4611. if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
  4612. return PIN_CONFIG_BIAS_DISABLE;
  4613. else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
  4614. return PIN_CONFIG_BIAS_PULL_UP;
  4615. else
  4616. return PIN_CONFIG_BIAS_PULL_DOWN;
  4617. }
  4618. static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  4619. unsigned int bias)
  4620. {
  4621. const struct pinmux_bias_reg *reg;
  4622. u32 enable, updown;
  4623. unsigned int bit;
  4624. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  4625. if (!reg)
  4626. return;
  4627. enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
  4628. if (bias != PIN_CONFIG_BIAS_DISABLE)
  4629. enable |= BIT(bit);
  4630. updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
  4631. if (bias == PIN_CONFIG_BIAS_PULL_UP)
  4632. updown |= BIT(bit);
  4633. sh_pfc_write(pfc, reg->pud, updown);
  4634. sh_pfc_write(pfc, reg->puen, enable);
  4635. }
  4636. static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
  4637. .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
  4638. .get_bias = r8a77990_pinmux_get_bias,
  4639. .set_bias = r8a77990_pinmux_set_bias,
  4640. };
  4641. #ifdef CONFIG_PINCTRL_PFC_R8A774C0
  4642. const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
  4643. .name = "r8a774c0_pfc",
  4644. .ops = &r8a77990_pinmux_ops,
  4645. .unlock_reg = 0xe6060000, /* PMMR */
  4646. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  4647. .pins = pinmux_pins,
  4648. .nr_pins = ARRAY_SIZE(pinmux_pins),
  4649. .groups = pinmux_groups.common,
  4650. .nr_groups = ARRAY_SIZE(pinmux_groups.common),
  4651. .functions = pinmux_functions.common,
  4652. .nr_functions = ARRAY_SIZE(pinmux_functions.common),
  4653. .cfg_regs = pinmux_config_regs,
  4654. .bias_regs = pinmux_bias_regs,
  4655. .ioctrl_regs = pinmux_ioctrl_regs,
  4656. .pinmux_data = pinmux_data,
  4657. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  4658. };
  4659. #endif
  4660. #ifdef CONFIG_PINCTRL_PFC_R8A77990
  4661. const struct sh_pfc_soc_info r8a77990_pinmux_info = {
  4662. .name = "r8a77990_pfc",
  4663. .ops = &r8a77990_pinmux_ops,
  4664. .unlock_reg = 0xe6060000, /* PMMR */
  4665. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  4666. .pins = pinmux_pins,
  4667. .nr_pins = ARRAY_SIZE(pinmux_pins),
  4668. .groups = pinmux_groups.common,
  4669. .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
  4670. ARRAY_SIZE(pinmux_groups.automotive),
  4671. .functions = pinmux_functions.common,
  4672. .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
  4673. ARRAY_SIZE(pinmux_functions.automotive),
  4674. .cfg_regs = pinmux_config_regs,
  4675. .bias_regs = pinmux_bias_regs,
  4676. .ioctrl_regs = pinmux_ioctrl_regs,
  4677. .pinmux_data = pinmux_data,
  4678. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  4679. };
  4680. #endif