pfc-r8a7796.c 204 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
  4. *
  5. * Copyright (C) 2016-2019 Renesas Electronics Corp.
  6. *
  7. * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  8. *
  9. * R-Car Gen3 processor support - PFC hardware block.
  10. *
  11. * Copyright (C) 2015 Renesas Electronics Corporation
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <dm/pinctrl.h>
  17. #include <linux/kernel.h>
  18. #include "sh_pfc.h"
  19. #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  20. #define CPU_ALL_GP(fn, sfx) \
  21. PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
  22. PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
  23. PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
  24. PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  25. PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
  26. PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
  27. PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
  28. PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
  29. PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  30. PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
  31. PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
  32. PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  33. #define CPU_ALL_NOGP(fn) \
  34. PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
  35. PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
  36. PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
  37. PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
  38. PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
  39. PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
  40. PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
  41. PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
  42. PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
  43. PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
  44. PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
  45. PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
  46. PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
  47. PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
  48. PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
  49. PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
  50. PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
  51. PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
  52. PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  53. PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
  54. PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
  55. PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
  56. PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
  57. PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
  58. PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
  59. PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
  60. PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
  61. PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
  62. PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
  63. PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
  64. PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
  65. PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
  66. PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
  67. PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
  68. PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
  69. PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
  70. PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
  71. PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  72. PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  73. PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
  74. PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
  75. PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  76. /*
  77. * F_() : just information
  78. * FM() : macro for FN_xxx / xxx_MARK
  79. */
  80. /* GPSR0 */
  81. #define GPSR0_15 F_(D15, IP7_11_8)
  82. #define GPSR0_14 F_(D14, IP7_7_4)
  83. #define GPSR0_13 F_(D13, IP7_3_0)
  84. #define GPSR0_12 F_(D12, IP6_31_28)
  85. #define GPSR0_11 F_(D11, IP6_27_24)
  86. #define GPSR0_10 F_(D10, IP6_23_20)
  87. #define GPSR0_9 F_(D9, IP6_19_16)
  88. #define GPSR0_8 F_(D8, IP6_15_12)
  89. #define GPSR0_7 F_(D7, IP6_11_8)
  90. #define GPSR0_6 F_(D6, IP6_7_4)
  91. #define GPSR0_5 F_(D5, IP6_3_0)
  92. #define GPSR0_4 F_(D4, IP5_31_28)
  93. #define GPSR0_3 F_(D3, IP5_27_24)
  94. #define GPSR0_2 F_(D2, IP5_23_20)
  95. #define GPSR0_1 F_(D1, IP5_19_16)
  96. #define GPSR0_0 F_(D0, IP5_15_12)
  97. /* GPSR1 */
  98. #define GPSR1_28 FM(CLKOUT)
  99. #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
  100. #define GPSR1_26 F_(WE1_N, IP5_7_4)
  101. #define GPSR1_25 F_(WE0_N, IP5_3_0)
  102. #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
  103. #define GPSR1_23 F_(RD_N, IP4_27_24)
  104. #define GPSR1_22 F_(BS_N, IP4_23_20)
  105. #define GPSR1_21 F_(CS1_N, IP4_19_16)
  106. #define GPSR1_20 F_(CS0_N, IP4_15_12)
  107. #define GPSR1_19 F_(A19, IP4_11_8)
  108. #define GPSR1_18 F_(A18, IP4_7_4)
  109. #define GPSR1_17 F_(A17, IP4_3_0)
  110. #define GPSR1_16 F_(A16, IP3_31_28)
  111. #define GPSR1_15 F_(A15, IP3_27_24)
  112. #define GPSR1_14 F_(A14, IP3_23_20)
  113. #define GPSR1_13 F_(A13, IP3_19_16)
  114. #define GPSR1_12 F_(A12, IP3_15_12)
  115. #define GPSR1_11 F_(A11, IP3_11_8)
  116. #define GPSR1_10 F_(A10, IP3_7_4)
  117. #define GPSR1_9 F_(A9, IP3_3_0)
  118. #define GPSR1_8 F_(A8, IP2_31_28)
  119. #define GPSR1_7 F_(A7, IP2_27_24)
  120. #define GPSR1_6 F_(A6, IP2_23_20)
  121. #define GPSR1_5 F_(A5, IP2_19_16)
  122. #define GPSR1_4 F_(A4, IP2_15_12)
  123. #define GPSR1_3 F_(A3, IP2_11_8)
  124. #define GPSR1_2 F_(A2, IP2_7_4)
  125. #define GPSR1_1 F_(A1, IP2_3_0)
  126. #define GPSR1_0 F_(A0, IP1_31_28)
  127. /* GPSR2 */
  128. #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
  129. #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
  130. #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
  131. #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
  132. #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
  133. #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
  134. #define GPSR2_8 F_(PWM2_A, IP1_27_24)
  135. #define GPSR2_7 F_(PWM1_A, IP1_23_20)
  136. #define GPSR2_6 F_(PWM0, IP1_19_16)
  137. #define GPSR2_5 F_(IRQ5, IP1_15_12)
  138. #define GPSR2_4 F_(IRQ4, IP1_11_8)
  139. #define GPSR2_3 F_(IRQ3, IP1_7_4)
  140. #define GPSR2_2 F_(IRQ2, IP1_3_0)
  141. #define GPSR2_1 F_(IRQ1, IP0_31_28)
  142. #define GPSR2_0 F_(IRQ0, IP0_27_24)
  143. /* GPSR3 */
  144. #define GPSR3_15 F_(SD1_WP, IP11_23_20)
  145. #define GPSR3_14 F_(SD1_CD, IP11_19_16)
  146. #define GPSR3_13 F_(SD0_WP, IP11_15_12)
  147. #define GPSR3_12 F_(SD0_CD, IP11_11_8)
  148. #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
  149. #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
  150. #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
  151. #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
  152. #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
  153. #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
  154. #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
  155. #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
  156. #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
  157. #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
  158. #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
  159. #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
  160. /* GPSR4 */
  161. #define GPSR4_17 F_(SD3_DS, IP11_7_4)
  162. #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
  163. #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
  164. #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
  165. #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
  166. #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
  167. #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
  168. #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
  169. #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
  170. #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
  171. #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
  172. #define GPSR4_6 F_(SD2_DS, IP9_27_24)
  173. #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
  174. #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
  175. #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
  176. #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
  177. #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
  178. #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
  179. /* GPSR5 */
  180. #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
  181. #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
  182. #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
  183. #define GPSR5_22 FM(MSIOF0_RXD)
  184. #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
  185. #define GPSR5_20 FM(MSIOF0_TXD)
  186. #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
  187. #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
  188. #define GPSR5_17 FM(MSIOF0_SCK)
  189. #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
  190. #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
  191. #define GPSR5_14 F_(HTX0, IP13_19_16)
  192. #define GPSR5_13 F_(HRX0, IP13_15_12)
  193. #define GPSR5_12 F_(HSCK0, IP13_11_8)
  194. #define GPSR5_11 F_(RX2_A, IP13_7_4)
  195. #define GPSR5_10 F_(TX2_A, IP13_3_0)
  196. #define GPSR5_9 F_(SCK2, IP12_31_28)
  197. #define GPSR5_8 F_(RTS1_N, IP12_27_24)
  198. #define GPSR5_7 F_(CTS1_N, IP12_23_20)
  199. #define GPSR5_6 F_(TX1_A, IP12_19_16)
  200. #define GPSR5_5 F_(RX1_A, IP12_15_12)
  201. #define GPSR5_4 F_(RTS0_N, IP12_11_8)
  202. #define GPSR5_3 F_(CTS0_N, IP12_7_4)
  203. #define GPSR5_2 F_(TX0, IP12_3_0)
  204. #define GPSR5_1 F_(RX0, IP11_31_28)
  205. #define GPSR5_0 F_(SCK0, IP11_27_24)
  206. /* GPSR6 */
  207. #define GPSR6_31 F_(GP6_31, IP18_7_4)
  208. #define GPSR6_30 F_(GP6_30, IP18_3_0)
  209. #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
  210. #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
  211. #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
  212. #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
  213. #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
  214. #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
  215. #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
  216. #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
  217. #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
  218. #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
  219. #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
  220. #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
  221. #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
  222. #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
  223. #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
  224. #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
  225. #define GPSR6_13 FM(SSI_SDATA5)
  226. #define GPSR6_12 FM(SSI_WS5)
  227. #define GPSR6_11 FM(SSI_SCK5)
  228. #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
  229. #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
  230. #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
  231. #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
  232. #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
  233. #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
  234. #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
  235. #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
  236. #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
  237. #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
  238. #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
  239. /* GPSR7 */
  240. #define GPSR7_3 FM(GP7_03)
  241. #define GPSR7_2 FM(GP7_02)
  242. #define GPSR7_1 FM(AVS2)
  243. #define GPSR7_0 FM(AVS1)
  244. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  245. #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  246. #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  247. #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  248. #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  249. #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  250. #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  251. #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  252. #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  253. #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  254. #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  255. #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  256. #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  257. #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  258. #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  259. #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  260. #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  261. #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  262. #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  263. #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  264. #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  265. #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  266. #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  267. #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  268. #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  269. #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  270. #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  271. #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  272. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  273. #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  274. #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  275. #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  276. #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  277. #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  278. #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  279. #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  280. #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  281. #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  282. #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  283. #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  284. #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  285. #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  286. #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  287. #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  288. #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  289. #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  290. #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  291. #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  292. #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  293. #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  294. #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  295. #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  296. #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  297. #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  298. #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  299. #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  300. #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  301. #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  302. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  303. #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  304. #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  305. #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  306. #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  307. #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  308. #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  309. #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  310. #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  311. #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  312. #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  313. #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  314. #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  315. #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  316. #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  317. #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  318. #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  319. #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  320. #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  321. #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  322. #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  323. #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  324. #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  325. #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  326. #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  327. #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  328. #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  329. #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  330. #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  331. #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  332. #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  333. #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  334. #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  335. #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  336. #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  337. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  338. #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  339. #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  340. #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  341. #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  342. #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  343. #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  344. #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  345. #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  346. #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  347. #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  348. #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  349. #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  350. #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  351. #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  352. #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  353. #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  354. #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  355. #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  356. #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  357. #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  358. #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
  359. #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  360. #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  361. #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  362. #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  363. #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  364. #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  365. #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  366. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  367. #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  368. #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  369. #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  370. #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  371. #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  372. #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  373. #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  374. #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  375. #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  376. #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  377. #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  378. #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  379. #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  380. #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  381. #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  382. #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  383. #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  384. #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  385. #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  386. #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
  387. #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
  388. #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
  389. #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
  390. #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
  391. #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  392. #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
  393. #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
  394. #define PINMUX_GPSR \
  395. \
  396. GPSR6_31 \
  397. GPSR6_30 \
  398. GPSR6_29 \
  399. GPSR1_28 GPSR6_28 \
  400. GPSR1_27 GPSR6_27 \
  401. GPSR1_26 GPSR6_26 \
  402. GPSR1_25 GPSR5_25 GPSR6_25 \
  403. GPSR1_24 GPSR5_24 GPSR6_24 \
  404. GPSR1_23 GPSR5_23 GPSR6_23 \
  405. GPSR1_22 GPSR5_22 GPSR6_22 \
  406. GPSR1_21 GPSR5_21 GPSR6_21 \
  407. GPSR1_20 GPSR5_20 GPSR6_20 \
  408. GPSR1_19 GPSR5_19 GPSR6_19 \
  409. GPSR1_18 GPSR5_18 GPSR6_18 \
  410. GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
  411. GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
  412. GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
  413. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
  414. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
  415. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
  416. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
  417. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
  418. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
  419. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
  420. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
  421. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
  422. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
  423. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
  424. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
  425. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
  426. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
  427. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
  428. #define PINMUX_IPSR \
  429. \
  430. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  431. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  432. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  433. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  434. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  435. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  436. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  437. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  438. \
  439. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  440. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  441. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  442. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
  443. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  444. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  445. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  446. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  447. \
  448. FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
  449. FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
  450. FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
  451. FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
  452. FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
  453. FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
  454. FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
  455. FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
  456. \
  457. FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
  458. FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
  459. FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
  460. FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
  461. FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
  462. FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
  463. FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
  464. FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
  465. \
  466. FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
  467. FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
  468. FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
  469. FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
  470. FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
  471. FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
  472. FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
  473. FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
  474. /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  475. #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
  476. #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
  477. #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
  478. #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
  479. #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
  480. #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
  481. #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
  482. #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
  483. #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
  484. #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
  485. #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
  486. #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
  487. #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
  488. #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
  489. #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
  490. #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
  491. #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
  492. #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
  493. /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  494. #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
  495. #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  496. #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
  497. #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
  498. #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  499. #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
  500. #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
  501. #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
  502. #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
  503. #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
  504. #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
  505. #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
  506. #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
  507. #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
  508. #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
  509. #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
  510. #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
  511. #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
  512. #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  513. #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
  514. #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
  515. #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  516. /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  517. #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
  518. #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
  519. #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
  520. #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
  521. #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
  522. #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  523. #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
  524. #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
  525. #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
  526. #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
  527. #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
  528. #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
  529. #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
  530. #define PINMUX_MOD_SELS \
  531. \
  532. MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
  533. MOD_SEL2_30 \
  534. MOD_SEL1_29_28_27 MOD_SEL2_29 \
  535. MOD_SEL0_28_27 MOD_SEL2_28_27 \
  536. MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
  537. MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
  538. MOD_SEL0_23 MOD_SEL1_23_22_21 \
  539. MOD_SEL0_22 MOD_SEL2_22 \
  540. MOD_SEL0_21 MOD_SEL2_21 \
  541. MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
  542. MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
  543. MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
  544. MOD_SEL2_17 \
  545. MOD_SEL0_16 MOD_SEL1_16 \
  546. MOD_SEL1_15_14 \
  547. MOD_SEL0_14_13 \
  548. MOD_SEL1_13 \
  549. MOD_SEL0_12 MOD_SEL1_12 \
  550. MOD_SEL0_11 MOD_SEL1_11 \
  551. MOD_SEL0_10 MOD_SEL1_10 \
  552. MOD_SEL0_9_8 MOD_SEL1_9 \
  553. MOD_SEL0_7_6 \
  554. MOD_SEL1_6 \
  555. MOD_SEL0_5 MOD_SEL1_5 \
  556. MOD_SEL0_4_3 MOD_SEL1_4 \
  557. MOD_SEL1_3 \
  558. MOD_SEL1_2 \
  559. MOD_SEL1_1 \
  560. MOD_SEL1_0 MOD_SEL2_0
  561. /*
  562. * These pins are not able to be muxed but have other properties
  563. * that can be set, such as drive-strength or pull-up/pull-down enable.
  564. */
  565. #define PINMUX_STATIC \
  566. FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
  567. FM(QSPI0_IO2) FM(QSPI0_IO3) \
  568. FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
  569. FM(QSPI1_IO2) FM(QSPI1_IO3) \
  570. FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
  571. FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
  572. FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
  573. FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
  574. FM(PRESETOUT) \
  575. FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
  576. FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
  577. #define PINMUX_PHYS \
  578. FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
  579. enum {
  580. PINMUX_RESERVED = 0,
  581. PINMUX_DATA_BEGIN,
  582. GP_ALL(DATA),
  583. PINMUX_DATA_END,
  584. #define F_(x, y)
  585. #define FM(x) FN_##x,
  586. PINMUX_FUNCTION_BEGIN,
  587. GP_ALL(FN),
  588. PINMUX_GPSR
  589. PINMUX_IPSR
  590. PINMUX_MOD_SELS
  591. PINMUX_FUNCTION_END,
  592. #undef F_
  593. #undef FM
  594. #define F_(x, y)
  595. #define FM(x) x##_MARK,
  596. PINMUX_MARK_BEGIN,
  597. PINMUX_GPSR
  598. PINMUX_IPSR
  599. PINMUX_MOD_SELS
  600. PINMUX_STATIC
  601. PINMUX_PHYS
  602. PINMUX_MARK_END,
  603. #undef F_
  604. #undef FM
  605. };
  606. static const u16 pinmux_data[] = {
  607. PINMUX_DATA_GP_ALL(),
  608. PINMUX_SINGLE(AVS1),
  609. PINMUX_SINGLE(AVS2),
  610. PINMUX_SINGLE(CLKOUT),
  611. PINMUX_SINGLE(GP7_03),
  612. PINMUX_SINGLE(GP7_02),
  613. PINMUX_SINGLE(MSIOF0_RXD),
  614. PINMUX_SINGLE(MSIOF0_SCK),
  615. PINMUX_SINGLE(MSIOF0_TXD),
  616. PINMUX_SINGLE(SSI_SCK5),
  617. PINMUX_SINGLE(SSI_SDATA5),
  618. PINMUX_SINGLE(SSI_WS5),
  619. /* IPSR0 */
  620. PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
  621. PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
  622. PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
  623. PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
  624. PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
  625. PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
  626. PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
  627. PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
  628. PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
  629. PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
  630. PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
  631. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  632. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  633. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  634. PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
  635. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  636. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  637. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  638. PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
  639. PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
  640. PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
  641. PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
  642. PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
  643. PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
  644. PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
  645. PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
  646. PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
  647. PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
  648. PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
  649. PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
  650. PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
  651. PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
  652. PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
  653. /* IPSR1 */
  654. PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
  655. PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
  656. PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
  657. PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
  658. PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
  659. PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
  660. PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
  661. PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
  662. PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
  663. PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
  664. PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
  665. PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
  666. PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
  667. PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
  668. PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
  669. PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
  670. PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
  671. PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
  672. PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
  673. PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
  674. PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
  675. PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
  676. PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
  677. PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
  678. PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
  679. PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
  680. PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
  681. PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
  682. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
  683. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  684. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
  685. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  686. PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
  687. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
  688. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  689. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  690. PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
  691. PINMUX_IPSR_GPSR(IP1_31_28, A0),
  692. PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
  693. PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
  694. PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
  695. PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
  696. PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
  697. /* IPSR2 */
  698. PINMUX_IPSR_GPSR(IP2_3_0, A1),
  699. PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
  700. PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
  701. PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
  702. PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
  703. PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
  704. PINMUX_IPSR_GPSR(IP2_7_4, A2),
  705. PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
  706. PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
  707. PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
  708. PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
  709. PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
  710. PINMUX_IPSR_GPSR(IP2_11_8, A3),
  711. PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
  712. PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
  713. PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
  714. PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
  715. PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
  716. PINMUX_IPSR_GPSR(IP2_15_12, A4),
  717. PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
  718. PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
  719. PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
  720. PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
  721. PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
  722. PINMUX_IPSR_GPSR(IP2_19_16, A5),
  723. PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
  724. PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
  725. PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
  726. PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
  727. PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
  728. PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
  729. PINMUX_IPSR_GPSR(IP2_23_20, A6),
  730. PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
  731. PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
  732. PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
  733. PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
  734. PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
  735. PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
  736. PINMUX_IPSR_GPSR(IP2_27_24, A7),
  737. PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
  738. PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
  739. PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
  740. PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
  741. PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
  742. PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
  743. PINMUX_IPSR_GPSR(IP2_31_28, A8),
  744. PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
  745. PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
  746. PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
  747. PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
  748. PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
  749. PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
  750. /* IPSR3 */
  751. PINMUX_IPSR_GPSR(IP3_3_0, A9),
  752. PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
  753. PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
  754. PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
  755. PINMUX_IPSR_GPSR(IP3_7_4, A10),
  756. PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
  757. PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
  758. PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
  759. PINMUX_IPSR_GPSR(IP3_11_8, A11),
  760. PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
  761. PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
  762. PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
  763. PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
  764. PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
  765. PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
  766. PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
  767. PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
  768. PINMUX_IPSR_GPSR(IP3_15_12, A12),
  769. PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
  770. PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
  771. PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
  772. PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
  773. PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
  774. PINMUX_IPSR_GPSR(IP3_19_16, A13),
  775. PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
  776. PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
  777. PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
  778. PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
  779. PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
  780. PINMUX_IPSR_GPSR(IP3_23_20, A14),
  781. PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
  782. PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
  783. PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
  784. PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
  785. PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
  786. PINMUX_IPSR_GPSR(IP3_27_24, A15),
  787. PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
  788. PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
  789. PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
  790. PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
  791. PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
  792. PINMUX_IPSR_GPSR(IP3_31_28, A16),
  793. PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
  794. PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
  795. PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
  796. /* IPSR4 */
  797. PINMUX_IPSR_GPSR(IP4_3_0, A17),
  798. PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
  799. PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
  800. PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
  801. PINMUX_IPSR_GPSR(IP4_7_4, A18),
  802. PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
  803. PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
  804. PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
  805. PINMUX_IPSR_GPSR(IP4_11_8, A19),
  806. PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
  807. PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
  808. PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
  809. PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
  810. PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
  811. PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
  812. PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
  813. PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
  814. PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
  815. PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
  816. PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
  817. PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
  818. PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
  819. PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
  820. PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
  821. PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
  822. PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
  823. PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
  824. PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
  825. PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
  826. PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
  827. PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
  828. PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
  829. PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
  830. PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
  831. PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
  832. PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
  833. PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
  834. /* IPSR5 */
  835. PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
  836. PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
  837. PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
  838. PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
  839. PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
  840. PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
  841. PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
  842. PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
  843. PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
  844. PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
  845. PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
  846. PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
  847. PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
  848. PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
  849. PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
  850. PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
  851. PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
  852. PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
  853. PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
  854. PINMUX_IPSR_GPSR(IP5_15_12, D0),
  855. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
  856. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
  857. PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
  858. PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
  859. PINMUX_IPSR_GPSR(IP5_19_16, D1),
  860. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
  861. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
  862. PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
  863. PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
  864. PINMUX_IPSR_GPSR(IP5_23_20, D2),
  865. PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
  866. PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
  867. PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
  868. PINMUX_IPSR_GPSR(IP5_27_24, D3),
  869. PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
  870. PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
  871. PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
  872. PINMUX_IPSR_GPSR(IP5_31_28, D4),
  873. PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
  874. PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
  875. PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
  876. /* IPSR6 */
  877. PINMUX_IPSR_GPSR(IP6_3_0, D5),
  878. PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
  879. PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
  880. PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
  881. PINMUX_IPSR_GPSR(IP6_7_4, D6),
  882. PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
  883. PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
  884. PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
  885. PINMUX_IPSR_GPSR(IP6_11_8, D7),
  886. PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
  887. PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
  888. PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
  889. PINMUX_IPSR_GPSR(IP6_15_12, D8),
  890. PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
  891. PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
  892. PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
  893. PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
  894. PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
  895. PINMUX_IPSR_GPSR(IP6_19_16, D9),
  896. PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
  897. PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
  898. PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
  899. PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
  900. PINMUX_IPSR_GPSR(IP6_23_20, D10),
  901. PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
  902. PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
  903. PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
  904. PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
  905. PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
  906. PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
  907. PINMUX_IPSR_GPSR(IP6_27_24, D11),
  908. PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
  909. PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
  910. PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
  911. PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
  912. PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
  913. PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
  914. PINMUX_IPSR_GPSR(IP6_31_28, D12),
  915. PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
  916. PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
  917. PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
  918. PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
  919. PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
  920. /* IPSR7 */
  921. PINMUX_IPSR_GPSR(IP7_3_0, D13),
  922. PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
  923. PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
  924. PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
  925. PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
  926. PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
  927. PINMUX_IPSR_GPSR(IP7_7_4, D14),
  928. PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
  929. PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
  930. PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
  931. PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
  932. PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
  933. PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
  934. PINMUX_IPSR_GPSR(IP7_11_8, D15),
  935. PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
  936. PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
  937. PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
  938. PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
  939. PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
  940. PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
  941. PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
  942. PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
  943. PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
  944. PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
  945. PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
  946. PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
  947. PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
  948. PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
  949. PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
  950. PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
  951. PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
  952. PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
  953. PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
  954. PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
  955. /* IPSR8 */
  956. PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
  957. PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
  958. PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
  959. PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
  960. PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
  961. PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
  962. PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
  963. PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
  964. PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
  965. PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
  966. PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
  967. PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
  968. PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
  969. PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
  970. PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
  971. PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
  972. PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
  973. PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
  974. PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
  975. PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
  976. PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
  977. PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
  978. PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
  979. PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
  980. PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
  981. PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
  982. PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
  983. PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
  984. PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
  985. PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
  986. PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
  987. PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
  988. PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
  989. PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
  990. PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
  991. PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
  992. PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
  993. PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
  994. PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
  995. PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
  996. /* IPSR9 */
  997. PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
  998. PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
  999. PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
  1000. PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
  1001. PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
  1002. PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
  1003. PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
  1004. PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
  1005. PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
  1006. PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
  1007. PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
  1008. PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
  1009. PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
  1010. PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
  1011. PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
  1012. PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
  1013. /* IPSR10 */
  1014. PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
  1015. PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
  1016. PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
  1017. PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
  1018. PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
  1019. PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
  1020. PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
  1021. PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
  1022. PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
  1023. PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
  1024. PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
  1025. PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
  1026. PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
  1027. PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
  1028. PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
  1029. PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
  1030. PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
  1031. PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
  1032. PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
  1033. /* IPSR11 */
  1034. PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
  1035. PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
  1036. PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
  1037. PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
  1038. PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
  1039. PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
  1040. PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
  1041. PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
  1042. PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
  1043. PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
  1044. PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
  1045. PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
  1046. PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
  1047. PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
  1048. PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1049. PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
  1050. PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
  1051. PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
  1052. PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1053. PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
  1054. PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
  1055. PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
  1056. PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
  1057. PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
  1058. PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
  1059. PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
  1060. PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
  1061. PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
  1062. PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
  1063. PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
  1064. PINMUX_IPSR_GPSR(IP11_31_28, RX0),
  1065. PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
  1066. PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
  1067. PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
  1068. PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
  1069. /* IPSR12 */
  1070. PINMUX_IPSR_GPSR(IP12_3_0, TX0),
  1071. PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
  1072. PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
  1073. PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
  1074. PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
  1075. PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
  1076. PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
  1077. PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
  1078. PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
  1079. PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
  1080. PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
  1081. PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
  1082. PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
  1083. PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
  1084. PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
  1085. PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
  1086. PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
  1087. PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
  1088. PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
  1089. PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
  1090. PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
  1091. PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
  1092. PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
  1093. PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
  1094. PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
  1095. PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
  1096. PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
  1097. PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
  1098. PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
  1099. PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
  1100. PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
  1101. PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
  1102. PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
  1103. PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
  1104. PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
  1105. PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
  1106. PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
  1107. PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
  1108. PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
  1109. PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
  1110. PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
  1111. PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
  1112. PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
  1113. PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
  1114. PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
  1115. PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
  1116. PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
  1117. PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
  1118. PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
  1119. PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
  1120. PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
  1121. PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
  1122. /* IPSR13 */
  1123. PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
  1124. PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
  1125. PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
  1126. PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
  1127. PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
  1128. PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
  1129. PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
  1130. PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
  1131. PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
  1132. PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
  1133. PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
  1134. PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
  1135. PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
  1136. PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
  1137. PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
  1138. PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
  1139. PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
  1140. PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
  1141. PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
  1142. PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
  1143. PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
  1144. PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
  1145. PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
  1146. PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
  1147. PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
  1148. PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
  1149. PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
  1150. PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
  1151. PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
  1152. PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
  1153. PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
  1154. PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
  1155. PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
  1156. PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
  1157. PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
  1158. PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
  1159. PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
  1160. PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
  1161. PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
  1162. PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
  1163. PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
  1164. PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
  1165. PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
  1166. PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
  1167. PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
  1168. PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
  1169. PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
  1170. PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
  1171. PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
  1172. PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
  1173. PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
  1174. /* IPSR14 */
  1175. PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
  1176. PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
  1177. PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
  1178. PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
  1179. PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
  1180. PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
  1181. PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
  1182. PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
  1183. PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
  1184. PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
  1185. PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
  1186. PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
  1187. PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
  1188. PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
  1189. PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
  1190. PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
  1191. PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
  1192. PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
  1193. PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
  1194. PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
  1195. PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
  1196. PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
  1197. PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
  1198. PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
  1199. PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
  1200. PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
  1201. PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
  1202. PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
  1203. PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
  1204. PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
  1205. PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
  1206. PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
  1207. /* IPSR15 */
  1208. PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
  1209. PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
  1210. PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
  1211. PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
  1212. PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
  1213. PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
  1214. PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
  1215. PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
  1216. PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
  1217. PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
  1218. PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
  1219. PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
  1220. PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
  1221. PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
  1222. PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
  1223. PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
  1224. PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
  1225. PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
  1226. PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
  1227. PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
  1228. PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
  1229. PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
  1230. PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
  1231. PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
  1232. PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
  1233. PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
  1234. PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
  1235. PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
  1236. PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
  1237. PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
  1238. PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
  1239. PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
  1240. PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
  1241. PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
  1242. PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
  1243. PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
  1244. PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
  1245. PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
  1246. /* IPSR16 */
  1247. PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
  1248. PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
  1249. PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
  1250. PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
  1251. PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
  1252. PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
  1253. PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
  1254. PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
  1255. PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
  1256. PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
  1257. PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
  1258. PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
  1259. PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
  1260. PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
  1261. PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
  1262. PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
  1263. PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
  1264. PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
  1265. PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
  1266. PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
  1267. PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
  1268. PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
  1269. PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
  1270. PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
  1271. PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
  1272. PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
  1273. PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
  1274. PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
  1275. PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
  1276. PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
  1277. PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
  1278. PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
  1279. PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
  1280. PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
  1281. PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
  1282. PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
  1283. PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
  1284. PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
  1285. PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
  1286. PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
  1287. PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
  1288. PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
  1289. PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
  1290. /* IPSR17 */
  1291. PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
  1292. PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
  1293. PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
  1294. PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
  1295. PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
  1296. PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
  1297. PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
  1298. PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
  1299. PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
  1300. PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
  1301. PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
  1302. PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
  1303. PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
  1304. PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
  1305. PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
  1306. PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
  1307. PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
  1308. PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
  1309. PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
  1310. PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
  1311. PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
  1312. PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
  1313. PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
  1314. PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
  1315. PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
  1316. PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
  1317. PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
  1318. PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
  1319. PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
  1320. PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
  1321. PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
  1322. PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
  1323. PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
  1324. PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
  1325. PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
  1326. PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
  1327. PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
  1328. PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
  1329. PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
  1330. PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
  1331. PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
  1332. PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
  1333. PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
  1334. PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
  1335. PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
  1336. PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
  1337. PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
  1338. PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
  1339. PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
  1340. PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
  1341. PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
  1342. PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
  1343. PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
  1344. PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
  1345. PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
  1346. PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
  1347. PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
  1348. /* IPSR18 */
  1349. PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
  1350. PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
  1351. PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
  1352. PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
  1353. PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
  1354. PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
  1355. PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
  1356. PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
  1357. PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
  1358. PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
  1359. PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
  1360. PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
  1361. PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
  1362. PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
  1363. PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
  1364. PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
  1365. PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
  1366. PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
  1367. /*
  1368. * Static pins can not be muxed between different functions but
  1369. * still need mark entries in the pinmux list. Add each static
  1370. * pin to the list without an associated function. The sh-pfc
  1371. * core will do the right thing and skip trying to mux the pin
  1372. * while still applying configuration to it.
  1373. */
  1374. #define FM(x) PINMUX_DATA(x##_MARK, 0),
  1375. PINMUX_STATIC
  1376. #undef FM
  1377. };
  1378. /*
  1379. * Pins not associated with a GPIO port.
  1380. */
  1381. enum {
  1382. GP_ASSIGN_LAST(),
  1383. NOGP_ALL(),
  1384. };
  1385. static const struct sh_pfc_pin pinmux_pins[] = {
  1386. PINMUX_GPIO_GP_ALL(),
  1387. PINMUX_NOGP_ALL(),
  1388. };
  1389. /* - AUDIO CLOCK ------------------------------------------------------------ */
  1390. static const unsigned int audio_clk_a_a_pins[] = {
  1391. /* CLK A */
  1392. RCAR_GP_PIN(6, 22),
  1393. };
  1394. static const unsigned int audio_clk_a_a_mux[] = {
  1395. AUDIO_CLKA_A_MARK,
  1396. };
  1397. static const unsigned int audio_clk_a_b_pins[] = {
  1398. /* CLK A */
  1399. RCAR_GP_PIN(5, 4),
  1400. };
  1401. static const unsigned int audio_clk_a_b_mux[] = {
  1402. AUDIO_CLKA_B_MARK,
  1403. };
  1404. static const unsigned int audio_clk_a_c_pins[] = {
  1405. /* CLK A */
  1406. RCAR_GP_PIN(5, 19),
  1407. };
  1408. static const unsigned int audio_clk_a_c_mux[] = {
  1409. AUDIO_CLKA_C_MARK,
  1410. };
  1411. static const unsigned int audio_clk_b_a_pins[] = {
  1412. /* CLK B */
  1413. RCAR_GP_PIN(5, 12),
  1414. };
  1415. static const unsigned int audio_clk_b_a_mux[] = {
  1416. AUDIO_CLKB_A_MARK,
  1417. };
  1418. static const unsigned int audio_clk_b_b_pins[] = {
  1419. /* CLK B */
  1420. RCAR_GP_PIN(6, 23),
  1421. };
  1422. static const unsigned int audio_clk_b_b_mux[] = {
  1423. AUDIO_CLKB_B_MARK,
  1424. };
  1425. static const unsigned int audio_clk_c_a_pins[] = {
  1426. /* CLK C */
  1427. RCAR_GP_PIN(5, 21),
  1428. };
  1429. static const unsigned int audio_clk_c_a_mux[] = {
  1430. AUDIO_CLKC_A_MARK,
  1431. };
  1432. static const unsigned int audio_clk_c_b_pins[] = {
  1433. /* CLK C */
  1434. RCAR_GP_PIN(5, 0),
  1435. };
  1436. static const unsigned int audio_clk_c_b_mux[] = {
  1437. AUDIO_CLKC_B_MARK,
  1438. };
  1439. static const unsigned int audio_clkout_a_pins[] = {
  1440. /* CLKOUT */
  1441. RCAR_GP_PIN(5, 18),
  1442. };
  1443. static const unsigned int audio_clkout_a_mux[] = {
  1444. AUDIO_CLKOUT_A_MARK,
  1445. };
  1446. static const unsigned int audio_clkout_b_pins[] = {
  1447. /* CLKOUT */
  1448. RCAR_GP_PIN(6, 28),
  1449. };
  1450. static const unsigned int audio_clkout_b_mux[] = {
  1451. AUDIO_CLKOUT_B_MARK,
  1452. };
  1453. static const unsigned int audio_clkout_c_pins[] = {
  1454. /* CLKOUT */
  1455. RCAR_GP_PIN(5, 3),
  1456. };
  1457. static const unsigned int audio_clkout_c_mux[] = {
  1458. AUDIO_CLKOUT_C_MARK,
  1459. };
  1460. static const unsigned int audio_clkout_d_pins[] = {
  1461. /* CLKOUT */
  1462. RCAR_GP_PIN(5, 21),
  1463. };
  1464. static const unsigned int audio_clkout_d_mux[] = {
  1465. AUDIO_CLKOUT_D_MARK,
  1466. };
  1467. static const unsigned int audio_clkout1_a_pins[] = {
  1468. /* CLKOUT1 */
  1469. RCAR_GP_PIN(5, 15),
  1470. };
  1471. static const unsigned int audio_clkout1_a_mux[] = {
  1472. AUDIO_CLKOUT1_A_MARK,
  1473. };
  1474. static const unsigned int audio_clkout1_b_pins[] = {
  1475. /* CLKOUT1 */
  1476. RCAR_GP_PIN(6, 29),
  1477. };
  1478. static const unsigned int audio_clkout1_b_mux[] = {
  1479. AUDIO_CLKOUT1_B_MARK,
  1480. };
  1481. static const unsigned int audio_clkout2_a_pins[] = {
  1482. /* CLKOUT2 */
  1483. RCAR_GP_PIN(5, 16),
  1484. };
  1485. static const unsigned int audio_clkout2_a_mux[] = {
  1486. AUDIO_CLKOUT2_A_MARK,
  1487. };
  1488. static const unsigned int audio_clkout2_b_pins[] = {
  1489. /* CLKOUT2 */
  1490. RCAR_GP_PIN(6, 30),
  1491. };
  1492. static const unsigned int audio_clkout2_b_mux[] = {
  1493. AUDIO_CLKOUT2_B_MARK,
  1494. };
  1495. static const unsigned int audio_clkout3_a_pins[] = {
  1496. /* CLKOUT3 */
  1497. RCAR_GP_PIN(5, 19),
  1498. };
  1499. static const unsigned int audio_clkout3_a_mux[] = {
  1500. AUDIO_CLKOUT3_A_MARK,
  1501. };
  1502. static const unsigned int audio_clkout3_b_pins[] = {
  1503. /* CLKOUT3 */
  1504. RCAR_GP_PIN(6, 31),
  1505. };
  1506. static const unsigned int audio_clkout3_b_mux[] = {
  1507. AUDIO_CLKOUT3_B_MARK,
  1508. };
  1509. /* - EtherAVB --------------------------------------------------------------- */
  1510. static const unsigned int avb_link_pins[] = {
  1511. /* AVB_LINK */
  1512. RCAR_GP_PIN(2, 12),
  1513. };
  1514. static const unsigned int avb_link_mux[] = {
  1515. AVB_LINK_MARK,
  1516. };
  1517. static const unsigned int avb_magic_pins[] = {
  1518. /* AVB_MAGIC_ */
  1519. RCAR_GP_PIN(2, 10),
  1520. };
  1521. static const unsigned int avb_magic_mux[] = {
  1522. AVB_MAGIC_MARK,
  1523. };
  1524. static const unsigned int avb_phy_int_pins[] = {
  1525. /* AVB_PHY_INT */
  1526. RCAR_GP_PIN(2, 11),
  1527. };
  1528. static const unsigned int avb_phy_int_mux[] = {
  1529. AVB_PHY_INT_MARK,
  1530. };
  1531. static const unsigned int avb_mdio_pins[] = {
  1532. /* AVB_MDC, AVB_MDIO */
  1533. RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
  1534. };
  1535. static const unsigned int avb_mdio_mux[] = {
  1536. AVB_MDC_MARK, AVB_MDIO_MARK,
  1537. };
  1538. static const unsigned int avb_mii_pins[] = {
  1539. /*
  1540. * AVB_TX_CTL, AVB_TXC, AVB_TD0,
  1541. * AVB_TD1, AVB_TD2, AVB_TD3,
  1542. * AVB_RX_CTL, AVB_RXC, AVB_RD0,
  1543. * AVB_RD1, AVB_RD2, AVB_RD3,
  1544. * AVB_TXCREFCLK
  1545. */
  1546. PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
  1547. PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
  1548. PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
  1549. PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
  1550. PIN_AVB_TXCREFCLK,
  1551. };
  1552. static const unsigned int avb_mii_mux[] = {
  1553. AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
  1554. AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
  1555. AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
  1556. AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
  1557. AVB_TXCREFCLK_MARK,
  1558. };
  1559. static const unsigned int avb_avtp_pps_pins[] = {
  1560. /* AVB_AVTP_PPS */
  1561. RCAR_GP_PIN(2, 6),
  1562. };
  1563. static const unsigned int avb_avtp_pps_mux[] = {
  1564. AVB_AVTP_PPS_MARK,
  1565. };
  1566. static const unsigned int avb_avtp_match_a_pins[] = {
  1567. /* AVB_AVTP_MATCH_A */
  1568. RCAR_GP_PIN(2, 13),
  1569. };
  1570. static const unsigned int avb_avtp_match_a_mux[] = {
  1571. AVB_AVTP_MATCH_A_MARK,
  1572. };
  1573. static const unsigned int avb_avtp_capture_a_pins[] = {
  1574. /* AVB_AVTP_CAPTURE_A */
  1575. RCAR_GP_PIN(2, 14),
  1576. };
  1577. static const unsigned int avb_avtp_capture_a_mux[] = {
  1578. AVB_AVTP_CAPTURE_A_MARK,
  1579. };
  1580. static const unsigned int avb_avtp_match_b_pins[] = {
  1581. /* AVB_AVTP_MATCH_B */
  1582. RCAR_GP_PIN(1, 8),
  1583. };
  1584. static const unsigned int avb_avtp_match_b_mux[] = {
  1585. AVB_AVTP_MATCH_B_MARK,
  1586. };
  1587. static const unsigned int avb_avtp_capture_b_pins[] = {
  1588. /* AVB_AVTP_CAPTURE_B */
  1589. RCAR_GP_PIN(1, 11),
  1590. };
  1591. static const unsigned int avb_avtp_capture_b_mux[] = {
  1592. AVB_AVTP_CAPTURE_B_MARK,
  1593. };
  1594. /* - CAN ------------------------------------------------------------------ */
  1595. static const unsigned int can0_data_a_pins[] = {
  1596. /* TX, RX */
  1597. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1598. };
  1599. static const unsigned int can0_data_a_mux[] = {
  1600. CAN0_TX_A_MARK, CAN0_RX_A_MARK,
  1601. };
  1602. static const unsigned int can0_data_b_pins[] = {
  1603. /* TX, RX */
  1604. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1605. };
  1606. static const unsigned int can0_data_b_mux[] = {
  1607. CAN0_TX_B_MARK, CAN0_RX_B_MARK,
  1608. };
  1609. static const unsigned int can1_data_pins[] = {
  1610. /* TX, RX */
  1611. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1612. };
  1613. static const unsigned int can1_data_mux[] = {
  1614. CAN1_TX_MARK, CAN1_RX_MARK,
  1615. };
  1616. /* - CAN Clock -------------------------------------------------------------- */
  1617. static const unsigned int can_clk_pins[] = {
  1618. /* CLK */
  1619. RCAR_GP_PIN(1, 25),
  1620. };
  1621. static const unsigned int can_clk_mux[] = {
  1622. CAN_CLK_MARK,
  1623. };
  1624. /* - CAN FD --------------------------------------------------------------- */
  1625. static const unsigned int canfd0_data_a_pins[] = {
  1626. /* TX, RX */
  1627. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1628. };
  1629. static const unsigned int canfd0_data_a_mux[] = {
  1630. CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
  1631. };
  1632. static const unsigned int canfd0_data_b_pins[] = {
  1633. /* TX, RX */
  1634. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1635. };
  1636. static const unsigned int canfd0_data_b_mux[] = {
  1637. CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
  1638. };
  1639. static const unsigned int canfd1_data_pins[] = {
  1640. /* TX, RX */
  1641. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1642. };
  1643. static const unsigned int canfd1_data_mux[] = {
  1644. CANFD1_TX_MARK, CANFD1_RX_MARK,
  1645. };
  1646. #if defined(CONFIG_PINCTRL_PFC_R8A7796)
  1647. /* - DRIF0 --------------------------------------------------------------- */
  1648. static const unsigned int drif0_ctrl_a_pins[] = {
  1649. /* CLK, SYNC */
  1650. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1651. };
  1652. static const unsigned int drif0_ctrl_a_mux[] = {
  1653. RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
  1654. };
  1655. static const unsigned int drif0_data0_a_pins[] = {
  1656. /* D0 */
  1657. RCAR_GP_PIN(6, 10),
  1658. };
  1659. static const unsigned int drif0_data0_a_mux[] = {
  1660. RIF0_D0_A_MARK,
  1661. };
  1662. static const unsigned int drif0_data1_a_pins[] = {
  1663. /* D1 */
  1664. RCAR_GP_PIN(6, 7),
  1665. };
  1666. static const unsigned int drif0_data1_a_mux[] = {
  1667. RIF0_D1_A_MARK,
  1668. };
  1669. static const unsigned int drif0_ctrl_b_pins[] = {
  1670. /* CLK, SYNC */
  1671. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  1672. };
  1673. static const unsigned int drif0_ctrl_b_mux[] = {
  1674. RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
  1675. };
  1676. static const unsigned int drif0_data0_b_pins[] = {
  1677. /* D0 */
  1678. RCAR_GP_PIN(5, 1),
  1679. };
  1680. static const unsigned int drif0_data0_b_mux[] = {
  1681. RIF0_D0_B_MARK,
  1682. };
  1683. static const unsigned int drif0_data1_b_pins[] = {
  1684. /* D1 */
  1685. RCAR_GP_PIN(5, 2),
  1686. };
  1687. static const unsigned int drif0_data1_b_mux[] = {
  1688. RIF0_D1_B_MARK,
  1689. };
  1690. static const unsigned int drif0_ctrl_c_pins[] = {
  1691. /* CLK, SYNC */
  1692. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
  1693. };
  1694. static const unsigned int drif0_ctrl_c_mux[] = {
  1695. RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
  1696. };
  1697. static const unsigned int drif0_data0_c_pins[] = {
  1698. /* D0 */
  1699. RCAR_GP_PIN(5, 13),
  1700. };
  1701. static const unsigned int drif0_data0_c_mux[] = {
  1702. RIF0_D0_C_MARK,
  1703. };
  1704. static const unsigned int drif0_data1_c_pins[] = {
  1705. /* D1 */
  1706. RCAR_GP_PIN(5, 14),
  1707. };
  1708. static const unsigned int drif0_data1_c_mux[] = {
  1709. RIF0_D1_C_MARK,
  1710. };
  1711. /* - DRIF1 --------------------------------------------------------------- */
  1712. static const unsigned int drif1_ctrl_a_pins[] = {
  1713. /* CLK, SYNC */
  1714. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1715. };
  1716. static const unsigned int drif1_ctrl_a_mux[] = {
  1717. RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
  1718. };
  1719. static const unsigned int drif1_data0_a_pins[] = {
  1720. /* D0 */
  1721. RCAR_GP_PIN(6, 19),
  1722. };
  1723. static const unsigned int drif1_data0_a_mux[] = {
  1724. RIF1_D0_A_MARK,
  1725. };
  1726. static const unsigned int drif1_data1_a_pins[] = {
  1727. /* D1 */
  1728. RCAR_GP_PIN(6, 20),
  1729. };
  1730. static const unsigned int drif1_data1_a_mux[] = {
  1731. RIF1_D1_A_MARK,
  1732. };
  1733. static const unsigned int drif1_ctrl_b_pins[] = {
  1734. /* CLK, SYNC */
  1735. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
  1736. };
  1737. static const unsigned int drif1_ctrl_b_mux[] = {
  1738. RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
  1739. };
  1740. static const unsigned int drif1_data0_b_pins[] = {
  1741. /* D0 */
  1742. RCAR_GP_PIN(5, 7),
  1743. };
  1744. static const unsigned int drif1_data0_b_mux[] = {
  1745. RIF1_D0_B_MARK,
  1746. };
  1747. static const unsigned int drif1_data1_b_pins[] = {
  1748. /* D1 */
  1749. RCAR_GP_PIN(5, 8),
  1750. };
  1751. static const unsigned int drif1_data1_b_mux[] = {
  1752. RIF1_D1_B_MARK,
  1753. };
  1754. static const unsigned int drif1_ctrl_c_pins[] = {
  1755. /* CLK, SYNC */
  1756. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
  1757. };
  1758. static const unsigned int drif1_ctrl_c_mux[] = {
  1759. RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
  1760. };
  1761. static const unsigned int drif1_data0_c_pins[] = {
  1762. /* D0 */
  1763. RCAR_GP_PIN(5, 6),
  1764. };
  1765. static const unsigned int drif1_data0_c_mux[] = {
  1766. RIF1_D0_C_MARK,
  1767. };
  1768. static const unsigned int drif1_data1_c_pins[] = {
  1769. /* D1 */
  1770. RCAR_GP_PIN(5, 10),
  1771. };
  1772. static const unsigned int drif1_data1_c_mux[] = {
  1773. RIF1_D1_C_MARK,
  1774. };
  1775. /* - DRIF2 --------------------------------------------------------------- */
  1776. static const unsigned int drif2_ctrl_a_pins[] = {
  1777. /* CLK, SYNC */
  1778. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1779. };
  1780. static const unsigned int drif2_ctrl_a_mux[] = {
  1781. RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
  1782. };
  1783. static const unsigned int drif2_data0_a_pins[] = {
  1784. /* D0 */
  1785. RCAR_GP_PIN(6, 7),
  1786. };
  1787. static const unsigned int drif2_data0_a_mux[] = {
  1788. RIF2_D0_A_MARK,
  1789. };
  1790. static const unsigned int drif2_data1_a_pins[] = {
  1791. /* D1 */
  1792. RCAR_GP_PIN(6, 10),
  1793. };
  1794. static const unsigned int drif2_data1_a_mux[] = {
  1795. RIF2_D1_A_MARK,
  1796. };
  1797. static const unsigned int drif2_ctrl_b_pins[] = {
  1798. /* CLK, SYNC */
  1799. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  1800. };
  1801. static const unsigned int drif2_ctrl_b_mux[] = {
  1802. RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
  1803. };
  1804. static const unsigned int drif2_data0_b_pins[] = {
  1805. /* D0 */
  1806. RCAR_GP_PIN(6, 30),
  1807. };
  1808. static const unsigned int drif2_data0_b_mux[] = {
  1809. RIF2_D0_B_MARK,
  1810. };
  1811. static const unsigned int drif2_data1_b_pins[] = {
  1812. /* D1 */
  1813. RCAR_GP_PIN(6, 31),
  1814. };
  1815. static const unsigned int drif2_data1_b_mux[] = {
  1816. RIF2_D1_B_MARK,
  1817. };
  1818. /* - DRIF3 --------------------------------------------------------------- */
  1819. static const unsigned int drif3_ctrl_a_pins[] = {
  1820. /* CLK, SYNC */
  1821. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1822. };
  1823. static const unsigned int drif3_ctrl_a_mux[] = {
  1824. RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
  1825. };
  1826. static const unsigned int drif3_data0_a_pins[] = {
  1827. /* D0 */
  1828. RCAR_GP_PIN(6, 19),
  1829. };
  1830. static const unsigned int drif3_data0_a_mux[] = {
  1831. RIF3_D0_A_MARK,
  1832. };
  1833. static const unsigned int drif3_data1_a_pins[] = {
  1834. /* D1 */
  1835. RCAR_GP_PIN(6, 20),
  1836. };
  1837. static const unsigned int drif3_data1_a_mux[] = {
  1838. RIF3_D1_A_MARK,
  1839. };
  1840. static const unsigned int drif3_ctrl_b_pins[] = {
  1841. /* CLK, SYNC */
  1842. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  1843. };
  1844. static const unsigned int drif3_ctrl_b_mux[] = {
  1845. RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
  1846. };
  1847. static const unsigned int drif3_data0_b_pins[] = {
  1848. /* D0 */
  1849. RCAR_GP_PIN(6, 28),
  1850. };
  1851. static const unsigned int drif3_data0_b_mux[] = {
  1852. RIF3_D0_B_MARK,
  1853. };
  1854. static const unsigned int drif3_data1_b_pins[] = {
  1855. /* D1 */
  1856. RCAR_GP_PIN(6, 29),
  1857. };
  1858. static const unsigned int drif3_data1_b_mux[] = {
  1859. RIF3_D1_B_MARK,
  1860. };
  1861. #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
  1862. /* - DU --------------------------------------------------------------------- */
  1863. static const unsigned int du_rgb666_pins[] = {
  1864. /* R[7:2], G[7:2], B[7:2] */
  1865. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1866. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1867. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1868. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1869. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1870. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1871. };
  1872. static const unsigned int du_rgb666_mux[] = {
  1873. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1874. DU_DR3_MARK, DU_DR2_MARK,
  1875. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1876. DU_DG3_MARK, DU_DG2_MARK,
  1877. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1878. DU_DB3_MARK, DU_DB2_MARK,
  1879. };
  1880. static const unsigned int du_rgb888_pins[] = {
  1881. /* R[7:0], G[7:0], B[7:0] */
  1882. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1883. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1884. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
  1885. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1886. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1887. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  1888. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1889. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1890. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
  1891. };
  1892. static const unsigned int du_rgb888_mux[] = {
  1893. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1894. DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
  1895. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1896. DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
  1897. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1898. DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
  1899. };
  1900. static const unsigned int du_clk_out_0_pins[] = {
  1901. /* CLKOUT */
  1902. RCAR_GP_PIN(1, 27),
  1903. };
  1904. static const unsigned int du_clk_out_0_mux[] = {
  1905. DU_DOTCLKOUT0_MARK
  1906. };
  1907. static const unsigned int du_clk_out_1_pins[] = {
  1908. /* CLKOUT */
  1909. RCAR_GP_PIN(2, 3),
  1910. };
  1911. static const unsigned int du_clk_out_1_mux[] = {
  1912. DU_DOTCLKOUT1_MARK
  1913. };
  1914. static const unsigned int du_sync_pins[] = {
  1915. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1916. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
  1917. };
  1918. static const unsigned int du_sync_mux[] = {
  1919. DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
  1920. };
  1921. static const unsigned int du_oddf_pins[] = {
  1922. /* EXDISP/EXODDF/EXCDE */
  1923. RCAR_GP_PIN(2, 2),
  1924. };
  1925. static const unsigned int du_oddf_mux[] = {
  1926. DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
  1927. };
  1928. static const unsigned int du_cde_pins[] = {
  1929. /* CDE */
  1930. RCAR_GP_PIN(2, 0),
  1931. };
  1932. static const unsigned int du_cde_mux[] = {
  1933. DU_CDE_MARK,
  1934. };
  1935. static const unsigned int du_disp_pins[] = {
  1936. /* DISP */
  1937. RCAR_GP_PIN(2, 1),
  1938. };
  1939. static const unsigned int du_disp_mux[] = {
  1940. DU_DISP_MARK,
  1941. };
  1942. /* - HSCIF0 ----------------------------------------------------------------- */
  1943. static const unsigned int hscif0_data_pins[] = {
  1944. /* RX, TX */
  1945. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1946. };
  1947. static const unsigned int hscif0_data_mux[] = {
  1948. HRX0_MARK, HTX0_MARK,
  1949. };
  1950. static const unsigned int hscif0_clk_pins[] = {
  1951. /* SCK */
  1952. RCAR_GP_PIN(5, 12),
  1953. };
  1954. static const unsigned int hscif0_clk_mux[] = {
  1955. HSCK0_MARK,
  1956. };
  1957. static const unsigned int hscif0_ctrl_pins[] = {
  1958. /* RTS, CTS */
  1959. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
  1960. };
  1961. static const unsigned int hscif0_ctrl_mux[] = {
  1962. HRTS0_N_MARK, HCTS0_N_MARK,
  1963. };
  1964. /* - HSCIF1 ----------------------------------------------------------------- */
  1965. static const unsigned int hscif1_data_a_pins[] = {
  1966. /* RX, TX */
  1967. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  1968. };
  1969. static const unsigned int hscif1_data_a_mux[] = {
  1970. HRX1_A_MARK, HTX1_A_MARK,
  1971. };
  1972. static const unsigned int hscif1_clk_a_pins[] = {
  1973. /* SCK */
  1974. RCAR_GP_PIN(6, 21),
  1975. };
  1976. static const unsigned int hscif1_clk_a_mux[] = {
  1977. HSCK1_A_MARK,
  1978. };
  1979. static const unsigned int hscif1_ctrl_a_pins[] = {
  1980. /* RTS, CTS */
  1981. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  1982. };
  1983. static const unsigned int hscif1_ctrl_a_mux[] = {
  1984. HRTS1_N_A_MARK, HCTS1_N_A_MARK,
  1985. };
  1986. static const unsigned int hscif1_data_b_pins[] = {
  1987. /* RX, TX */
  1988. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1989. };
  1990. static const unsigned int hscif1_data_b_mux[] = {
  1991. HRX1_B_MARK, HTX1_B_MARK,
  1992. };
  1993. static const unsigned int hscif1_clk_b_pins[] = {
  1994. /* SCK */
  1995. RCAR_GP_PIN(5, 0),
  1996. };
  1997. static const unsigned int hscif1_clk_b_mux[] = {
  1998. HSCK1_B_MARK,
  1999. };
  2000. static const unsigned int hscif1_ctrl_b_pins[] = {
  2001. /* RTS, CTS */
  2002. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  2003. };
  2004. static const unsigned int hscif1_ctrl_b_mux[] = {
  2005. HRTS1_N_B_MARK, HCTS1_N_B_MARK,
  2006. };
  2007. /* - HSCIF2 ----------------------------------------------------------------- */
  2008. static const unsigned int hscif2_data_a_pins[] = {
  2009. /* RX, TX */
  2010. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  2011. };
  2012. static const unsigned int hscif2_data_a_mux[] = {
  2013. HRX2_A_MARK, HTX2_A_MARK,
  2014. };
  2015. static const unsigned int hscif2_clk_a_pins[] = {
  2016. /* SCK */
  2017. RCAR_GP_PIN(6, 10),
  2018. };
  2019. static const unsigned int hscif2_clk_a_mux[] = {
  2020. HSCK2_A_MARK,
  2021. };
  2022. static const unsigned int hscif2_ctrl_a_pins[] = {
  2023. /* RTS, CTS */
  2024. RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
  2025. };
  2026. static const unsigned int hscif2_ctrl_a_mux[] = {
  2027. HRTS2_N_A_MARK, HCTS2_N_A_MARK,
  2028. };
  2029. static const unsigned int hscif2_data_b_pins[] = {
  2030. /* RX, TX */
  2031. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  2032. };
  2033. static const unsigned int hscif2_data_b_mux[] = {
  2034. HRX2_B_MARK, HTX2_B_MARK,
  2035. };
  2036. static const unsigned int hscif2_clk_b_pins[] = {
  2037. /* SCK */
  2038. RCAR_GP_PIN(6, 21),
  2039. };
  2040. static const unsigned int hscif2_clk_b_mux[] = {
  2041. HSCK2_B_MARK,
  2042. };
  2043. static const unsigned int hscif2_ctrl_b_pins[] = {
  2044. /* RTS, CTS */
  2045. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
  2046. };
  2047. static const unsigned int hscif2_ctrl_b_mux[] = {
  2048. HRTS2_N_B_MARK, HCTS2_N_B_MARK,
  2049. };
  2050. static const unsigned int hscif2_data_c_pins[] = {
  2051. /* RX, TX */
  2052. RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
  2053. };
  2054. static const unsigned int hscif2_data_c_mux[] = {
  2055. HRX2_C_MARK, HTX2_C_MARK,
  2056. };
  2057. static const unsigned int hscif2_clk_c_pins[] = {
  2058. /* SCK */
  2059. RCAR_GP_PIN(6, 24),
  2060. };
  2061. static const unsigned int hscif2_clk_c_mux[] = {
  2062. HSCK2_C_MARK,
  2063. };
  2064. static const unsigned int hscif2_ctrl_c_pins[] = {
  2065. /* RTS, CTS */
  2066. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
  2067. };
  2068. static const unsigned int hscif2_ctrl_c_mux[] = {
  2069. HRTS2_N_C_MARK, HCTS2_N_C_MARK,
  2070. };
  2071. /* - HSCIF3 ----------------------------------------------------------------- */
  2072. static const unsigned int hscif3_data_a_pins[] = {
  2073. /* RX, TX */
  2074. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  2075. };
  2076. static const unsigned int hscif3_data_a_mux[] = {
  2077. HRX3_A_MARK, HTX3_A_MARK,
  2078. };
  2079. static const unsigned int hscif3_clk_pins[] = {
  2080. /* SCK */
  2081. RCAR_GP_PIN(1, 22),
  2082. };
  2083. static const unsigned int hscif3_clk_mux[] = {
  2084. HSCK3_MARK,
  2085. };
  2086. static const unsigned int hscif3_ctrl_pins[] = {
  2087. /* RTS, CTS */
  2088. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2089. };
  2090. static const unsigned int hscif3_ctrl_mux[] = {
  2091. HRTS3_N_MARK, HCTS3_N_MARK,
  2092. };
  2093. static const unsigned int hscif3_data_b_pins[] = {
  2094. /* RX, TX */
  2095. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  2096. };
  2097. static const unsigned int hscif3_data_b_mux[] = {
  2098. HRX3_B_MARK, HTX3_B_MARK,
  2099. };
  2100. static const unsigned int hscif3_data_c_pins[] = {
  2101. /* RX, TX */
  2102. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2103. };
  2104. static const unsigned int hscif3_data_c_mux[] = {
  2105. HRX3_C_MARK, HTX3_C_MARK,
  2106. };
  2107. static const unsigned int hscif3_data_d_pins[] = {
  2108. /* RX, TX */
  2109. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2110. };
  2111. static const unsigned int hscif3_data_d_mux[] = {
  2112. HRX3_D_MARK, HTX3_D_MARK,
  2113. };
  2114. /* - HSCIF4 ----------------------------------------------------------------- */
  2115. static const unsigned int hscif4_data_a_pins[] = {
  2116. /* RX, TX */
  2117. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  2118. };
  2119. static const unsigned int hscif4_data_a_mux[] = {
  2120. HRX4_A_MARK, HTX4_A_MARK,
  2121. };
  2122. static const unsigned int hscif4_clk_pins[] = {
  2123. /* SCK */
  2124. RCAR_GP_PIN(1, 11),
  2125. };
  2126. static const unsigned int hscif4_clk_mux[] = {
  2127. HSCK4_MARK,
  2128. };
  2129. static const unsigned int hscif4_ctrl_pins[] = {
  2130. /* RTS, CTS */
  2131. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
  2132. };
  2133. static const unsigned int hscif4_ctrl_mux[] = {
  2134. HRTS4_N_MARK, HCTS4_N_MARK,
  2135. };
  2136. static const unsigned int hscif4_data_b_pins[] = {
  2137. /* RX, TX */
  2138. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2139. };
  2140. static const unsigned int hscif4_data_b_mux[] = {
  2141. HRX4_B_MARK, HTX4_B_MARK,
  2142. };
  2143. /* - I2C -------------------------------------------------------------------- */
  2144. static const unsigned int i2c0_pins[] = {
  2145. /* SCL, SDA */
  2146. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2147. };
  2148. static const unsigned int i2c0_mux[] = {
  2149. SCL0_MARK, SDA0_MARK,
  2150. };
  2151. static const unsigned int i2c1_a_pins[] = {
  2152. /* SDA, SCL */
  2153. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  2154. };
  2155. static const unsigned int i2c1_a_mux[] = {
  2156. SDA1_A_MARK, SCL1_A_MARK,
  2157. };
  2158. static const unsigned int i2c1_b_pins[] = {
  2159. /* SDA, SCL */
  2160. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
  2161. };
  2162. static const unsigned int i2c1_b_mux[] = {
  2163. SDA1_B_MARK, SCL1_B_MARK,
  2164. };
  2165. static const unsigned int i2c2_a_pins[] = {
  2166. /* SDA, SCL */
  2167. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  2168. };
  2169. static const unsigned int i2c2_a_mux[] = {
  2170. SDA2_A_MARK, SCL2_A_MARK,
  2171. };
  2172. static const unsigned int i2c2_b_pins[] = {
  2173. /* SDA, SCL */
  2174. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
  2175. };
  2176. static const unsigned int i2c2_b_mux[] = {
  2177. SDA2_B_MARK, SCL2_B_MARK,
  2178. };
  2179. static const unsigned int i2c3_pins[] = {
  2180. /* SCL, SDA */
  2181. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2182. };
  2183. static const unsigned int i2c3_mux[] = {
  2184. SCL3_MARK, SDA3_MARK,
  2185. };
  2186. static const unsigned int i2c5_pins[] = {
  2187. /* SCL, SDA */
  2188. RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
  2189. };
  2190. static const unsigned int i2c5_mux[] = {
  2191. SCL5_MARK, SDA5_MARK,
  2192. };
  2193. static const unsigned int i2c6_a_pins[] = {
  2194. /* SDA, SCL */
  2195. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2196. };
  2197. static const unsigned int i2c6_a_mux[] = {
  2198. SDA6_A_MARK, SCL6_A_MARK,
  2199. };
  2200. static const unsigned int i2c6_b_pins[] = {
  2201. /* SDA, SCL */
  2202. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2203. };
  2204. static const unsigned int i2c6_b_mux[] = {
  2205. SDA6_B_MARK, SCL6_B_MARK,
  2206. };
  2207. static const unsigned int i2c6_c_pins[] = {
  2208. /* SDA, SCL */
  2209. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
  2210. };
  2211. static const unsigned int i2c6_c_mux[] = {
  2212. SDA6_C_MARK, SCL6_C_MARK,
  2213. };
  2214. /* - INTC-EX ---------------------------------------------------------------- */
  2215. static const unsigned int intc_ex_irq0_pins[] = {
  2216. /* IRQ0 */
  2217. RCAR_GP_PIN(2, 0),
  2218. };
  2219. static const unsigned int intc_ex_irq0_mux[] = {
  2220. IRQ0_MARK,
  2221. };
  2222. static const unsigned int intc_ex_irq1_pins[] = {
  2223. /* IRQ1 */
  2224. RCAR_GP_PIN(2, 1),
  2225. };
  2226. static const unsigned int intc_ex_irq1_mux[] = {
  2227. IRQ1_MARK,
  2228. };
  2229. static const unsigned int intc_ex_irq2_pins[] = {
  2230. /* IRQ2 */
  2231. RCAR_GP_PIN(2, 2),
  2232. };
  2233. static const unsigned int intc_ex_irq2_mux[] = {
  2234. IRQ2_MARK,
  2235. };
  2236. static const unsigned int intc_ex_irq3_pins[] = {
  2237. /* IRQ3 */
  2238. RCAR_GP_PIN(2, 3),
  2239. };
  2240. static const unsigned int intc_ex_irq3_mux[] = {
  2241. IRQ3_MARK,
  2242. };
  2243. static const unsigned int intc_ex_irq4_pins[] = {
  2244. /* IRQ4 */
  2245. RCAR_GP_PIN(2, 4),
  2246. };
  2247. static const unsigned int intc_ex_irq4_mux[] = {
  2248. IRQ4_MARK,
  2249. };
  2250. static const unsigned int intc_ex_irq5_pins[] = {
  2251. /* IRQ5 */
  2252. RCAR_GP_PIN(2, 5),
  2253. };
  2254. static const unsigned int intc_ex_irq5_mux[] = {
  2255. IRQ5_MARK,
  2256. };
  2257. /* - MSIOF0 ----------------------------------------------------------------- */
  2258. static const unsigned int msiof0_clk_pins[] = {
  2259. /* SCK */
  2260. RCAR_GP_PIN(5, 17),
  2261. };
  2262. static const unsigned int msiof0_clk_mux[] = {
  2263. MSIOF0_SCK_MARK,
  2264. };
  2265. static const unsigned int msiof0_sync_pins[] = {
  2266. /* SYNC */
  2267. RCAR_GP_PIN(5, 18),
  2268. };
  2269. static const unsigned int msiof0_sync_mux[] = {
  2270. MSIOF0_SYNC_MARK,
  2271. };
  2272. static const unsigned int msiof0_ss1_pins[] = {
  2273. /* SS1 */
  2274. RCAR_GP_PIN(5, 19),
  2275. };
  2276. static const unsigned int msiof0_ss1_mux[] = {
  2277. MSIOF0_SS1_MARK,
  2278. };
  2279. static const unsigned int msiof0_ss2_pins[] = {
  2280. /* SS2 */
  2281. RCAR_GP_PIN(5, 21),
  2282. };
  2283. static const unsigned int msiof0_ss2_mux[] = {
  2284. MSIOF0_SS2_MARK,
  2285. };
  2286. static const unsigned int msiof0_txd_pins[] = {
  2287. /* TXD */
  2288. RCAR_GP_PIN(5, 20),
  2289. };
  2290. static const unsigned int msiof0_txd_mux[] = {
  2291. MSIOF0_TXD_MARK,
  2292. };
  2293. static const unsigned int msiof0_rxd_pins[] = {
  2294. /* RXD */
  2295. RCAR_GP_PIN(5, 22),
  2296. };
  2297. static const unsigned int msiof0_rxd_mux[] = {
  2298. MSIOF0_RXD_MARK,
  2299. };
  2300. /* - MSIOF1 ----------------------------------------------------------------- */
  2301. static const unsigned int msiof1_clk_a_pins[] = {
  2302. /* SCK */
  2303. RCAR_GP_PIN(6, 8),
  2304. };
  2305. static const unsigned int msiof1_clk_a_mux[] = {
  2306. MSIOF1_SCK_A_MARK,
  2307. };
  2308. static const unsigned int msiof1_sync_a_pins[] = {
  2309. /* SYNC */
  2310. RCAR_GP_PIN(6, 9),
  2311. };
  2312. static const unsigned int msiof1_sync_a_mux[] = {
  2313. MSIOF1_SYNC_A_MARK,
  2314. };
  2315. static const unsigned int msiof1_ss1_a_pins[] = {
  2316. /* SS1 */
  2317. RCAR_GP_PIN(6, 5),
  2318. };
  2319. static const unsigned int msiof1_ss1_a_mux[] = {
  2320. MSIOF1_SS1_A_MARK,
  2321. };
  2322. static const unsigned int msiof1_ss2_a_pins[] = {
  2323. /* SS2 */
  2324. RCAR_GP_PIN(6, 6),
  2325. };
  2326. static const unsigned int msiof1_ss2_a_mux[] = {
  2327. MSIOF1_SS2_A_MARK,
  2328. };
  2329. static const unsigned int msiof1_txd_a_pins[] = {
  2330. /* TXD */
  2331. RCAR_GP_PIN(6, 7),
  2332. };
  2333. static const unsigned int msiof1_txd_a_mux[] = {
  2334. MSIOF1_TXD_A_MARK,
  2335. };
  2336. static const unsigned int msiof1_rxd_a_pins[] = {
  2337. /* RXD */
  2338. RCAR_GP_PIN(6, 10),
  2339. };
  2340. static const unsigned int msiof1_rxd_a_mux[] = {
  2341. MSIOF1_RXD_A_MARK,
  2342. };
  2343. static const unsigned int msiof1_clk_b_pins[] = {
  2344. /* SCK */
  2345. RCAR_GP_PIN(5, 9),
  2346. };
  2347. static const unsigned int msiof1_clk_b_mux[] = {
  2348. MSIOF1_SCK_B_MARK,
  2349. };
  2350. static const unsigned int msiof1_sync_b_pins[] = {
  2351. /* SYNC */
  2352. RCAR_GP_PIN(5, 3),
  2353. };
  2354. static const unsigned int msiof1_sync_b_mux[] = {
  2355. MSIOF1_SYNC_B_MARK,
  2356. };
  2357. static const unsigned int msiof1_ss1_b_pins[] = {
  2358. /* SS1 */
  2359. RCAR_GP_PIN(5, 4),
  2360. };
  2361. static const unsigned int msiof1_ss1_b_mux[] = {
  2362. MSIOF1_SS1_B_MARK,
  2363. };
  2364. static const unsigned int msiof1_ss2_b_pins[] = {
  2365. /* SS2 */
  2366. RCAR_GP_PIN(5, 0),
  2367. };
  2368. static const unsigned int msiof1_ss2_b_mux[] = {
  2369. MSIOF1_SS2_B_MARK,
  2370. };
  2371. static const unsigned int msiof1_txd_b_pins[] = {
  2372. /* TXD */
  2373. RCAR_GP_PIN(5, 8),
  2374. };
  2375. static const unsigned int msiof1_txd_b_mux[] = {
  2376. MSIOF1_TXD_B_MARK,
  2377. };
  2378. static const unsigned int msiof1_rxd_b_pins[] = {
  2379. /* RXD */
  2380. RCAR_GP_PIN(5, 7),
  2381. };
  2382. static const unsigned int msiof1_rxd_b_mux[] = {
  2383. MSIOF1_RXD_B_MARK,
  2384. };
  2385. static const unsigned int msiof1_clk_c_pins[] = {
  2386. /* SCK */
  2387. RCAR_GP_PIN(6, 17),
  2388. };
  2389. static const unsigned int msiof1_clk_c_mux[] = {
  2390. MSIOF1_SCK_C_MARK,
  2391. };
  2392. static const unsigned int msiof1_sync_c_pins[] = {
  2393. /* SYNC */
  2394. RCAR_GP_PIN(6, 18),
  2395. };
  2396. static const unsigned int msiof1_sync_c_mux[] = {
  2397. MSIOF1_SYNC_C_MARK,
  2398. };
  2399. static const unsigned int msiof1_ss1_c_pins[] = {
  2400. /* SS1 */
  2401. RCAR_GP_PIN(6, 21),
  2402. };
  2403. static const unsigned int msiof1_ss1_c_mux[] = {
  2404. MSIOF1_SS1_C_MARK,
  2405. };
  2406. static const unsigned int msiof1_ss2_c_pins[] = {
  2407. /* SS2 */
  2408. RCAR_GP_PIN(6, 27),
  2409. };
  2410. static const unsigned int msiof1_ss2_c_mux[] = {
  2411. MSIOF1_SS2_C_MARK,
  2412. };
  2413. static const unsigned int msiof1_txd_c_pins[] = {
  2414. /* TXD */
  2415. RCAR_GP_PIN(6, 20),
  2416. };
  2417. static const unsigned int msiof1_txd_c_mux[] = {
  2418. MSIOF1_TXD_C_MARK,
  2419. };
  2420. static const unsigned int msiof1_rxd_c_pins[] = {
  2421. /* RXD */
  2422. RCAR_GP_PIN(6, 19),
  2423. };
  2424. static const unsigned int msiof1_rxd_c_mux[] = {
  2425. MSIOF1_RXD_C_MARK,
  2426. };
  2427. static const unsigned int msiof1_clk_d_pins[] = {
  2428. /* SCK */
  2429. RCAR_GP_PIN(5, 12),
  2430. };
  2431. static const unsigned int msiof1_clk_d_mux[] = {
  2432. MSIOF1_SCK_D_MARK,
  2433. };
  2434. static const unsigned int msiof1_sync_d_pins[] = {
  2435. /* SYNC */
  2436. RCAR_GP_PIN(5, 15),
  2437. };
  2438. static const unsigned int msiof1_sync_d_mux[] = {
  2439. MSIOF1_SYNC_D_MARK,
  2440. };
  2441. static const unsigned int msiof1_ss1_d_pins[] = {
  2442. /* SS1 */
  2443. RCAR_GP_PIN(5, 16),
  2444. };
  2445. static const unsigned int msiof1_ss1_d_mux[] = {
  2446. MSIOF1_SS1_D_MARK,
  2447. };
  2448. static const unsigned int msiof1_ss2_d_pins[] = {
  2449. /* SS2 */
  2450. RCAR_GP_PIN(5, 21),
  2451. };
  2452. static const unsigned int msiof1_ss2_d_mux[] = {
  2453. MSIOF1_SS2_D_MARK,
  2454. };
  2455. static const unsigned int msiof1_txd_d_pins[] = {
  2456. /* TXD */
  2457. RCAR_GP_PIN(5, 14),
  2458. };
  2459. static const unsigned int msiof1_txd_d_mux[] = {
  2460. MSIOF1_TXD_D_MARK,
  2461. };
  2462. static const unsigned int msiof1_rxd_d_pins[] = {
  2463. /* RXD */
  2464. RCAR_GP_PIN(5, 13),
  2465. };
  2466. static const unsigned int msiof1_rxd_d_mux[] = {
  2467. MSIOF1_RXD_D_MARK,
  2468. };
  2469. static const unsigned int msiof1_clk_e_pins[] = {
  2470. /* SCK */
  2471. RCAR_GP_PIN(3, 0),
  2472. };
  2473. static const unsigned int msiof1_clk_e_mux[] = {
  2474. MSIOF1_SCK_E_MARK,
  2475. };
  2476. static const unsigned int msiof1_sync_e_pins[] = {
  2477. /* SYNC */
  2478. RCAR_GP_PIN(3, 1),
  2479. };
  2480. static const unsigned int msiof1_sync_e_mux[] = {
  2481. MSIOF1_SYNC_E_MARK,
  2482. };
  2483. static const unsigned int msiof1_ss1_e_pins[] = {
  2484. /* SS1 */
  2485. RCAR_GP_PIN(3, 4),
  2486. };
  2487. static const unsigned int msiof1_ss1_e_mux[] = {
  2488. MSIOF1_SS1_E_MARK,
  2489. };
  2490. static const unsigned int msiof1_ss2_e_pins[] = {
  2491. /* SS2 */
  2492. RCAR_GP_PIN(3, 5),
  2493. };
  2494. static const unsigned int msiof1_ss2_e_mux[] = {
  2495. MSIOF1_SS2_E_MARK,
  2496. };
  2497. static const unsigned int msiof1_txd_e_pins[] = {
  2498. /* TXD */
  2499. RCAR_GP_PIN(3, 3),
  2500. };
  2501. static const unsigned int msiof1_txd_e_mux[] = {
  2502. MSIOF1_TXD_E_MARK,
  2503. };
  2504. static const unsigned int msiof1_rxd_e_pins[] = {
  2505. /* RXD */
  2506. RCAR_GP_PIN(3, 2),
  2507. };
  2508. static const unsigned int msiof1_rxd_e_mux[] = {
  2509. MSIOF1_RXD_E_MARK,
  2510. };
  2511. static const unsigned int msiof1_clk_f_pins[] = {
  2512. /* SCK */
  2513. RCAR_GP_PIN(5, 23),
  2514. };
  2515. static const unsigned int msiof1_clk_f_mux[] = {
  2516. MSIOF1_SCK_F_MARK,
  2517. };
  2518. static const unsigned int msiof1_sync_f_pins[] = {
  2519. /* SYNC */
  2520. RCAR_GP_PIN(5, 24),
  2521. };
  2522. static const unsigned int msiof1_sync_f_mux[] = {
  2523. MSIOF1_SYNC_F_MARK,
  2524. };
  2525. static const unsigned int msiof1_ss1_f_pins[] = {
  2526. /* SS1 */
  2527. RCAR_GP_PIN(6, 1),
  2528. };
  2529. static const unsigned int msiof1_ss1_f_mux[] = {
  2530. MSIOF1_SS1_F_MARK,
  2531. };
  2532. static const unsigned int msiof1_ss2_f_pins[] = {
  2533. /* SS2 */
  2534. RCAR_GP_PIN(6, 2),
  2535. };
  2536. static const unsigned int msiof1_ss2_f_mux[] = {
  2537. MSIOF1_SS2_F_MARK,
  2538. };
  2539. static const unsigned int msiof1_txd_f_pins[] = {
  2540. /* TXD */
  2541. RCAR_GP_PIN(6, 0),
  2542. };
  2543. static const unsigned int msiof1_txd_f_mux[] = {
  2544. MSIOF1_TXD_F_MARK,
  2545. };
  2546. static const unsigned int msiof1_rxd_f_pins[] = {
  2547. /* RXD */
  2548. RCAR_GP_PIN(5, 25),
  2549. };
  2550. static const unsigned int msiof1_rxd_f_mux[] = {
  2551. MSIOF1_RXD_F_MARK,
  2552. };
  2553. static const unsigned int msiof1_clk_g_pins[] = {
  2554. /* SCK */
  2555. RCAR_GP_PIN(3, 6),
  2556. };
  2557. static const unsigned int msiof1_clk_g_mux[] = {
  2558. MSIOF1_SCK_G_MARK,
  2559. };
  2560. static const unsigned int msiof1_sync_g_pins[] = {
  2561. /* SYNC */
  2562. RCAR_GP_PIN(3, 7),
  2563. };
  2564. static const unsigned int msiof1_sync_g_mux[] = {
  2565. MSIOF1_SYNC_G_MARK,
  2566. };
  2567. static const unsigned int msiof1_ss1_g_pins[] = {
  2568. /* SS1 */
  2569. RCAR_GP_PIN(3, 10),
  2570. };
  2571. static const unsigned int msiof1_ss1_g_mux[] = {
  2572. MSIOF1_SS1_G_MARK,
  2573. };
  2574. static const unsigned int msiof1_ss2_g_pins[] = {
  2575. /* SS2 */
  2576. RCAR_GP_PIN(3, 11),
  2577. };
  2578. static const unsigned int msiof1_ss2_g_mux[] = {
  2579. MSIOF1_SS2_G_MARK,
  2580. };
  2581. static const unsigned int msiof1_txd_g_pins[] = {
  2582. /* TXD */
  2583. RCAR_GP_PIN(3, 9),
  2584. };
  2585. static const unsigned int msiof1_txd_g_mux[] = {
  2586. MSIOF1_TXD_G_MARK,
  2587. };
  2588. static const unsigned int msiof1_rxd_g_pins[] = {
  2589. /* RXD */
  2590. RCAR_GP_PIN(3, 8),
  2591. };
  2592. static const unsigned int msiof1_rxd_g_mux[] = {
  2593. MSIOF1_RXD_G_MARK,
  2594. };
  2595. /* - MSIOF2 ----------------------------------------------------------------- */
  2596. static const unsigned int msiof2_clk_a_pins[] = {
  2597. /* SCK */
  2598. RCAR_GP_PIN(1, 9),
  2599. };
  2600. static const unsigned int msiof2_clk_a_mux[] = {
  2601. MSIOF2_SCK_A_MARK,
  2602. };
  2603. static const unsigned int msiof2_sync_a_pins[] = {
  2604. /* SYNC */
  2605. RCAR_GP_PIN(1, 8),
  2606. };
  2607. static const unsigned int msiof2_sync_a_mux[] = {
  2608. MSIOF2_SYNC_A_MARK,
  2609. };
  2610. static const unsigned int msiof2_ss1_a_pins[] = {
  2611. /* SS1 */
  2612. RCAR_GP_PIN(1, 6),
  2613. };
  2614. static const unsigned int msiof2_ss1_a_mux[] = {
  2615. MSIOF2_SS1_A_MARK,
  2616. };
  2617. static const unsigned int msiof2_ss2_a_pins[] = {
  2618. /* SS2 */
  2619. RCAR_GP_PIN(1, 7),
  2620. };
  2621. static const unsigned int msiof2_ss2_a_mux[] = {
  2622. MSIOF2_SS2_A_MARK,
  2623. };
  2624. static const unsigned int msiof2_txd_a_pins[] = {
  2625. /* TXD */
  2626. RCAR_GP_PIN(1, 11),
  2627. };
  2628. static const unsigned int msiof2_txd_a_mux[] = {
  2629. MSIOF2_TXD_A_MARK,
  2630. };
  2631. static const unsigned int msiof2_rxd_a_pins[] = {
  2632. /* RXD */
  2633. RCAR_GP_PIN(1, 10),
  2634. };
  2635. static const unsigned int msiof2_rxd_a_mux[] = {
  2636. MSIOF2_RXD_A_MARK,
  2637. };
  2638. static const unsigned int msiof2_clk_b_pins[] = {
  2639. /* SCK */
  2640. RCAR_GP_PIN(0, 4),
  2641. };
  2642. static const unsigned int msiof2_clk_b_mux[] = {
  2643. MSIOF2_SCK_B_MARK,
  2644. };
  2645. static const unsigned int msiof2_sync_b_pins[] = {
  2646. /* SYNC */
  2647. RCAR_GP_PIN(0, 5),
  2648. };
  2649. static const unsigned int msiof2_sync_b_mux[] = {
  2650. MSIOF2_SYNC_B_MARK,
  2651. };
  2652. static const unsigned int msiof2_ss1_b_pins[] = {
  2653. /* SS1 */
  2654. RCAR_GP_PIN(0, 0),
  2655. };
  2656. static const unsigned int msiof2_ss1_b_mux[] = {
  2657. MSIOF2_SS1_B_MARK,
  2658. };
  2659. static const unsigned int msiof2_ss2_b_pins[] = {
  2660. /* SS2 */
  2661. RCAR_GP_PIN(0, 1),
  2662. };
  2663. static const unsigned int msiof2_ss2_b_mux[] = {
  2664. MSIOF2_SS2_B_MARK,
  2665. };
  2666. static const unsigned int msiof2_txd_b_pins[] = {
  2667. /* TXD */
  2668. RCAR_GP_PIN(0, 7),
  2669. };
  2670. static const unsigned int msiof2_txd_b_mux[] = {
  2671. MSIOF2_TXD_B_MARK,
  2672. };
  2673. static const unsigned int msiof2_rxd_b_pins[] = {
  2674. /* RXD */
  2675. RCAR_GP_PIN(0, 6),
  2676. };
  2677. static const unsigned int msiof2_rxd_b_mux[] = {
  2678. MSIOF2_RXD_B_MARK,
  2679. };
  2680. static const unsigned int msiof2_clk_c_pins[] = {
  2681. /* SCK */
  2682. RCAR_GP_PIN(2, 12),
  2683. };
  2684. static const unsigned int msiof2_clk_c_mux[] = {
  2685. MSIOF2_SCK_C_MARK,
  2686. };
  2687. static const unsigned int msiof2_sync_c_pins[] = {
  2688. /* SYNC */
  2689. RCAR_GP_PIN(2, 11),
  2690. };
  2691. static const unsigned int msiof2_sync_c_mux[] = {
  2692. MSIOF2_SYNC_C_MARK,
  2693. };
  2694. static const unsigned int msiof2_ss1_c_pins[] = {
  2695. /* SS1 */
  2696. RCAR_GP_PIN(2, 10),
  2697. };
  2698. static const unsigned int msiof2_ss1_c_mux[] = {
  2699. MSIOF2_SS1_C_MARK,
  2700. };
  2701. static const unsigned int msiof2_ss2_c_pins[] = {
  2702. /* SS2 */
  2703. RCAR_GP_PIN(2, 9),
  2704. };
  2705. static const unsigned int msiof2_ss2_c_mux[] = {
  2706. MSIOF2_SS2_C_MARK,
  2707. };
  2708. static const unsigned int msiof2_txd_c_pins[] = {
  2709. /* TXD */
  2710. RCAR_GP_PIN(2, 14),
  2711. };
  2712. static const unsigned int msiof2_txd_c_mux[] = {
  2713. MSIOF2_TXD_C_MARK,
  2714. };
  2715. static const unsigned int msiof2_rxd_c_pins[] = {
  2716. /* RXD */
  2717. RCAR_GP_PIN(2, 13),
  2718. };
  2719. static const unsigned int msiof2_rxd_c_mux[] = {
  2720. MSIOF2_RXD_C_MARK,
  2721. };
  2722. static const unsigned int msiof2_clk_d_pins[] = {
  2723. /* SCK */
  2724. RCAR_GP_PIN(0, 8),
  2725. };
  2726. static const unsigned int msiof2_clk_d_mux[] = {
  2727. MSIOF2_SCK_D_MARK,
  2728. };
  2729. static const unsigned int msiof2_sync_d_pins[] = {
  2730. /* SYNC */
  2731. RCAR_GP_PIN(0, 9),
  2732. };
  2733. static const unsigned int msiof2_sync_d_mux[] = {
  2734. MSIOF2_SYNC_D_MARK,
  2735. };
  2736. static const unsigned int msiof2_ss1_d_pins[] = {
  2737. /* SS1 */
  2738. RCAR_GP_PIN(0, 12),
  2739. };
  2740. static const unsigned int msiof2_ss1_d_mux[] = {
  2741. MSIOF2_SS1_D_MARK,
  2742. };
  2743. static const unsigned int msiof2_ss2_d_pins[] = {
  2744. /* SS2 */
  2745. RCAR_GP_PIN(0, 13),
  2746. };
  2747. static const unsigned int msiof2_ss2_d_mux[] = {
  2748. MSIOF2_SS2_D_MARK,
  2749. };
  2750. static const unsigned int msiof2_txd_d_pins[] = {
  2751. /* TXD */
  2752. RCAR_GP_PIN(0, 11),
  2753. };
  2754. static const unsigned int msiof2_txd_d_mux[] = {
  2755. MSIOF2_TXD_D_MARK,
  2756. };
  2757. static const unsigned int msiof2_rxd_d_pins[] = {
  2758. /* RXD */
  2759. RCAR_GP_PIN(0, 10),
  2760. };
  2761. static const unsigned int msiof2_rxd_d_mux[] = {
  2762. MSIOF2_RXD_D_MARK,
  2763. };
  2764. /* - MSIOF3 ----------------------------------------------------------------- */
  2765. static const unsigned int msiof3_clk_a_pins[] = {
  2766. /* SCK */
  2767. RCAR_GP_PIN(0, 0),
  2768. };
  2769. static const unsigned int msiof3_clk_a_mux[] = {
  2770. MSIOF3_SCK_A_MARK,
  2771. };
  2772. static const unsigned int msiof3_sync_a_pins[] = {
  2773. /* SYNC */
  2774. RCAR_GP_PIN(0, 1),
  2775. };
  2776. static const unsigned int msiof3_sync_a_mux[] = {
  2777. MSIOF3_SYNC_A_MARK,
  2778. };
  2779. static const unsigned int msiof3_ss1_a_pins[] = {
  2780. /* SS1 */
  2781. RCAR_GP_PIN(0, 14),
  2782. };
  2783. static const unsigned int msiof3_ss1_a_mux[] = {
  2784. MSIOF3_SS1_A_MARK,
  2785. };
  2786. static const unsigned int msiof3_ss2_a_pins[] = {
  2787. /* SS2 */
  2788. RCAR_GP_PIN(0, 15),
  2789. };
  2790. static const unsigned int msiof3_ss2_a_mux[] = {
  2791. MSIOF3_SS2_A_MARK,
  2792. };
  2793. static const unsigned int msiof3_txd_a_pins[] = {
  2794. /* TXD */
  2795. RCAR_GP_PIN(0, 3),
  2796. };
  2797. static const unsigned int msiof3_txd_a_mux[] = {
  2798. MSIOF3_TXD_A_MARK,
  2799. };
  2800. static const unsigned int msiof3_rxd_a_pins[] = {
  2801. /* RXD */
  2802. RCAR_GP_PIN(0, 2),
  2803. };
  2804. static const unsigned int msiof3_rxd_a_mux[] = {
  2805. MSIOF3_RXD_A_MARK,
  2806. };
  2807. static const unsigned int msiof3_clk_b_pins[] = {
  2808. /* SCK */
  2809. RCAR_GP_PIN(1, 2),
  2810. };
  2811. static const unsigned int msiof3_clk_b_mux[] = {
  2812. MSIOF3_SCK_B_MARK,
  2813. };
  2814. static const unsigned int msiof3_sync_b_pins[] = {
  2815. /* SYNC */
  2816. RCAR_GP_PIN(1, 0),
  2817. };
  2818. static const unsigned int msiof3_sync_b_mux[] = {
  2819. MSIOF3_SYNC_B_MARK,
  2820. };
  2821. static const unsigned int msiof3_ss1_b_pins[] = {
  2822. /* SS1 */
  2823. RCAR_GP_PIN(1, 4),
  2824. };
  2825. static const unsigned int msiof3_ss1_b_mux[] = {
  2826. MSIOF3_SS1_B_MARK,
  2827. };
  2828. static const unsigned int msiof3_ss2_b_pins[] = {
  2829. /* SS2 */
  2830. RCAR_GP_PIN(1, 5),
  2831. };
  2832. static const unsigned int msiof3_ss2_b_mux[] = {
  2833. MSIOF3_SS2_B_MARK,
  2834. };
  2835. static const unsigned int msiof3_txd_b_pins[] = {
  2836. /* TXD */
  2837. RCAR_GP_PIN(1, 1),
  2838. };
  2839. static const unsigned int msiof3_txd_b_mux[] = {
  2840. MSIOF3_TXD_B_MARK,
  2841. };
  2842. static const unsigned int msiof3_rxd_b_pins[] = {
  2843. /* RXD */
  2844. RCAR_GP_PIN(1, 3),
  2845. };
  2846. static const unsigned int msiof3_rxd_b_mux[] = {
  2847. MSIOF3_RXD_B_MARK,
  2848. };
  2849. static const unsigned int msiof3_clk_c_pins[] = {
  2850. /* SCK */
  2851. RCAR_GP_PIN(1, 12),
  2852. };
  2853. static const unsigned int msiof3_clk_c_mux[] = {
  2854. MSIOF3_SCK_C_MARK,
  2855. };
  2856. static const unsigned int msiof3_sync_c_pins[] = {
  2857. /* SYNC */
  2858. RCAR_GP_PIN(1, 13),
  2859. };
  2860. static const unsigned int msiof3_sync_c_mux[] = {
  2861. MSIOF3_SYNC_C_MARK,
  2862. };
  2863. static const unsigned int msiof3_txd_c_pins[] = {
  2864. /* TXD */
  2865. RCAR_GP_PIN(1, 15),
  2866. };
  2867. static const unsigned int msiof3_txd_c_mux[] = {
  2868. MSIOF3_TXD_C_MARK,
  2869. };
  2870. static const unsigned int msiof3_rxd_c_pins[] = {
  2871. /* RXD */
  2872. RCAR_GP_PIN(1, 14),
  2873. };
  2874. static const unsigned int msiof3_rxd_c_mux[] = {
  2875. MSIOF3_RXD_C_MARK,
  2876. };
  2877. static const unsigned int msiof3_clk_d_pins[] = {
  2878. /* SCK */
  2879. RCAR_GP_PIN(1, 22),
  2880. };
  2881. static const unsigned int msiof3_clk_d_mux[] = {
  2882. MSIOF3_SCK_D_MARK,
  2883. };
  2884. static const unsigned int msiof3_sync_d_pins[] = {
  2885. /* SYNC */
  2886. RCAR_GP_PIN(1, 23),
  2887. };
  2888. static const unsigned int msiof3_sync_d_mux[] = {
  2889. MSIOF3_SYNC_D_MARK,
  2890. };
  2891. static const unsigned int msiof3_ss1_d_pins[] = {
  2892. /* SS1 */
  2893. RCAR_GP_PIN(1, 26),
  2894. };
  2895. static const unsigned int msiof3_ss1_d_mux[] = {
  2896. MSIOF3_SS1_D_MARK,
  2897. };
  2898. static const unsigned int msiof3_txd_d_pins[] = {
  2899. /* TXD */
  2900. RCAR_GP_PIN(1, 25),
  2901. };
  2902. static const unsigned int msiof3_txd_d_mux[] = {
  2903. MSIOF3_TXD_D_MARK,
  2904. };
  2905. static const unsigned int msiof3_rxd_d_pins[] = {
  2906. /* RXD */
  2907. RCAR_GP_PIN(1, 24),
  2908. };
  2909. static const unsigned int msiof3_rxd_d_mux[] = {
  2910. MSIOF3_RXD_D_MARK,
  2911. };
  2912. static const unsigned int msiof3_clk_e_pins[] = {
  2913. /* SCK */
  2914. RCAR_GP_PIN(2, 3),
  2915. };
  2916. static const unsigned int msiof3_clk_e_mux[] = {
  2917. MSIOF3_SCK_E_MARK,
  2918. };
  2919. static const unsigned int msiof3_sync_e_pins[] = {
  2920. /* SYNC */
  2921. RCAR_GP_PIN(2, 2),
  2922. };
  2923. static const unsigned int msiof3_sync_e_mux[] = {
  2924. MSIOF3_SYNC_E_MARK,
  2925. };
  2926. static const unsigned int msiof3_ss1_e_pins[] = {
  2927. /* SS1 */
  2928. RCAR_GP_PIN(2, 1),
  2929. };
  2930. static const unsigned int msiof3_ss1_e_mux[] = {
  2931. MSIOF3_SS1_E_MARK,
  2932. };
  2933. static const unsigned int msiof3_ss2_e_pins[] = {
  2934. /* SS2 */
  2935. RCAR_GP_PIN(2, 0),
  2936. };
  2937. static const unsigned int msiof3_ss2_e_mux[] = {
  2938. MSIOF3_SS2_E_MARK,
  2939. };
  2940. static const unsigned int msiof3_txd_e_pins[] = {
  2941. /* TXD */
  2942. RCAR_GP_PIN(2, 5),
  2943. };
  2944. static const unsigned int msiof3_txd_e_mux[] = {
  2945. MSIOF3_TXD_E_MARK,
  2946. };
  2947. static const unsigned int msiof3_rxd_e_pins[] = {
  2948. /* RXD */
  2949. RCAR_GP_PIN(2, 4),
  2950. };
  2951. static const unsigned int msiof3_rxd_e_mux[] = {
  2952. MSIOF3_RXD_E_MARK,
  2953. };
  2954. /* - PWM0 --------------------------------------------------------------------*/
  2955. static const unsigned int pwm0_pins[] = {
  2956. /* PWM */
  2957. RCAR_GP_PIN(2, 6),
  2958. };
  2959. static const unsigned int pwm0_mux[] = {
  2960. PWM0_MARK,
  2961. };
  2962. /* - PWM1 --------------------------------------------------------------------*/
  2963. static const unsigned int pwm1_a_pins[] = {
  2964. /* PWM */
  2965. RCAR_GP_PIN(2, 7),
  2966. };
  2967. static const unsigned int pwm1_a_mux[] = {
  2968. PWM1_A_MARK,
  2969. };
  2970. static const unsigned int pwm1_b_pins[] = {
  2971. /* PWM */
  2972. RCAR_GP_PIN(1, 8),
  2973. };
  2974. static const unsigned int pwm1_b_mux[] = {
  2975. PWM1_B_MARK,
  2976. };
  2977. /* - PWM2 --------------------------------------------------------------------*/
  2978. static const unsigned int pwm2_a_pins[] = {
  2979. /* PWM */
  2980. RCAR_GP_PIN(2, 8),
  2981. };
  2982. static const unsigned int pwm2_a_mux[] = {
  2983. PWM2_A_MARK,
  2984. };
  2985. static const unsigned int pwm2_b_pins[] = {
  2986. /* PWM */
  2987. RCAR_GP_PIN(1, 11),
  2988. };
  2989. static const unsigned int pwm2_b_mux[] = {
  2990. PWM2_B_MARK,
  2991. };
  2992. /* - PWM3 --------------------------------------------------------------------*/
  2993. static const unsigned int pwm3_a_pins[] = {
  2994. /* PWM */
  2995. RCAR_GP_PIN(1, 0),
  2996. };
  2997. static const unsigned int pwm3_a_mux[] = {
  2998. PWM3_A_MARK,
  2999. };
  3000. static const unsigned int pwm3_b_pins[] = {
  3001. /* PWM */
  3002. RCAR_GP_PIN(2, 2),
  3003. };
  3004. static const unsigned int pwm3_b_mux[] = {
  3005. PWM3_B_MARK,
  3006. };
  3007. /* - PWM4 --------------------------------------------------------------------*/
  3008. static const unsigned int pwm4_a_pins[] = {
  3009. /* PWM */
  3010. RCAR_GP_PIN(1, 1),
  3011. };
  3012. static const unsigned int pwm4_a_mux[] = {
  3013. PWM4_A_MARK,
  3014. };
  3015. static const unsigned int pwm4_b_pins[] = {
  3016. /* PWM */
  3017. RCAR_GP_PIN(2, 3),
  3018. };
  3019. static const unsigned int pwm4_b_mux[] = {
  3020. PWM4_B_MARK,
  3021. };
  3022. /* - PWM5 --------------------------------------------------------------------*/
  3023. static const unsigned int pwm5_a_pins[] = {
  3024. /* PWM */
  3025. RCAR_GP_PIN(1, 2),
  3026. };
  3027. static const unsigned int pwm5_a_mux[] = {
  3028. PWM5_A_MARK,
  3029. };
  3030. static const unsigned int pwm5_b_pins[] = {
  3031. /* PWM */
  3032. RCAR_GP_PIN(2, 4),
  3033. };
  3034. static const unsigned int pwm5_b_mux[] = {
  3035. PWM5_B_MARK,
  3036. };
  3037. /* - PWM6 --------------------------------------------------------------------*/
  3038. static const unsigned int pwm6_a_pins[] = {
  3039. /* PWM */
  3040. RCAR_GP_PIN(1, 3),
  3041. };
  3042. static const unsigned int pwm6_a_mux[] = {
  3043. PWM6_A_MARK,
  3044. };
  3045. static const unsigned int pwm6_b_pins[] = {
  3046. /* PWM */
  3047. RCAR_GP_PIN(2, 5),
  3048. };
  3049. static const unsigned int pwm6_b_mux[] = {
  3050. PWM6_B_MARK,
  3051. };
  3052. /* - QSPI0 ------------------------------------------------------------------ */
  3053. static const unsigned int qspi0_ctrl_pins[] = {
  3054. /* QSPI0_SPCLK, QSPI0_SSL */
  3055. PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
  3056. };
  3057. static const unsigned int qspi0_ctrl_mux[] = {
  3058. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  3059. };
  3060. static const unsigned int qspi0_data2_pins[] = {
  3061. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
  3062. PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
  3063. };
  3064. static const unsigned int qspi0_data2_mux[] = {
  3065. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  3066. };
  3067. static const unsigned int qspi0_data4_pins[] = {
  3068. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
  3069. PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
  3070. /* QSPI0_IO2, QSPI0_IO3 */
  3071. PIN_QSPI0_IO2, PIN_QSPI0_IO3,
  3072. };
  3073. static const unsigned int qspi0_data4_mux[] = {
  3074. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  3075. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  3076. };
  3077. /* - QSPI1 ------------------------------------------------------------------ */
  3078. static const unsigned int qspi1_ctrl_pins[] = {
  3079. /* QSPI1_SPCLK, QSPI1_SSL */
  3080. PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
  3081. };
  3082. static const unsigned int qspi1_ctrl_mux[] = {
  3083. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  3084. };
  3085. static const unsigned int qspi1_data2_pins[] = {
  3086. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
  3087. PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
  3088. };
  3089. static const unsigned int qspi1_data2_mux[] = {
  3090. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  3091. };
  3092. static const unsigned int qspi1_data4_pins[] = {
  3093. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
  3094. PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
  3095. /* QSPI1_IO2, QSPI1_IO3 */
  3096. PIN_QSPI1_IO2, PIN_QSPI1_IO3,
  3097. };
  3098. static const unsigned int qspi1_data4_mux[] = {
  3099. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  3100. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  3101. };
  3102. /* - SCIF0 ------------------------------------------------------------------ */
  3103. static const unsigned int scif0_data_pins[] = {
  3104. /* RX, TX */
  3105. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  3106. };
  3107. static const unsigned int scif0_data_mux[] = {
  3108. RX0_MARK, TX0_MARK,
  3109. };
  3110. static const unsigned int scif0_clk_pins[] = {
  3111. /* SCK */
  3112. RCAR_GP_PIN(5, 0),
  3113. };
  3114. static const unsigned int scif0_clk_mux[] = {
  3115. SCK0_MARK,
  3116. };
  3117. static const unsigned int scif0_ctrl_pins[] = {
  3118. /* RTS, CTS */
  3119. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  3120. };
  3121. static const unsigned int scif0_ctrl_mux[] = {
  3122. RTS0_N_MARK, CTS0_N_MARK,
  3123. };
  3124. /* - SCIF1 ------------------------------------------------------------------ */
  3125. static const unsigned int scif1_data_a_pins[] = {
  3126. /* RX, TX */
  3127. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  3128. };
  3129. static const unsigned int scif1_data_a_mux[] = {
  3130. RX1_A_MARK, TX1_A_MARK,
  3131. };
  3132. static const unsigned int scif1_clk_pins[] = {
  3133. /* SCK */
  3134. RCAR_GP_PIN(6, 21),
  3135. };
  3136. static const unsigned int scif1_clk_mux[] = {
  3137. SCK1_MARK,
  3138. };
  3139. static const unsigned int scif1_ctrl_pins[] = {
  3140. /* RTS, CTS */
  3141. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  3142. };
  3143. static const unsigned int scif1_ctrl_mux[] = {
  3144. RTS1_N_MARK, CTS1_N_MARK,
  3145. };
  3146. static const unsigned int scif1_data_b_pins[] = {
  3147. /* RX, TX */
  3148. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  3149. };
  3150. static const unsigned int scif1_data_b_mux[] = {
  3151. RX1_B_MARK, TX1_B_MARK,
  3152. };
  3153. /* - SCIF2 ------------------------------------------------------------------ */
  3154. static const unsigned int scif2_data_a_pins[] = {
  3155. /* RX, TX */
  3156. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  3157. };
  3158. static const unsigned int scif2_data_a_mux[] = {
  3159. RX2_A_MARK, TX2_A_MARK,
  3160. };
  3161. static const unsigned int scif2_clk_pins[] = {
  3162. /* SCK */
  3163. RCAR_GP_PIN(5, 9),
  3164. };
  3165. static const unsigned int scif2_clk_mux[] = {
  3166. SCK2_MARK,
  3167. };
  3168. static const unsigned int scif2_data_b_pins[] = {
  3169. /* RX, TX */
  3170. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3171. };
  3172. static const unsigned int scif2_data_b_mux[] = {
  3173. RX2_B_MARK, TX2_B_MARK,
  3174. };
  3175. /* - SCIF3 ------------------------------------------------------------------ */
  3176. static const unsigned int scif3_data_a_pins[] = {
  3177. /* RX, TX */
  3178. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  3179. };
  3180. static const unsigned int scif3_data_a_mux[] = {
  3181. RX3_A_MARK, TX3_A_MARK,
  3182. };
  3183. static const unsigned int scif3_clk_pins[] = {
  3184. /* SCK */
  3185. RCAR_GP_PIN(1, 22),
  3186. };
  3187. static const unsigned int scif3_clk_mux[] = {
  3188. SCK3_MARK,
  3189. };
  3190. static const unsigned int scif3_ctrl_pins[] = {
  3191. /* RTS, CTS */
  3192. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  3193. };
  3194. static const unsigned int scif3_ctrl_mux[] = {
  3195. RTS3_N_MARK, CTS3_N_MARK,
  3196. };
  3197. static const unsigned int scif3_data_b_pins[] = {
  3198. /* RX, TX */
  3199. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  3200. };
  3201. static const unsigned int scif3_data_b_mux[] = {
  3202. RX3_B_MARK, TX3_B_MARK,
  3203. };
  3204. /* - SCIF4 ------------------------------------------------------------------ */
  3205. static const unsigned int scif4_data_a_pins[] = {
  3206. /* RX, TX */
  3207. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
  3208. };
  3209. static const unsigned int scif4_data_a_mux[] = {
  3210. RX4_A_MARK, TX4_A_MARK,
  3211. };
  3212. static const unsigned int scif4_clk_a_pins[] = {
  3213. /* SCK */
  3214. RCAR_GP_PIN(2, 10),
  3215. };
  3216. static const unsigned int scif4_clk_a_mux[] = {
  3217. SCK4_A_MARK,
  3218. };
  3219. static const unsigned int scif4_ctrl_a_pins[] = {
  3220. /* RTS, CTS */
  3221. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  3222. };
  3223. static const unsigned int scif4_ctrl_a_mux[] = {
  3224. RTS4_N_A_MARK, CTS4_N_A_MARK,
  3225. };
  3226. static const unsigned int scif4_data_b_pins[] = {
  3227. /* RX, TX */
  3228. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3229. };
  3230. static const unsigned int scif4_data_b_mux[] = {
  3231. RX4_B_MARK, TX4_B_MARK,
  3232. };
  3233. static const unsigned int scif4_clk_b_pins[] = {
  3234. /* SCK */
  3235. RCAR_GP_PIN(1, 5),
  3236. };
  3237. static const unsigned int scif4_clk_b_mux[] = {
  3238. SCK4_B_MARK,
  3239. };
  3240. static const unsigned int scif4_ctrl_b_pins[] = {
  3241. /* RTS, CTS */
  3242. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
  3243. };
  3244. static const unsigned int scif4_ctrl_b_mux[] = {
  3245. RTS4_N_B_MARK, CTS4_N_B_MARK,
  3246. };
  3247. static const unsigned int scif4_data_c_pins[] = {
  3248. /* RX, TX */
  3249. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3250. };
  3251. static const unsigned int scif4_data_c_mux[] = {
  3252. RX4_C_MARK, TX4_C_MARK,
  3253. };
  3254. static const unsigned int scif4_clk_c_pins[] = {
  3255. /* SCK */
  3256. RCAR_GP_PIN(0, 8),
  3257. };
  3258. static const unsigned int scif4_clk_c_mux[] = {
  3259. SCK4_C_MARK,
  3260. };
  3261. static const unsigned int scif4_ctrl_c_pins[] = {
  3262. /* RTS, CTS */
  3263. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  3264. };
  3265. static const unsigned int scif4_ctrl_c_mux[] = {
  3266. RTS4_N_C_MARK, CTS4_N_C_MARK,
  3267. };
  3268. /* - SCIF5 ------------------------------------------------------------------ */
  3269. static const unsigned int scif5_data_a_pins[] = {
  3270. /* RX, TX */
  3271. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3272. };
  3273. static const unsigned int scif5_data_a_mux[] = {
  3274. RX5_A_MARK, TX5_A_MARK,
  3275. };
  3276. static const unsigned int scif5_clk_a_pins[] = {
  3277. /* SCK */
  3278. RCAR_GP_PIN(6, 21),
  3279. };
  3280. static const unsigned int scif5_clk_a_mux[] = {
  3281. SCK5_A_MARK,
  3282. };
  3283. static const unsigned int scif5_data_b_pins[] = {
  3284. /* RX, TX */
  3285. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
  3286. };
  3287. static const unsigned int scif5_data_b_mux[] = {
  3288. RX5_B_MARK, TX5_B_MARK,
  3289. };
  3290. static const unsigned int scif5_clk_b_pins[] = {
  3291. /* SCK */
  3292. RCAR_GP_PIN(5, 0),
  3293. };
  3294. static const unsigned int scif5_clk_b_mux[] = {
  3295. SCK5_B_MARK,
  3296. };
  3297. /* - SCIF Clock ------------------------------------------------------------- */
  3298. static const unsigned int scif_clk_a_pins[] = {
  3299. /* SCIF_CLK */
  3300. RCAR_GP_PIN(6, 23),
  3301. };
  3302. static const unsigned int scif_clk_a_mux[] = {
  3303. SCIF_CLK_A_MARK,
  3304. };
  3305. static const unsigned int scif_clk_b_pins[] = {
  3306. /* SCIF_CLK */
  3307. RCAR_GP_PIN(5, 9),
  3308. };
  3309. static const unsigned int scif_clk_b_mux[] = {
  3310. SCIF_CLK_B_MARK,
  3311. };
  3312. /* - SDHI0 ------------------------------------------------------------------ */
  3313. static const unsigned int sdhi0_data1_pins[] = {
  3314. /* D0 */
  3315. RCAR_GP_PIN(3, 2),
  3316. };
  3317. static const unsigned int sdhi0_data1_mux[] = {
  3318. SD0_DAT0_MARK,
  3319. };
  3320. static const unsigned int sdhi0_data4_pins[] = {
  3321. /* D[0:3] */
  3322. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  3323. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  3324. };
  3325. static const unsigned int sdhi0_data4_mux[] = {
  3326. SD0_DAT0_MARK, SD0_DAT1_MARK,
  3327. SD0_DAT2_MARK, SD0_DAT3_MARK,
  3328. };
  3329. static const unsigned int sdhi0_ctrl_pins[] = {
  3330. /* CLK, CMD */
  3331. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  3332. };
  3333. static const unsigned int sdhi0_ctrl_mux[] = {
  3334. SD0_CLK_MARK, SD0_CMD_MARK,
  3335. };
  3336. static const unsigned int sdhi0_cd_pins[] = {
  3337. /* CD */
  3338. RCAR_GP_PIN(3, 12),
  3339. };
  3340. static const unsigned int sdhi0_cd_mux[] = {
  3341. SD0_CD_MARK,
  3342. };
  3343. static const unsigned int sdhi0_wp_pins[] = {
  3344. /* WP */
  3345. RCAR_GP_PIN(3, 13),
  3346. };
  3347. static const unsigned int sdhi0_wp_mux[] = {
  3348. SD0_WP_MARK,
  3349. };
  3350. /* - SDHI1 ------------------------------------------------------------------ */
  3351. static const unsigned int sdhi1_data1_pins[] = {
  3352. /* D0 */
  3353. RCAR_GP_PIN(3, 8),
  3354. };
  3355. static const unsigned int sdhi1_data1_mux[] = {
  3356. SD1_DAT0_MARK,
  3357. };
  3358. static const unsigned int sdhi1_data4_pins[] = {
  3359. /* D[0:3] */
  3360. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3361. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3362. };
  3363. static const unsigned int sdhi1_data4_mux[] = {
  3364. SD1_DAT0_MARK, SD1_DAT1_MARK,
  3365. SD1_DAT2_MARK, SD1_DAT3_MARK,
  3366. };
  3367. static const unsigned int sdhi1_ctrl_pins[] = {
  3368. /* CLK, CMD */
  3369. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  3370. };
  3371. static const unsigned int sdhi1_ctrl_mux[] = {
  3372. SD1_CLK_MARK, SD1_CMD_MARK,
  3373. };
  3374. static const unsigned int sdhi1_cd_pins[] = {
  3375. /* CD */
  3376. RCAR_GP_PIN(3, 14),
  3377. };
  3378. static const unsigned int sdhi1_cd_mux[] = {
  3379. SD1_CD_MARK,
  3380. };
  3381. static const unsigned int sdhi1_wp_pins[] = {
  3382. /* WP */
  3383. RCAR_GP_PIN(3, 15),
  3384. };
  3385. static const unsigned int sdhi1_wp_mux[] = {
  3386. SD1_WP_MARK,
  3387. };
  3388. /* - SDHI2 ------------------------------------------------------------------ */
  3389. static const unsigned int sdhi2_data1_pins[] = {
  3390. /* D0 */
  3391. RCAR_GP_PIN(4, 2),
  3392. };
  3393. static const unsigned int sdhi2_data1_mux[] = {
  3394. SD2_DAT0_MARK,
  3395. };
  3396. static const unsigned int sdhi2_data4_pins[] = {
  3397. /* D[0:3] */
  3398. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3399. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3400. };
  3401. static const unsigned int sdhi2_data4_mux[] = {
  3402. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3403. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3404. };
  3405. static const unsigned int sdhi2_data8_pins[] = {
  3406. /* D[0:7] */
  3407. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3408. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3409. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3410. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3411. };
  3412. static const unsigned int sdhi2_data8_mux[] = {
  3413. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3414. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3415. SD2_DAT4_MARK, SD2_DAT5_MARK,
  3416. SD2_DAT6_MARK, SD2_DAT7_MARK,
  3417. };
  3418. static const unsigned int sdhi2_ctrl_pins[] = {
  3419. /* CLK, CMD */
  3420. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  3421. };
  3422. static const unsigned int sdhi2_ctrl_mux[] = {
  3423. SD2_CLK_MARK, SD2_CMD_MARK,
  3424. };
  3425. static const unsigned int sdhi2_cd_a_pins[] = {
  3426. /* CD */
  3427. RCAR_GP_PIN(4, 13),
  3428. };
  3429. static const unsigned int sdhi2_cd_a_mux[] = {
  3430. SD2_CD_A_MARK,
  3431. };
  3432. static const unsigned int sdhi2_cd_b_pins[] = {
  3433. /* CD */
  3434. RCAR_GP_PIN(5, 10),
  3435. };
  3436. static const unsigned int sdhi2_cd_b_mux[] = {
  3437. SD2_CD_B_MARK,
  3438. };
  3439. static const unsigned int sdhi2_wp_a_pins[] = {
  3440. /* WP */
  3441. RCAR_GP_PIN(4, 14),
  3442. };
  3443. static const unsigned int sdhi2_wp_a_mux[] = {
  3444. SD2_WP_A_MARK,
  3445. };
  3446. static const unsigned int sdhi2_wp_b_pins[] = {
  3447. /* WP */
  3448. RCAR_GP_PIN(5, 11),
  3449. };
  3450. static const unsigned int sdhi2_wp_b_mux[] = {
  3451. SD2_WP_B_MARK,
  3452. };
  3453. static const unsigned int sdhi2_ds_pins[] = {
  3454. /* DS */
  3455. RCAR_GP_PIN(4, 6),
  3456. };
  3457. static const unsigned int sdhi2_ds_mux[] = {
  3458. SD2_DS_MARK,
  3459. };
  3460. /* - SDHI3 ------------------------------------------------------------------ */
  3461. static const unsigned int sdhi3_data1_pins[] = {
  3462. /* D0 */
  3463. RCAR_GP_PIN(4, 9),
  3464. };
  3465. static const unsigned int sdhi3_data1_mux[] = {
  3466. SD3_DAT0_MARK,
  3467. };
  3468. static const unsigned int sdhi3_data4_pins[] = {
  3469. /* D[0:3] */
  3470. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3471. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3472. };
  3473. static const unsigned int sdhi3_data4_mux[] = {
  3474. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3475. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3476. };
  3477. static const unsigned int sdhi3_data8_pins[] = {
  3478. /* D[0:7] */
  3479. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3480. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3481. RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
  3482. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
  3483. };
  3484. static const unsigned int sdhi3_data8_mux[] = {
  3485. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3486. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3487. SD3_DAT4_MARK, SD3_DAT5_MARK,
  3488. SD3_DAT6_MARK, SD3_DAT7_MARK,
  3489. };
  3490. static const unsigned int sdhi3_ctrl_pins[] = {
  3491. /* CLK, CMD */
  3492. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
  3493. };
  3494. static const unsigned int sdhi3_ctrl_mux[] = {
  3495. SD3_CLK_MARK, SD3_CMD_MARK,
  3496. };
  3497. static const unsigned int sdhi3_cd_pins[] = {
  3498. /* CD */
  3499. RCAR_GP_PIN(4, 15),
  3500. };
  3501. static const unsigned int sdhi3_cd_mux[] = {
  3502. SD3_CD_MARK,
  3503. };
  3504. static const unsigned int sdhi3_wp_pins[] = {
  3505. /* WP */
  3506. RCAR_GP_PIN(4, 16),
  3507. };
  3508. static const unsigned int sdhi3_wp_mux[] = {
  3509. SD3_WP_MARK,
  3510. };
  3511. static const unsigned int sdhi3_ds_pins[] = {
  3512. /* DS */
  3513. RCAR_GP_PIN(4, 17),
  3514. };
  3515. static const unsigned int sdhi3_ds_mux[] = {
  3516. SD3_DS_MARK,
  3517. };
  3518. /* - SSI -------------------------------------------------------------------- */
  3519. static const unsigned int ssi0_data_pins[] = {
  3520. /* SDATA */
  3521. RCAR_GP_PIN(6, 2),
  3522. };
  3523. static const unsigned int ssi0_data_mux[] = {
  3524. SSI_SDATA0_MARK,
  3525. };
  3526. static const unsigned int ssi01239_ctrl_pins[] = {
  3527. /* SCK, WS */
  3528. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  3529. };
  3530. static const unsigned int ssi01239_ctrl_mux[] = {
  3531. SSI_SCK01239_MARK, SSI_WS01239_MARK,
  3532. };
  3533. static const unsigned int ssi1_data_a_pins[] = {
  3534. /* SDATA */
  3535. RCAR_GP_PIN(6, 3),
  3536. };
  3537. static const unsigned int ssi1_data_a_mux[] = {
  3538. SSI_SDATA1_A_MARK,
  3539. };
  3540. static const unsigned int ssi1_data_b_pins[] = {
  3541. /* SDATA */
  3542. RCAR_GP_PIN(5, 12),
  3543. };
  3544. static const unsigned int ssi1_data_b_mux[] = {
  3545. SSI_SDATA1_B_MARK,
  3546. };
  3547. static const unsigned int ssi1_ctrl_a_pins[] = {
  3548. /* SCK, WS */
  3549. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3550. };
  3551. static const unsigned int ssi1_ctrl_a_mux[] = {
  3552. SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
  3553. };
  3554. static const unsigned int ssi1_ctrl_b_pins[] = {
  3555. /* SCK, WS */
  3556. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
  3557. };
  3558. static const unsigned int ssi1_ctrl_b_mux[] = {
  3559. SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
  3560. };
  3561. static const unsigned int ssi2_data_a_pins[] = {
  3562. /* SDATA */
  3563. RCAR_GP_PIN(6, 4),
  3564. };
  3565. static const unsigned int ssi2_data_a_mux[] = {
  3566. SSI_SDATA2_A_MARK,
  3567. };
  3568. static const unsigned int ssi2_data_b_pins[] = {
  3569. /* SDATA */
  3570. RCAR_GP_PIN(5, 13),
  3571. };
  3572. static const unsigned int ssi2_data_b_mux[] = {
  3573. SSI_SDATA2_B_MARK,
  3574. };
  3575. static const unsigned int ssi2_ctrl_a_pins[] = {
  3576. /* SCK, WS */
  3577. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3578. };
  3579. static const unsigned int ssi2_ctrl_a_mux[] = {
  3580. SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
  3581. };
  3582. static const unsigned int ssi2_ctrl_b_pins[] = {
  3583. /* SCK, WS */
  3584. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3585. };
  3586. static const unsigned int ssi2_ctrl_b_mux[] = {
  3587. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  3588. };
  3589. static const unsigned int ssi3_data_pins[] = {
  3590. /* SDATA */
  3591. RCAR_GP_PIN(6, 7),
  3592. };
  3593. static const unsigned int ssi3_data_mux[] = {
  3594. SSI_SDATA3_MARK,
  3595. };
  3596. static const unsigned int ssi349_ctrl_pins[] = {
  3597. /* SCK, WS */
  3598. RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
  3599. };
  3600. static const unsigned int ssi349_ctrl_mux[] = {
  3601. SSI_SCK349_MARK, SSI_WS349_MARK,
  3602. };
  3603. static const unsigned int ssi4_data_pins[] = {
  3604. /* SDATA */
  3605. RCAR_GP_PIN(6, 10),
  3606. };
  3607. static const unsigned int ssi4_data_mux[] = {
  3608. SSI_SDATA4_MARK,
  3609. };
  3610. static const unsigned int ssi4_ctrl_pins[] = {
  3611. /* SCK, WS */
  3612. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  3613. };
  3614. static const unsigned int ssi4_ctrl_mux[] = {
  3615. SSI_SCK4_MARK, SSI_WS4_MARK,
  3616. };
  3617. static const unsigned int ssi5_data_pins[] = {
  3618. /* SDATA */
  3619. RCAR_GP_PIN(6, 13),
  3620. };
  3621. static const unsigned int ssi5_data_mux[] = {
  3622. SSI_SDATA5_MARK,
  3623. };
  3624. static const unsigned int ssi5_ctrl_pins[] = {
  3625. /* SCK, WS */
  3626. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  3627. };
  3628. static const unsigned int ssi5_ctrl_mux[] = {
  3629. SSI_SCK5_MARK, SSI_WS5_MARK,
  3630. };
  3631. static const unsigned int ssi6_data_pins[] = {
  3632. /* SDATA */
  3633. RCAR_GP_PIN(6, 16),
  3634. };
  3635. static const unsigned int ssi6_data_mux[] = {
  3636. SSI_SDATA6_MARK,
  3637. };
  3638. static const unsigned int ssi6_ctrl_pins[] = {
  3639. /* SCK, WS */
  3640. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  3641. };
  3642. static const unsigned int ssi6_ctrl_mux[] = {
  3643. SSI_SCK6_MARK, SSI_WS6_MARK,
  3644. };
  3645. static const unsigned int ssi7_data_pins[] = {
  3646. /* SDATA */
  3647. RCAR_GP_PIN(6, 19),
  3648. };
  3649. static const unsigned int ssi7_data_mux[] = {
  3650. SSI_SDATA7_MARK,
  3651. };
  3652. static const unsigned int ssi78_ctrl_pins[] = {
  3653. /* SCK, WS */
  3654. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  3655. };
  3656. static const unsigned int ssi78_ctrl_mux[] = {
  3657. SSI_SCK78_MARK, SSI_WS78_MARK,
  3658. };
  3659. static const unsigned int ssi8_data_pins[] = {
  3660. /* SDATA */
  3661. RCAR_GP_PIN(6, 20),
  3662. };
  3663. static const unsigned int ssi8_data_mux[] = {
  3664. SSI_SDATA8_MARK,
  3665. };
  3666. static const unsigned int ssi9_data_a_pins[] = {
  3667. /* SDATA */
  3668. RCAR_GP_PIN(6, 21),
  3669. };
  3670. static const unsigned int ssi9_data_a_mux[] = {
  3671. SSI_SDATA9_A_MARK,
  3672. };
  3673. static const unsigned int ssi9_data_b_pins[] = {
  3674. /* SDATA */
  3675. RCAR_GP_PIN(5, 14),
  3676. };
  3677. static const unsigned int ssi9_data_b_mux[] = {
  3678. SSI_SDATA9_B_MARK,
  3679. };
  3680. static const unsigned int ssi9_ctrl_a_pins[] = {
  3681. /* SCK, WS */
  3682. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3683. };
  3684. static const unsigned int ssi9_ctrl_a_mux[] = {
  3685. SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
  3686. };
  3687. static const unsigned int ssi9_ctrl_b_pins[] = {
  3688. /* SCK, WS */
  3689. RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
  3690. };
  3691. static const unsigned int ssi9_ctrl_b_mux[] = {
  3692. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  3693. };
  3694. /* - TMU -------------------------------------------------------------------- */
  3695. static const unsigned int tmu_tclk1_a_pins[] = {
  3696. /* TCLK */
  3697. RCAR_GP_PIN(6, 23),
  3698. };
  3699. static const unsigned int tmu_tclk1_a_mux[] = {
  3700. TCLK1_A_MARK,
  3701. };
  3702. static const unsigned int tmu_tclk1_b_pins[] = {
  3703. /* TCLK */
  3704. RCAR_GP_PIN(5, 19),
  3705. };
  3706. static const unsigned int tmu_tclk1_b_mux[] = {
  3707. TCLK1_B_MARK,
  3708. };
  3709. static const unsigned int tmu_tclk2_a_pins[] = {
  3710. /* TCLK */
  3711. RCAR_GP_PIN(6, 19),
  3712. };
  3713. static const unsigned int tmu_tclk2_a_mux[] = {
  3714. TCLK2_A_MARK,
  3715. };
  3716. static const unsigned int tmu_tclk2_b_pins[] = {
  3717. /* TCLK */
  3718. RCAR_GP_PIN(6, 28),
  3719. };
  3720. static const unsigned int tmu_tclk2_b_mux[] = {
  3721. TCLK2_B_MARK,
  3722. };
  3723. /* - TPU ------------------------------------------------------------------- */
  3724. static const unsigned int tpu_to0_pins[] = {
  3725. /* TPU0TO0 */
  3726. RCAR_GP_PIN(6, 28),
  3727. };
  3728. static const unsigned int tpu_to0_mux[] = {
  3729. TPU0TO0_MARK,
  3730. };
  3731. static const unsigned int tpu_to1_pins[] = {
  3732. /* TPU0TO1 */
  3733. RCAR_GP_PIN(6, 29),
  3734. };
  3735. static const unsigned int tpu_to1_mux[] = {
  3736. TPU0TO1_MARK,
  3737. };
  3738. static const unsigned int tpu_to2_pins[] = {
  3739. /* TPU0TO2 */
  3740. RCAR_GP_PIN(6, 30),
  3741. };
  3742. static const unsigned int tpu_to2_mux[] = {
  3743. TPU0TO2_MARK,
  3744. };
  3745. static const unsigned int tpu_to3_pins[] = {
  3746. /* TPU0TO3 */
  3747. RCAR_GP_PIN(6, 31),
  3748. };
  3749. static const unsigned int tpu_to3_mux[] = {
  3750. TPU0TO3_MARK,
  3751. };
  3752. /* - USB0 ------------------------------------------------------------------- */
  3753. static const unsigned int usb0_pins[] = {
  3754. /* PWEN, OVC */
  3755. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  3756. };
  3757. static const unsigned int usb0_mux[] = {
  3758. USB0_PWEN_MARK, USB0_OVC_MARK,
  3759. };
  3760. /* - USB1 ------------------------------------------------------------------- */
  3761. static const unsigned int usb1_pins[] = {
  3762. /* PWEN, OVC */
  3763. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3764. };
  3765. static const unsigned int usb1_mux[] = {
  3766. USB1_PWEN_MARK, USB1_OVC_MARK,
  3767. };
  3768. /* - USB30 ------------------------------------------------------------------ */
  3769. static const unsigned int usb30_pins[] = {
  3770. /* PWEN, OVC */
  3771. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3772. };
  3773. static const unsigned int usb30_mux[] = {
  3774. USB30_PWEN_MARK, USB30_OVC_MARK,
  3775. };
  3776. /* - VIN4 ------------------------------------------------------------------- */
  3777. static const unsigned int vin4_data18_a_pins[] = {
  3778. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3779. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3780. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3781. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3782. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3783. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3784. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3785. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3786. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3787. };
  3788. static const unsigned int vin4_data18_a_mux[] = {
  3789. VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
  3790. VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
  3791. VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
  3792. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3793. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3794. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3795. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3796. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3797. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3798. };
  3799. static const unsigned int vin4_data18_b_pins[] = {
  3800. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  3801. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  3802. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  3803. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3804. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3805. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3806. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3807. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3808. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3809. };
  3810. static const unsigned int vin4_data18_b_mux[] = {
  3811. VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
  3812. VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
  3813. VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
  3814. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3815. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3816. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3817. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3818. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3819. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3820. };
  3821. static const union vin_data vin4_data_a_pins = {
  3822. .data24 = {
  3823. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  3824. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3825. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3826. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3827. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
  3828. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3829. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3830. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3831. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3832. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3833. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3834. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3835. },
  3836. };
  3837. static const union vin_data vin4_data_a_mux = {
  3838. .data24 = {
  3839. VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
  3840. VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
  3841. VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
  3842. VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
  3843. VI4_DATA8_MARK, VI4_DATA9_MARK,
  3844. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3845. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3846. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3847. VI4_DATA16_MARK, VI4_DATA17_MARK,
  3848. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3849. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3850. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3851. },
  3852. };
  3853. static const union vin_data vin4_data_b_pins = {
  3854. .data24 = {
  3855. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  3856. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  3857. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  3858. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  3859. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
  3860. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3861. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3862. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3863. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3864. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3865. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3866. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3867. },
  3868. };
  3869. static const union vin_data vin4_data_b_mux = {
  3870. .data24 = {
  3871. VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
  3872. VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
  3873. VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
  3874. VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
  3875. VI4_DATA8_MARK, VI4_DATA9_MARK,
  3876. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3877. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3878. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3879. VI4_DATA16_MARK, VI4_DATA17_MARK,
  3880. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3881. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3882. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3883. },
  3884. };
  3885. static const unsigned int vin4_sync_pins[] = {
  3886. /* HSYNC#, VSYNC# */
  3887. RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
  3888. };
  3889. static const unsigned int vin4_sync_mux[] = {
  3890. VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
  3891. };
  3892. static const unsigned int vin4_field_pins[] = {
  3893. /* FIELD */
  3894. RCAR_GP_PIN(1, 16),
  3895. };
  3896. static const unsigned int vin4_field_mux[] = {
  3897. VI4_FIELD_MARK,
  3898. };
  3899. static const unsigned int vin4_clkenb_pins[] = {
  3900. /* CLKENB */
  3901. RCAR_GP_PIN(1, 19),
  3902. };
  3903. static const unsigned int vin4_clkenb_mux[] = {
  3904. VI4_CLKENB_MARK,
  3905. };
  3906. static const unsigned int vin4_clk_pins[] = {
  3907. /* CLK */
  3908. RCAR_GP_PIN(1, 27),
  3909. };
  3910. static const unsigned int vin4_clk_mux[] = {
  3911. VI4_CLK_MARK,
  3912. };
  3913. /* - VIN5 ------------------------------------------------------------------- */
  3914. static const union vin_data16 vin5_data_pins = {
  3915. .data16 = {
  3916. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3917. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3918. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3919. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3920. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  3921. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  3922. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3923. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3924. },
  3925. };
  3926. static const union vin_data16 vin5_data_mux = {
  3927. .data16 = {
  3928. VI5_DATA0_MARK, VI5_DATA1_MARK,
  3929. VI5_DATA2_MARK, VI5_DATA3_MARK,
  3930. VI5_DATA4_MARK, VI5_DATA5_MARK,
  3931. VI5_DATA6_MARK, VI5_DATA7_MARK,
  3932. VI5_DATA8_MARK, VI5_DATA9_MARK,
  3933. VI5_DATA10_MARK, VI5_DATA11_MARK,
  3934. VI5_DATA12_MARK, VI5_DATA13_MARK,
  3935. VI5_DATA14_MARK, VI5_DATA15_MARK,
  3936. },
  3937. };
  3938. static const unsigned int vin5_sync_pins[] = {
  3939. /* HSYNC#, VSYNC# */
  3940. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
  3941. };
  3942. static const unsigned int vin5_sync_mux[] = {
  3943. VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
  3944. };
  3945. static const unsigned int vin5_field_pins[] = {
  3946. RCAR_GP_PIN(1, 11),
  3947. };
  3948. static const unsigned int vin5_field_mux[] = {
  3949. /* FIELD */
  3950. VI5_FIELD_MARK,
  3951. };
  3952. static const unsigned int vin5_clkenb_pins[] = {
  3953. RCAR_GP_PIN(1, 20),
  3954. };
  3955. static const unsigned int vin5_clkenb_mux[] = {
  3956. /* CLKENB */
  3957. VI5_CLKENB_MARK,
  3958. };
  3959. static const unsigned int vin5_clk_pins[] = {
  3960. RCAR_GP_PIN(1, 21),
  3961. };
  3962. static const unsigned int vin5_clk_mux[] = {
  3963. /* CLK */
  3964. VI5_CLK_MARK,
  3965. };
  3966. static const struct {
  3967. struct sh_pfc_pin_group common[322];
  3968. #if defined(CONFIG_PINCTRL_PFC_R8A7796)
  3969. struct sh_pfc_pin_group automotive[30];
  3970. #endif
  3971. } pinmux_groups = {
  3972. .common = {
  3973. SH_PFC_PIN_GROUP(audio_clk_a_a),
  3974. SH_PFC_PIN_GROUP(audio_clk_a_b),
  3975. SH_PFC_PIN_GROUP(audio_clk_a_c),
  3976. SH_PFC_PIN_GROUP(audio_clk_b_a),
  3977. SH_PFC_PIN_GROUP(audio_clk_b_b),
  3978. SH_PFC_PIN_GROUP(audio_clk_c_a),
  3979. SH_PFC_PIN_GROUP(audio_clk_c_b),
  3980. SH_PFC_PIN_GROUP(audio_clkout_a),
  3981. SH_PFC_PIN_GROUP(audio_clkout_b),
  3982. SH_PFC_PIN_GROUP(audio_clkout_c),
  3983. SH_PFC_PIN_GROUP(audio_clkout_d),
  3984. SH_PFC_PIN_GROUP(audio_clkout1_a),
  3985. SH_PFC_PIN_GROUP(audio_clkout1_b),
  3986. SH_PFC_PIN_GROUP(audio_clkout2_a),
  3987. SH_PFC_PIN_GROUP(audio_clkout2_b),
  3988. SH_PFC_PIN_GROUP(audio_clkout3_a),
  3989. SH_PFC_PIN_GROUP(audio_clkout3_b),
  3990. SH_PFC_PIN_GROUP(avb_link),
  3991. SH_PFC_PIN_GROUP(avb_magic),
  3992. SH_PFC_PIN_GROUP(avb_phy_int),
  3993. SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
  3994. SH_PFC_PIN_GROUP(avb_mdio),
  3995. SH_PFC_PIN_GROUP(avb_mii),
  3996. SH_PFC_PIN_GROUP(avb_avtp_pps),
  3997. SH_PFC_PIN_GROUP(avb_avtp_match_a),
  3998. SH_PFC_PIN_GROUP(avb_avtp_capture_a),
  3999. SH_PFC_PIN_GROUP(avb_avtp_match_b),
  4000. SH_PFC_PIN_GROUP(avb_avtp_capture_b),
  4001. SH_PFC_PIN_GROUP(can0_data_a),
  4002. SH_PFC_PIN_GROUP(can0_data_b),
  4003. SH_PFC_PIN_GROUP(can1_data),
  4004. SH_PFC_PIN_GROUP(can_clk),
  4005. SH_PFC_PIN_GROUP(canfd0_data_a),
  4006. SH_PFC_PIN_GROUP(canfd0_data_b),
  4007. SH_PFC_PIN_GROUP(canfd1_data),
  4008. SH_PFC_PIN_GROUP(du_rgb666),
  4009. SH_PFC_PIN_GROUP(du_rgb888),
  4010. SH_PFC_PIN_GROUP(du_clk_out_0),
  4011. SH_PFC_PIN_GROUP(du_clk_out_1),
  4012. SH_PFC_PIN_GROUP(du_sync),
  4013. SH_PFC_PIN_GROUP(du_oddf),
  4014. SH_PFC_PIN_GROUP(du_cde),
  4015. SH_PFC_PIN_GROUP(du_disp),
  4016. SH_PFC_PIN_GROUP(hscif0_data),
  4017. SH_PFC_PIN_GROUP(hscif0_clk),
  4018. SH_PFC_PIN_GROUP(hscif0_ctrl),
  4019. SH_PFC_PIN_GROUP(hscif1_data_a),
  4020. SH_PFC_PIN_GROUP(hscif1_clk_a),
  4021. SH_PFC_PIN_GROUP(hscif1_ctrl_a),
  4022. SH_PFC_PIN_GROUP(hscif1_data_b),
  4023. SH_PFC_PIN_GROUP(hscif1_clk_b),
  4024. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  4025. SH_PFC_PIN_GROUP(hscif2_data_a),
  4026. SH_PFC_PIN_GROUP(hscif2_clk_a),
  4027. SH_PFC_PIN_GROUP(hscif2_ctrl_a),
  4028. SH_PFC_PIN_GROUP(hscif2_data_b),
  4029. SH_PFC_PIN_GROUP(hscif2_clk_b),
  4030. SH_PFC_PIN_GROUP(hscif2_ctrl_b),
  4031. SH_PFC_PIN_GROUP(hscif2_data_c),
  4032. SH_PFC_PIN_GROUP(hscif2_clk_c),
  4033. SH_PFC_PIN_GROUP(hscif2_ctrl_c),
  4034. SH_PFC_PIN_GROUP(hscif3_data_a),
  4035. SH_PFC_PIN_GROUP(hscif3_clk),
  4036. SH_PFC_PIN_GROUP(hscif3_ctrl),
  4037. SH_PFC_PIN_GROUP(hscif3_data_b),
  4038. SH_PFC_PIN_GROUP(hscif3_data_c),
  4039. SH_PFC_PIN_GROUP(hscif3_data_d),
  4040. SH_PFC_PIN_GROUP(hscif4_data_a),
  4041. SH_PFC_PIN_GROUP(hscif4_clk),
  4042. SH_PFC_PIN_GROUP(hscif4_ctrl),
  4043. SH_PFC_PIN_GROUP(hscif4_data_b),
  4044. SH_PFC_PIN_GROUP(i2c0),
  4045. SH_PFC_PIN_GROUP(i2c1_a),
  4046. SH_PFC_PIN_GROUP(i2c1_b),
  4047. SH_PFC_PIN_GROUP(i2c2_a),
  4048. SH_PFC_PIN_GROUP(i2c2_b),
  4049. SH_PFC_PIN_GROUP(i2c3),
  4050. SH_PFC_PIN_GROUP(i2c5),
  4051. SH_PFC_PIN_GROUP(i2c6_a),
  4052. SH_PFC_PIN_GROUP(i2c6_b),
  4053. SH_PFC_PIN_GROUP(i2c6_c),
  4054. SH_PFC_PIN_GROUP(intc_ex_irq0),
  4055. SH_PFC_PIN_GROUP(intc_ex_irq1),
  4056. SH_PFC_PIN_GROUP(intc_ex_irq2),
  4057. SH_PFC_PIN_GROUP(intc_ex_irq3),
  4058. SH_PFC_PIN_GROUP(intc_ex_irq4),
  4059. SH_PFC_PIN_GROUP(intc_ex_irq5),
  4060. SH_PFC_PIN_GROUP(msiof0_clk),
  4061. SH_PFC_PIN_GROUP(msiof0_sync),
  4062. SH_PFC_PIN_GROUP(msiof0_ss1),
  4063. SH_PFC_PIN_GROUP(msiof0_ss2),
  4064. SH_PFC_PIN_GROUP(msiof0_txd),
  4065. SH_PFC_PIN_GROUP(msiof0_rxd),
  4066. SH_PFC_PIN_GROUP(msiof1_clk_a),
  4067. SH_PFC_PIN_GROUP(msiof1_sync_a),
  4068. SH_PFC_PIN_GROUP(msiof1_ss1_a),
  4069. SH_PFC_PIN_GROUP(msiof1_ss2_a),
  4070. SH_PFC_PIN_GROUP(msiof1_txd_a),
  4071. SH_PFC_PIN_GROUP(msiof1_rxd_a),
  4072. SH_PFC_PIN_GROUP(msiof1_clk_b),
  4073. SH_PFC_PIN_GROUP(msiof1_sync_b),
  4074. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  4075. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  4076. SH_PFC_PIN_GROUP(msiof1_txd_b),
  4077. SH_PFC_PIN_GROUP(msiof1_rxd_b),
  4078. SH_PFC_PIN_GROUP(msiof1_clk_c),
  4079. SH_PFC_PIN_GROUP(msiof1_sync_c),
  4080. SH_PFC_PIN_GROUP(msiof1_ss1_c),
  4081. SH_PFC_PIN_GROUP(msiof1_ss2_c),
  4082. SH_PFC_PIN_GROUP(msiof1_txd_c),
  4083. SH_PFC_PIN_GROUP(msiof1_rxd_c),
  4084. SH_PFC_PIN_GROUP(msiof1_clk_d),
  4085. SH_PFC_PIN_GROUP(msiof1_sync_d),
  4086. SH_PFC_PIN_GROUP(msiof1_ss1_d),
  4087. SH_PFC_PIN_GROUP(msiof1_ss2_d),
  4088. SH_PFC_PIN_GROUP(msiof1_txd_d),
  4089. SH_PFC_PIN_GROUP(msiof1_rxd_d),
  4090. SH_PFC_PIN_GROUP(msiof1_clk_e),
  4091. SH_PFC_PIN_GROUP(msiof1_sync_e),
  4092. SH_PFC_PIN_GROUP(msiof1_ss1_e),
  4093. SH_PFC_PIN_GROUP(msiof1_ss2_e),
  4094. SH_PFC_PIN_GROUP(msiof1_txd_e),
  4095. SH_PFC_PIN_GROUP(msiof1_rxd_e),
  4096. SH_PFC_PIN_GROUP(msiof1_clk_f),
  4097. SH_PFC_PIN_GROUP(msiof1_sync_f),
  4098. SH_PFC_PIN_GROUP(msiof1_ss1_f),
  4099. SH_PFC_PIN_GROUP(msiof1_ss2_f),
  4100. SH_PFC_PIN_GROUP(msiof1_txd_f),
  4101. SH_PFC_PIN_GROUP(msiof1_rxd_f),
  4102. SH_PFC_PIN_GROUP(msiof1_clk_g),
  4103. SH_PFC_PIN_GROUP(msiof1_sync_g),
  4104. SH_PFC_PIN_GROUP(msiof1_ss1_g),
  4105. SH_PFC_PIN_GROUP(msiof1_ss2_g),
  4106. SH_PFC_PIN_GROUP(msiof1_txd_g),
  4107. SH_PFC_PIN_GROUP(msiof1_rxd_g),
  4108. SH_PFC_PIN_GROUP(msiof2_clk_a),
  4109. SH_PFC_PIN_GROUP(msiof2_sync_a),
  4110. SH_PFC_PIN_GROUP(msiof2_ss1_a),
  4111. SH_PFC_PIN_GROUP(msiof2_ss2_a),
  4112. SH_PFC_PIN_GROUP(msiof2_txd_a),
  4113. SH_PFC_PIN_GROUP(msiof2_rxd_a),
  4114. SH_PFC_PIN_GROUP(msiof2_clk_b),
  4115. SH_PFC_PIN_GROUP(msiof2_sync_b),
  4116. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  4117. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  4118. SH_PFC_PIN_GROUP(msiof2_txd_b),
  4119. SH_PFC_PIN_GROUP(msiof2_rxd_b),
  4120. SH_PFC_PIN_GROUP(msiof2_clk_c),
  4121. SH_PFC_PIN_GROUP(msiof2_sync_c),
  4122. SH_PFC_PIN_GROUP(msiof2_ss1_c),
  4123. SH_PFC_PIN_GROUP(msiof2_ss2_c),
  4124. SH_PFC_PIN_GROUP(msiof2_txd_c),
  4125. SH_PFC_PIN_GROUP(msiof2_rxd_c),
  4126. SH_PFC_PIN_GROUP(msiof2_clk_d),
  4127. SH_PFC_PIN_GROUP(msiof2_sync_d),
  4128. SH_PFC_PIN_GROUP(msiof2_ss1_d),
  4129. SH_PFC_PIN_GROUP(msiof2_ss2_d),
  4130. SH_PFC_PIN_GROUP(msiof2_txd_d),
  4131. SH_PFC_PIN_GROUP(msiof2_rxd_d),
  4132. SH_PFC_PIN_GROUP(msiof3_clk_a),
  4133. SH_PFC_PIN_GROUP(msiof3_sync_a),
  4134. SH_PFC_PIN_GROUP(msiof3_ss1_a),
  4135. SH_PFC_PIN_GROUP(msiof3_ss2_a),
  4136. SH_PFC_PIN_GROUP(msiof3_txd_a),
  4137. SH_PFC_PIN_GROUP(msiof3_rxd_a),
  4138. SH_PFC_PIN_GROUP(msiof3_clk_b),
  4139. SH_PFC_PIN_GROUP(msiof3_sync_b),
  4140. SH_PFC_PIN_GROUP(msiof3_ss1_b),
  4141. SH_PFC_PIN_GROUP(msiof3_ss2_b),
  4142. SH_PFC_PIN_GROUP(msiof3_txd_b),
  4143. SH_PFC_PIN_GROUP(msiof3_rxd_b),
  4144. SH_PFC_PIN_GROUP(msiof3_clk_c),
  4145. SH_PFC_PIN_GROUP(msiof3_sync_c),
  4146. SH_PFC_PIN_GROUP(msiof3_txd_c),
  4147. SH_PFC_PIN_GROUP(msiof3_rxd_c),
  4148. SH_PFC_PIN_GROUP(msiof3_clk_d),
  4149. SH_PFC_PIN_GROUP(msiof3_sync_d),
  4150. SH_PFC_PIN_GROUP(msiof3_ss1_d),
  4151. SH_PFC_PIN_GROUP(msiof3_txd_d),
  4152. SH_PFC_PIN_GROUP(msiof3_rxd_d),
  4153. SH_PFC_PIN_GROUP(msiof3_clk_e),
  4154. SH_PFC_PIN_GROUP(msiof3_sync_e),
  4155. SH_PFC_PIN_GROUP(msiof3_ss1_e),
  4156. SH_PFC_PIN_GROUP(msiof3_ss2_e),
  4157. SH_PFC_PIN_GROUP(msiof3_txd_e),
  4158. SH_PFC_PIN_GROUP(msiof3_rxd_e),
  4159. SH_PFC_PIN_GROUP(pwm0),
  4160. SH_PFC_PIN_GROUP(pwm1_a),
  4161. SH_PFC_PIN_GROUP(pwm1_b),
  4162. SH_PFC_PIN_GROUP(pwm2_a),
  4163. SH_PFC_PIN_GROUP(pwm2_b),
  4164. SH_PFC_PIN_GROUP(pwm3_a),
  4165. SH_PFC_PIN_GROUP(pwm3_b),
  4166. SH_PFC_PIN_GROUP(pwm4_a),
  4167. SH_PFC_PIN_GROUP(pwm4_b),
  4168. SH_PFC_PIN_GROUP(pwm5_a),
  4169. SH_PFC_PIN_GROUP(pwm5_b),
  4170. SH_PFC_PIN_GROUP(pwm6_a),
  4171. SH_PFC_PIN_GROUP(pwm6_b),
  4172. SH_PFC_PIN_GROUP(qspi0_ctrl),
  4173. SH_PFC_PIN_GROUP(qspi0_data2),
  4174. SH_PFC_PIN_GROUP(qspi0_data4),
  4175. SH_PFC_PIN_GROUP(qspi1_ctrl),
  4176. SH_PFC_PIN_GROUP(qspi1_data2),
  4177. SH_PFC_PIN_GROUP(qspi1_data4),
  4178. SH_PFC_PIN_GROUP(scif0_data),
  4179. SH_PFC_PIN_GROUP(scif0_clk),
  4180. SH_PFC_PIN_GROUP(scif0_ctrl),
  4181. SH_PFC_PIN_GROUP(scif1_data_a),
  4182. SH_PFC_PIN_GROUP(scif1_clk),
  4183. SH_PFC_PIN_GROUP(scif1_ctrl),
  4184. SH_PFC_PIN_GROUP(scif1_data_b),
  4185. SH_PFC_PIN_GROUP(scif2_data_a),
  4186. SH_PFC_PIN_GROUP(scif2_clk),
  4187. SH_PFC_PIN_GROUP(scif2_data_b),
  4188. SH_PFC_PIN_GROUP(scif3_data_a),
  4189. SH_PFC_PIN_GROUP(scif3_clk),
  4190. SH_PFC_PIN_GROUP(scif3_ctrl),
  4191. SH_PFC_PIN_GROUP(scif3_data_b),
  4192. SH_PFC_PIN_GROUP(scif4_data_a),
  4193. SH_PFC_PIN_GROUP(scif4_clk_a),
  4194. SH_PFC_PIN_GROUP(scif4_ctrl_a),
  4195. SH_PFC_PIN_GROUP(scif4_data_b),
  4196. SH_PFC_PIN_GROUP(scif4_clk_b),
  4197. SH_PFC_PIN_GROUP(scif4_ctrl_b),
  4198. SH_PFC_PIN_GROUP(scif4_data_c),
  4199. SH_PFC_PIN_GROUP(scif4_clk_c),
  4200. SH_PFC_PIN_GROUP(scif4_ctrl_c),
  4201. SH_PFC_PIN_GROUP(scif5_data_a),
  4202. SH_PFC_PIN_GROUP(scif5_clk_a),
  4203. SH_PFC_PIN_GROUP(scif5_data_b),
  4204. SH_PFC_PIN_GROUP(scif5_clk_b),
  4205. SH_PFC_PIN_GROUP(scif_clk_a),
  4206. SH_PFC_PIN_GROUP(scif_clk_b),
  4207. SH_PFC_PIN_GROUP(sdhi0_data1),
  4208. SH_PFC_PIN_GROUP(sdhi0_data4),
  4209. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  4210. SH_PFC_PIN_GROUP(sdhi0_cd),
  4211. SH_PFC_PIN_GROUP(sdhi0_wp),
  4212. SH_PFC_PIN_GROUP(sdhi1_data1),
  4213. SH_PFC_PIN_GROUP(sdhi1_data4),
  4214. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  4215. SH_PFC_PIN_GROUP(sdhi1_cd),
  4216. SH_PFC_PIN_GROUP(sdhi1_wp),
  4217. SH_PFC_PIN_GROUP(sdhi2_data1),
  4218. SH_PFC_PIN_GROUP(sdhi2_data4),
  4219. SH_PFC_PIN_GROUP(sdhi2_data8),
  4220. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  4221. SH_PFC_PIN_GROUP(sdhi2_cd_a),
  4222. SH_PFC_PIN_GROUP(sdhi2_wp_a),
  4223. SH_PFC_PIN_GROUP(sdhi2_cd_b),
  4224. SH_PFC_PIN_GROUP(sdhi2_wp_b),
  4225. SH_PFC_PIN_GROUP(sdhi2_ds),
  4226. SH_PFC_PIN_GROUP(sdhi3_data1),
  4227. SH_PFC_PIN_GROUP(sdhi3_data4),
  4228. SH_PFC_PIN_GROUP(sdhi3_data8),
  4229. SH_PFC_PIN_GROUP(sdhi3_ctrl),
  4230. SH_PFC_PIN_GROUP(sdhi3_cd),
  4231. SH_PFC_PIN_GROUP(sdhi3_wp),
  4232. SH_PFC_PIN_GROUP(sdhi3_ds),
  4233. SH_PFC_PIN_GROUP(ssi0_data),
  4234. SH_PFC_PIN_GROUP(ssi01239_ctrl),
  4235. SH_PFC_PIN_GROUP(ssi1_data_a),
  4236. SH_PFC_PIN_GROUP(ssi1_data_b),
  4237. SH_PFC_PIN_GROUP(ssi1_ctrl_a),
  4238. SH_PFC_PIN_GROUP(ssi1_ctrl_b),
  4239. SH_PFC_PIN_GROUP(ssi2_data_a),
  4240. SH_PFC_PIN_GROUP(ssi2_data_b),
  4241. SH_PFC_PIN_GROUP(ssi2_ctrl_a),
  4242. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  4243. SH_PFC_PIN_GROUP(ssi3_data),
  4244. SH_PFC_PIN_GROUP(ssi349_ctrl),
  4245. SH_PFC_PIN_GROUP(ssi4_data),
  4246. SH_PFC_PIN_GROUP(ssi4_ctrl),
  4247. SH_PFC_PIN_GROUP(ssi5_data),
  4248. SH_PFC_PIN_GROUP(ssi5_ctrl),
  4249. SH_PFC_PIN_GROUP(ssi6_data),
  4250. SH_PFC_PIN_GROUP(ssi6_ctrl),
  4251. SH_PFC_PIN_GROUP(ssi7_data),
  4252. SH_PFC_PIN_GROUP(ssi78_ctrl),
  4253. SH_PFC_PIN_GROUP(ssi8_data),
  4254. SH_PFC_PIN_GROUP(ssi9_data_a),
  4255. SH_PFC_PIN_GROUP(ssi9_data_b),
  4256. SH_PFC_PIN_GROUP(ssi9_ctrl_a),
  4257. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  4258. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  4259. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  4260. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  4261. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  4262. SH_PFC_PIN_GROUP(tpu_to0),
  4263. SH_PFC_PIN_GROUP(tpu_to1),
  4264. SH_PFC_PIN_GROUP(tpu_to2),
  4265. SH_PFC_PIN_GROUP(tpu_to3),
  4266. SH_PFC_PIN_GROUP(usb0),
  4267. SH_PFC_PIN_GROUP(usb1),
  4268. SH_PFC_PIN_GROUP(usb30),
  4269. VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
  4270. VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
  4271. VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
  4272. VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
  4273. SH_PFC_PIN_GROUP(vin4_data18_a),
  4274. VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
  4275. VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
  4276. VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
  4277. VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
  4278. VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
  4279. VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
  4280. SH_PFC_PIN_GROUP(vin4_data18_b),
  4281. VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
  4282. VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
  4283. SH_PFC_PIN_GROUP(vin4_sync),
  4284. SH_PFC_PIN_GROUP(vin4_field),
  4285. SH_PFC_PIN_GROUP(vin4_clkenb),
  4286. SH_PFC_PIN_GROUP(vin4_clk),
  4287. VIN_DATA_PIN_GROUP(vin5_data, 8),
  4288. VIN_DATA_PIN_GROUP(vin5_data, 10),
  4289. VIN_DATA_PIN_GROUP(vin5_data, 12),
  4290. VIN_DATA_PIN_GROUP(vin5_data, 16),
  4291. SH_PFC_PIN_GROUP(vin5_sync),
  4292. SH_PFC_PIN_GROUP(vin5_field),
  4293. SH_PFC_PIN_GROUP(vin5_clkenb),
  4294. SH_PFC_PIN_GROUP(vin5_clk),
  4295. },
  4296. #if defined(CONFIG_PINCTRL_PFC_R8A7796)
  4297. .automotive = {
  4298. SH_PFC_PIN_GROUP(drif0_ctrl_a),
  4299. SH_PFC_PIN_GROUP(drif0_data0_a),
  4300. SH_PFC_PIN_GROUP(drif0_data1_a),
  4301. SH_PFC_PIN_GROUP(drif0_ctrl_b),
  4302. SH_PFC_PIN_GROUP(drif0_data0_b),
  4303. SH_PFC_PIN_GROUP(drif0_data1_b),
  4304. SH_PFC_PIN_GROUP(drif0_ctrl_c),
  4305. SH_PFC_PIN_GROUP(drif0_data0_c),
  4306. SH_PFC_PIN_GROUP(drif0_data1_c),
  4307. SH_PFC_PIN_GROUP(drif1_ctrl_a),
  4308. SH_PFC_PIN_GROUP(drif1_data0_a),
  4309. SH_PFC_PIN_GROUP(drif1_data1_a),
  4310. SH_PFC_PIN_GROUP(drif1_ctrl_b),
  4311. SH_PFC_PIN_GROUP(drif1_data0_b),
  4312. SH_PFC_PIN_GROUP(drif1_data1_b),
  4313. SH_PFC_PIN_GROUP(drif1_ctrl_c),
  4314. SH_PFC_PIN_GROUP(drif1_data0_c),
  4315. SH_PFC_PIN_GROUP(drif1_data1_c),
  4316. SH_PFC_PIN_GROUP(drif2_ctrl_a),
  4317. SH_PFC_PIN_GROUP(drif2_data0_a),
  4318. SH_PFC_PIN_GROUP(drif2_data1_a),
  4319. SH_PFC_PIN_GROUP(drif2_ctrl_b),
  4320. SH_PFC_PIN_GROUP(drif2_data0_b),
  4321. SH_PFC_PIN_GROUP(drif2_data1_b),
  4322. SH_PFC_PIN_GROUP(drif3_ctrl_a),
  4323. SH_PFC_PIN_GROUP(drif3_data0_a),
  4324. SH_PFC_PIN_GROUP(drif3_data1_a),
  4325. SH_PFC_PIN_GROUP(drif3_ctrl_b),
  4326. SH_PFC_PIN_GROUP(drif3_data0_b),
  4327. SH_PFC_PIN_GROUP(drif3_data1_b),
  4328. }
  4329. #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
  4330. };
  4331. static const char * const audio_clk_groups[] = {
  4332. "audio_clk_a_a",
  4333. "audio_clk_a_b",
  4334. "audio_clk_a_c",
  4335. "audio_clk_b_a",
  4336. "audio_clk_b_b",
  4337. "audio_clk_c_a",
  4338. "audio_clk_c_b",
  4339. "audio_clkout_a",
  4340. "audio_clkout_b",
  4341. "audio_clkout_c",
  4342. "audio_clkout_d",
  4343. "audio_clkout1_a",
  4344. "audio_clkout1_b",
  4345. "audio_clkout2_a",
  4346. "audio_clkout2_b",
  4347. "audio_clkout3_a",
  4348. "audio_clkout3_b",
  4349. };
  4350. static const char * const avb_groups[] = {
  4351. "avb_link",
  4352. "avb_magic",
  4353. "avb_phy_int",
  4354. "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
  4355. "avb_mdio",
  4356. "avb_mii",
  4357. "avb_avtp_pps",
  4358. "avb_avtp_match_a",
  4359. "avb_avtp_capture_a",
  4360. "avb_avtp_match_b",
  4361. "avb_avtp_capture_b",
  4362. };
  4363. static const char * const can0_groups[] = {
  4364. "can0_data_a",
  4365. "can0_data_b",
  4366. };
  4367. static const char * const can1_groups[] = {
  4368. "can1_data",
  4369. };
  4370. static const char * const can_clk_groups[] = {
  4371. "can_clk",
  4372. };
  4373. static const char * const canfd0_groups[] = {
  4374. "canfd0_data_a",
  4375. "canfd0_data_b",
  4376. };
  4377. static const char * const canfd1_groups[] = {
  4378. "canfd1_data",
  4379. };
  4380. #if defined(CONFIG_PINCTRL_PFC_R8A7796)
  4381. static const char * const drif0_groups[] = {
  4382. "drif0_ctrl_a",
  4383. "drif0_data0_a",
  4384. "drif0_data1_a",
  4385. "drif0_ctrl_b",
  4386. "drif0_data0_b",
  4387. "drif0_data1_b",
  4388. "drif0_ctrl_c",
  4389. "drif0_data0_c",
  4390. "drif0_data1_c",
  4391. };
  4392. static const char * const drif1_groups[] = {
  4393. "drif1_ctrl_a",
  4394. "drif1_data0_a",
  4395. "drif1_data1_a",
  4396. "drif1_ctrl_b",
  4397. "drif1_data0_b",
  4398. "drif1_data1_b",
  4399. "drif1_ctrl_c",
  4400. "drif1_data0_c",
  4401. "drif1_data1_c",
  4402. };
  4403. static const char * const drif2_groups[] = {
  4404. "drif2_ctrl_a",
  4405. "drif2_data0_a",
  4406. "drif2_data1_a",
  4407. "drif2_ctrl_b",
  4408. "drif2_data0_b",
  4409. "drif2_data1_b",
  4410. };
  4411. static const char * const drif3_groups[] = {
  4412. "drif3_ctrl_a",
  4413. "drif3_data0_a",
  4414. "drif3_data1_a",
  4415. "drif3_ctrl_b",
  4416. "drif3_data0_b",
  4417. "drif3_data1_b",
  4418. };
  4419. #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
  4420. static const char * const du_groups[] = {
  4421. "du_rgb666",
  4422. "du_rgb888",
  4423. "du_clk_out_0",
  4424. "du_clk_out_1",
  4425. "du_sync",
  4426. "du_oddf",
  4427. "du_cde",
  4428. "du_disp",
  4429. };
  4430. static const char * const hscif0_groups[] = {
  4431. "hscif0_data",
  4432. "hscif0_clk",
  4433. "hscif0_ctrl",
  4434. };
  4435. static const char * const hscif1_groups[] = {
  4436. "hscif1_data_a",
  4437. "hscif1_clk_a",
  4438. "hscif1_ctrl_a",
  4439. "hscif1_data_b",
  4440. "hscif1_clk_b",
  4441. "hscif1_ctrl_b",
  4442. };
  4443. static const char * const hscif2_groups[] = {
  4444. "hscif2_data_a",
  4445. "hscif2_clk_a",
  4446. "hscif2_ctrl_a",
  4447. "hscif2_data_b",
  4448. "hscif2_clk_b",
  4449. "hscif2_ctrl_b",
  4450. "hscif2_data_c",
  4451. "hscif2_clk_c",
  4452. "hscif2_ctrl_c",
  4453. };
  4454. static const char * const hscif3_groups[] = {
  4455. "hscif3_data_a",
  4456. "hscif3_clk",
  4457. "hscif3_ctrl",
  4458. "hscif3_data_b",
  4459. "hscif3_data_c",
  4460. "hscif3_data_d",
  4461. };
  4462. static const char * const hscif4_groups[] = {
  4463. "hscif4_data_a",
  4464. "hscif4_clk",
  4465. "hscif4_ctrl",
  4466. "hscif4_data_b",
  4467. };
  4468. static const char * const i2c0_groups[] = {
  4469. "i2c0",
  4470. };
  4471. static const char * const i2c1_groups[] = {
  4472. "i2c1_a",
  4473. "i2c1_b",
  4474. };
  4475. static const char * const i2c2_groups[] = {
  4476. "i2c2_a",
  4477. "i2c2_b",
  4478. };
  4479. static const char * const i2c3_groups[] = {
  4480. "i2c3",
  4481. };
  4482. static const char * const i2c5_groups[] = {
  4483. "i2c5",
  4484. };
  4485. static const char * const i2c6_groups[] = {
  4486. "i2c6_a",
  4487. "i2c6_b",
  4488. "i2c6_c",
  4489. };
  4490. static const char * const intc_ex_groups[] = {
  4491. "intc_ex_irq0",
  4492. "intc_ex_irq1",
  4493. "intc_ex_irq2",
  4494. "intc_ex_irq3",
  4495. "intc_ex_irq4",
  4496. "intc_ex_irq5",
  4497. };
  4498. static const char * const msiof0_groups[] = {
  4499. "msiof0_clk",
  4500. "msiof0_sync",
  4501. "msiof0_ss1",
  4502. "msiof0_ss2",
  4503. "msiof0_txd",
  4504. "msiof0_rxd",
  4505. };
  4506. static const char * const msiof1_groups[] = {
  4507. "msiof1_clk_a",
  4508. "msiof1_sync_a",
  4509. "msiof1_ss1_a",
  4510. "msiof1_ss2_a",
  4511. "msiof1_txd_a",
  4512. "msiof1_rxd_a",
  4513. "msiof1_clk_b",
  4514. "msiof1_sync_b",
  4515. "msiof1_ss1_b",
  4516. "msiof1_ss2_b",
  4517. "msiof1_txd_b",
  4518. "msiof1_rxd_b",
  4519. "msiof1_clk_c",
  4520. "msiof1_sync_c",
  4521. "msiof1_ss1_c",
  4522. "msiof1_ss2_c",
  4523. "msiof1_txd_c",
  4524. "msiof1_rxd_c",
  4525. "msiof1_clk_d",
  4526. "msiof1_sync_d",
  4527. "msiof1_ss1_d",
  4528. "msiof1_ss2_d",
  4529. "msiof1_txd_d",
  4530. "msiof1_rxd_d",
  4531. "msiof1_clk_e",
  4532. "msiof1_sync_e",
  4533. "msiof1_ss1_e",
  4534. "msiof1_ss2_e",
  4535. "msiof1_txd_e",
  4536. "msiof1_rxd_e",
  4537. "msiof1_clk_f",
  4538. "msiof1_sync_f",
  4539. "msiof1_ss1_f",
  4540. "msiof1_ss2_f",
  4541. "msiof1_txd_f",
  4542. "msiof1_rxd_f",
  4543. "msiof1_clk_g",
  4544. "msiof1_sync_g",
  4545. "msiof1_ss1_g",
  4546. "msiof1_ss2_g",
  4547. "msiof1_txd_g",
  4548. "msiof1_rxd_g",
  4549. };
  4550. static const char * const msiof2_groups[] = {
  4551. "msiof2_clk_a",
  4552. "msiof2_sync_a",
  4553. "msiof2_ss1_a",
  4554. "msiof2_ss2_a",
  4555. "msiof2_txd_a",
  4556. "msiof2_rxd_a",
  4557. "msiof2_clk_b",
  4558. "msiof2_sync_b",
  4559. "msiof2_ss1_b",
  4560. "msiof2_ss2_b",
  4561. "msiof2_txd_b",
  4562. "msiof2_rxd_b",
  4563. "msiof2_clk_c",
  4564. "msiof2_sync_c",
  4565. "msiof2_ss1_c",
  4566. "msiof2_ss2_c",
  4567. "msiof2_txd_c",
  4568. "msiof2_rxd_c",
  4569. "msiof2_clk_d",
  4570. "msiof2_sync_d",
  4571. "msiof2_ss1_d",
  4572. "msiof2_ss2_d",
  4573. "msiof2_txd_d",
  4574. "msiof2_rxd_d",
  4575. };
  4576. static const char * const msiof3_groups[] = {
  4577. "msiof3_clk_a",
  4578. "msiof3_sync_a",
  4579. "msiof3_ss1_a",
  4580. "msiof3_ss2_a",
  4581. "msiof3_txd_a",
  4582. "msiof3_rxd_a",
  4583. "msiof3_clk_b",
  4584. "msiof3_sync_b",
  4585. "msiof3_ss1_b",
  4586. "msiof3_ss2_b",
  4587. "msiof3_txd_b",
  4588. "msiof3_rxd_b",
  4589. "msiof3_clk_c",
  4590. "msiof3_sync_c",
  4591. "msiof3_txd_c",
  4592. "msiof3_rxd_c",
  4593. "msiof3_clk_d",
  4594. "msiof3_sync_d",
  4595. "msiof3_ss1_d",
  4596. "msiof3_txd_d",
  4597. "msiof3_rxd_d",
  4598. "msiof3_clk_e",
  4599. "msiof3_sync_e",
  4600. "msiof3_ss1_e",
  4601. "msiof3_ss2_e",
  4602. "msiof3_txd_e",
  4603. "msiof3_rxd_e",
  4604. };
  4605. static const char * const pwm0_groups[] = {
  4606. "pwm0",
  4607. };
  4608. static const char * const pwm1_groups[] = {
  4609. "pwm1_a",
  4610. "pwm1_b",
  4611. };
  4612. static const char * const pwm2_groups[] = {
  4613. "pwm2_a",
  4614. "pwm2_b",
  4615. };
  4616. static const char * const pwm3_groups[] = {
  4617. "pwm3_a",
  4618. "pwm3_b",
  4619. };
  4620. static const char * const pwm4_groups[] = {
  4621. "pwm4_a",
  4622. "pwm4_b",
  4623. };
  4624. static const char * const pwm5_groups[] = {
  4625. "pwm5_a",
  4626. "pwm5_b",
  4627. };
  4628. static const char * const pwm6_groups[] = {
  4629. "pwm6_a",
  4630. "pwm6_b",
  4631. };
  4632. static const char * const qspi0_groups[] = {
  4633. "qspi0_ctrl",
  4634. "qspi0_data2",
  4635. "qspi0_data4",
  4636. };
  4637. static const char * const qspi1_groups[] = {
  4638. "qspi1_ctrl",
  4639. "qspi1_data2",
  4640. "qspi1_data4",
  4641. };
  4642. static const char * const scif0_groups[] = {
  4643. "scif0_data",
  4644. "scif0_clk",
  4645. "scif0_ctrl",
  4646. };
  4647. static const char * const scif1_groups[] = {
  4648. "scif1_data_a",
  4649. "scif1_clk",
  4650. "scif1_ctrl",
  4651. "scif1_data_b",
  4652. };
  4653. static const char * const scif2_groups[] = {
  4654. "scif2_data_a",
  4655. "scif2_clk",
  4656. "scif2_data_b",
  4657. };
  4658. static const char * const scif3_groups[] = {
  4659. "scif3_data_a",
  4660. "scif3_clk",
  4661. "scif3_ctrl",
  4662. "scif3_data_b",
  4663. };
  4664. static const char * const scif4_groups[] = {
  4665. "scif4_data_a",
  4666. "scif4_clk_a",
  4667. "scif4_ctrl_a",
  4668. "scif4_data_b",
  4669. "scif4_clk_b",
  4670. "scif4_ctrl_b",
  4671. "scif4_data_c",
  4672. "scif4_clk_c",
  4673. "scif4_ctrl_c",
  4674. };
  4675. static const char * const scif5_groups[] = {
  4676. "scif5_data_a",
  4677. "scif5_clk_a",
  4678. "scif5_data_b",
  4679. "scif5_clk_b",
  4680. };
  4681. static const char * const scif_clk_groups[] = {
  4682. "scif_clk_a",
  4683. "scif_clk_b",
  4684. };
  4685. static const char * const sdhi0_groups[] = {
  4686. "sdhi0_data1",
  4687. "sdhi0_data4",
  4688. "sdhi0_ctrl",
  4689. "sdhi0_cd",
  4690. "sdhi0_wp",
  4691. };
  4692. static const char * const sdhi1_groups[] = {
  4693. "sdhi1_data1",
  4694. "sdhi1_data4",
  4695. "sdhi1_ctrl",
  4696. "sdhi1_cd",
  4697. "sdhi1_wp",
  4698. };
  4699. static const char * const sdhi2_groups[] = {
  4700. "sdhi2_data1",
  4701. "sdhi2_data4",
  4702. "sdhi2_data8",
  4703. "sdhi2_ctrl",
  4704. "sdhi2_cd_a",
  4705. "sdhi2_wp_a",
  4706. "sdhi2_cd_b",
  4707. "sdhi2_wp_b",
  4708. "sdhi2_ds",
  4709. };
  4710. static const char * const sdhi3_groups[] = {
  4711. "sdhi3_data1",
  4712. "sdhi3_data4",
  4713. "sdhi3_data8",
  4714. "sdhi3_ctrl",
  4715. "sdhi3_cd",
  4716. "sdhi3_wp",
  4717. "sdhi3_ds",
  4718. };
  4719. static const char * const ssi_groups[] = {
  4720. "ssi0_data",
  4721. "ssi01239_ctrl",
  4722. "ssi1_data_a",
  4723. "ssi1_data_b",
  4724. "ssi1_ctrl_a",
  4725. "ssi1_ctrl_b",
  4726. "ssi2_data_a",
  4727. "ssi2_data_b",
  4728. "ssi2_ctrl_a",
  4729. "ssi2_ctrl_b",
  4730. "ssi3_data",
  4731. "ssi349_ctrl",
  4732. "ssi4_data",
  4733. "ssi4_ctrl",
  4734. "ssi5_data",
  4735. "ssi5_ctrl",
  4736. "ssi6_data",
  4737. "ssi6_ctrl",
  4738. "ssi7_data",
  4739. "ssi78_ctrl",
  4740. "ssi8_data",
  4741. "ssi9_data_a",
  4742. "ssi9_data_b",
  4743. "ssi9_ctrl_a",
  4744. "ssi9_ctrl_b",
  4745. };
  4746. static const char * const tmu_groups[] = {
  4747. "tmu_tclk1_a",
  4748. "tmu_tclk1_b",
  4749. "tmu_tclk2_a",
  4750. "tmu_tclk2_b",
  4751. };
  4752. static const char * const tpu_groups[] = {
  4753. "tpu_to0",
  4754. "tpu_to1",
  4755. "tpu_to2",
  4756. "tpu_to3",
  4757. };
  4758. static const char * const usb0_groups[] = {
  4759. "usb0",
  4760. };
  4761. static const char * const usb1_groups[] = {
  4762. "usb1",
  4763. };
  4764. static const char * const usb30_groups[] = {
  4765. "usb30",
  4766. };
  4767. static const char * const vin4_groups[] = {
  4768. "vin4_data8_a",
  4769. "vin4_data10_a",
  4770. "vin4_data12_a",
  4771. "vin4_data16_a",
  4772. "vin4_data18_a",
  4773. "vin4_data20_a",
  4774. "vin4_data24_a",
  4775. "vin4_data8_b",
  4776. "vin4_data10_b",
  4777. "vin4_data12_b",
  4778. "vin4_data16_b",
  4779. "vin4_data18_b",
  4780. "vin4_data20_b",
  4781. "vin4_data24_b",
  4782. "vin4_sync",
  4783. "vin4_field",
  4784. "vin4_clkenb",
  4785. "vin4_clk",
  4786. };
  4787. static const char * const vin5_groups[] = {
  4788. "vin5_data8",
  4789. "vin5_data10",
  4790. "vin5_data12",
  4791. "vin5_data16",
  4792. "vin5_sync",
  4793. "vin5_field",
  4794. "vin5_clkenb",
  4795. "vin5_clk",
  4796. };
  4797. static const struct {
  4798. struct sh_pfc_function common[52];
  4799. #if defined(CONFIG_PINCTRL_PFC_R8A7796)
  4800. struct sh_pfc_function automotive[4];
  4801. #endif
  4802. } pinmux_functions = {
  4803. .common = {
  4804. SH_PFC_FUNCTION(audio_clk),
  4805. SH_PFC_FUNCTION(avb),
  4806. SH_PFC_FUNCTION(can0),
  4807. SH_PFC_FUNCTION(can1),
  4808. SH_PFC_FUNCTION(can_clk),
  4809. SH_PFC_FUNCTION(canfd0),
  4810. SH_PFC_FUNCTION(canfd1),
  4811. SH_PFC_FUNCTION(du),
  4812. SH_PFC_FUNCTION(hscif0),
  4813. SH_PFC_FUNCTION(hscif1),
  4814. SH_PFC_FUNCTION(hscif2),
  4815. SH_PFC_FUNCTION(hscif3),
  4816. SH_PFC_FUNCTION(hscif4),
  4817. SH_PFC_FUNCTION(i2c0),
  4818. SH_PFC_FUNCTION(i2c1),
  4819. SH_PFC_FUNCTION(i2c2),
  4820. SH_PFC_FUNCTION(i2c3),
  4821. SH_PFC_FUNCTION(i2c5),
  4822. SH_PFC_FUNCTION(i2c6),
  4823. SH_PFC_FUNCTION(intc_ex),
  4824. SH_PFC_FUNCTION(msiof0),
  4825. SH_PFC_FUNCTION(msiof1),
  4826. SH_PFC_FUNCTION(msiof2),
  4827. SH_PFC_FUNCTION(msiof3),
  4828. SH_PFC_FUNCTION(pwm0),
  4829. SH_PFC_FUNCTION(pwm1),
  4830. SH_PFC_FUNCTION(pwm2),
  4831. SH_PFC_FUNCTION(pwm3),
  4832. SH_PFC_FUNCTION(pwm4),
  4833. SH_PFC_FUNCTION(pwm5),
  4834. SH_PFC_FUNCTION(pwm6),
  4835. SH_PFC_FUNCTION(qspi0),
  4836. SH_PFC_FUNCTION(qspi1),
  4837. SH_PFC_FUNCTION(scif0),
  4838. SH_PFC_FUNCTION(scif1),
  4839. SH_PFC_FUNCTION(scif2),
  4840. SH_PFC_FUNCTION(scif3),
  4841. SH_PFC_FUNCTION(scif4),
  4842. SH_PFC_FUNCTION(scif5),
  4843. SH_PFC_FUNCTION(scif_clk),
  4844. SH_PFC_FUNCTION(sdhi0),
  4845. SH_PFC_FUNCTION(sdhi1),
  4846. SH_PFC_FUNCTION(sdhi2),
  4847. SH_PFC_FUNCTION(sdhi3),
  4848. SH_PFC_FUNCTION(ssi),
  4849. SH_PFC_FUNCTION(tmu),
  4850. SH_PFC_FUNCTION(tpu),
  4851. SH_PFC_FUNCTION(usb0),
  4852. SH_PFC_FUNCTION(usb1),
  4853. SH_PFC_FUNCTION(usb30),
  4854. SH_PFC_FUNCTION(vin4),
  4855. SH_PFC_FUNCTION(vin5),
  4856. },
  4857. #if defined(CONFIG_PINCTRL_PFC_R8A7796)
  4858. .automotive = {
  4859. SH_PFC_FUNCTION(drif0),
  4860. SH_PFC_FUNCTION(drif1),
  4861. SH_PFC_FUNCTION(drif2),
  4862. SH_PFC_FUNCTION(drif3),
  4863. }
  4864. #endif /* CONFIG_PINCTRL_PFC_R8A7796 */
  4865. };
  4866. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4867. #define F_(x, y) FN_##y
  4868. #define FM(x) FN_##x
  4869. { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
  4870. 0, 0,
  4871. 0, 0,
  4872. 0, 0,
  4873. 0, 0,
  4874. 0, 0,
  4875. 0, 0,
  4876. 0, 0,
  4877. 0, 0,
  4878. 0, 0,
  4879. 0, 0,
  4880. 0, 0,
  4881. 0, 0,
  4882. 0, 0,
  4883. 0, 0,
  4884. 0, 0,
  4885. 0, 0,
  4886. GP_0_15_FN, GPSR0_15,
  4887. GP_0_14_FN, GPSR0_14,
  4888. GP_0_13_FN, GPSR0_13,
  4889. GP_0_12_FN, GPSR0_12,
  4890. GP_0_11_FN, GPSR0_11,
  4891. GP_0_10_FN, GPSR0_10,
  4892. GP_0_9_FN, GPSR0_9,
  4893. GP_0_8_FN, GPSR0_8,
  4894. GP_0_7_FN, GPSR0_7,
  4895. GP_0_6_FN, GPSR0_6,
  4896. GP_0_5_FN, GPSR0_5,
  4897. GP_0_4_FN, GPSR0_4,
  4898. GP_0_3_FN, GPSR0_3,
  4899. GP_0_2_FN, GPSR0_2,
  4900. GP_0_1_FN, GPSR0_1,
  4901. GP_0_0_FN, GPSR0_0, ))
  4902. },
  4903. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  4904. 0, 0,
  4905. 0, 0,
  4906. 0, 0,
  4907. GP_1_28_FN, GPSR1_28,
  4908. GP_1_27_FN, GPSR1_27,
  4909. GP_1_26_FN, GPSR1_26,
  4910. GP_1_25_FN, GPSR1_25,
  4911. GP_1_24_FN, GPSR1_24,
  4912. GP_1_23_FN, GPSR1_23,
  4913. GP_1_22_FN, GPSR1_22,
  4914. GP_1_21_FN, GPSR1_21,
  4915. GP_1_20_FN, GPSR1_20,
  4916. GP_1_19_FN, GPSR1_19,
  4917. GP_1_18_FN, GPSR1_18,
  4918. GP_1_17_FN, GPSR1_17,
  4919. GP_1_16_FN, GPSR1_16,
  4920. GP_1_15_FN, GPSR1_15,
  4921. GP_1_14_FN, GPSR1_14,
  4922. GP_1_13_FN, GPSR1_13,
  4923. GP_1_12_FN, GPSR1_12,
  4924. GP_1_11_FN, GPSR1_11,
  4925. GP_1_10_FN, GPSR1_10,
  4926. GP_1_9_FN, GPSR1_9,
  4927. GP_1_8_FN, GPSR1_8,
  4928. GP_1_7_FN, GPSR1_7,
  4929. GP_1_6_FN, GPSR1_6,
  4930. GP_1_5_FN, GPSR1_5,
  4931. GP_1_4_FN, GPSR1_4,
  4932. GP_1_3_FN, GPSR1_3,
  4933. GP_1_2_FN, GPSR1_2,
  4934. GP_1_1_FN, GPSR1_1,
  4935. GP_1_0_FN, GPSR1_0, ))
  4936. },
  4937. { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
  4938. 0, 0,
  4939. 0, 0,
  4940. 0, 0,
  4941. 0, 0,
  4942. 0, 0,
  4943. 0, 0,
  4944. 0, 0,
  4945. 0, 0,
  4946. 0, 0,
  4947. 0, 0,
  4948. 0, 0,
  4949. 0, 0,
  4950. 0, 0,
  4951. 0, 0,
  4952. 0, 0,
  4953. 0, 0,
  4954. 0, 0,
  4955. GP_2_14_FN, GPSR2_14,
  4956. GP_2_13_FN, GPSR2_13,
  4957. GP_2_12_FN, GPSR2_12,
  4958. GP_2_11_FN, GPSR2_11,
  4959. GP_2_10_FN, GPSR2_10,
  4960. GP_2_9_FN, GPSR2_9,
  4961. GP_2_8_FN, GPSR2_8,
  4962. GP_2_7_FN, GPSR2_7,
  4963. GP_2_6_FN, GPSR2_6,
  4964. GP_2_5_FN, GPSR2_5,
  4965. GP_2_4_FN, GPSR2_4,
  4966. GP_2_3_FN, GPSR2_3,
  4967. GP_2_2_FN, GPSR2_2,
  4968. GP_2_1_FN, GPSR2_1,
  4969. GP_2_0_FN, GPSR2_0, ))
  4970. },
  4971. { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
  4972. 0, 0,
  4973. 0, 0,
  4974. 0, 0,
  4975. 0, 0,
  4976. 0, 0,
  4977. 0, 0,
  4978. 0, 0,
  4979. 0, 0,
  4980. 0, 0,
  4981. 0, 0,
  4982. 0, 0,
  4983. 0, 0,
  4984. 0, 0,
  4985. 0, 0,
  4986. 0, 0,
  4987. 0, 0,
  4988. GP_3_15_FN, GPSR3_15,
  4989. GP_3_14_FN, GPSR3_14,
  4990. GP_3_13_FN, GPSR3_13,
  4991. GP_3_12_FN, GPSR3_12,
  4992. GP_3_11_FN, GPSR3_11,
  4993. GP_3_10_FN, GPSR3_10,
  4994. GP_3_9_FN, GPSR3_9,
  4995. GP_3_8_FN, GPSR3_8,
  4996. GP_3_7_FN, GPSR3_7,
  4997. GP_3_6_FN, GPSR3_6,
  4998. GP_3_5_FN, GPSR3_5,
  4999. GP_3_4_FN, GPSR3_4,
  5000. GP_3_3_FN, GPSR3_3,
  5001. GP_3_2_FN, GPSR3_2,
  5002. GP_3_1_FN, GPSR3_1,
  5003. GP_3_0_FN, GPSR3_0, ))
  5004. },
  5005. { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
  5006. 0, 0,
  5007. 0, 0,
  5008. 0, 0,
  5009. 0, 0,
  5010. 0, 0,
  5011. 0, 0,
  5012. 0, 0,
  5013. 0, 0,
  5014. 0, 0,
  5015. 0, 0,
  5016. 0, 0,
  5017. 0, 0,
  5018. 0, 0,
  5019. 0, 0,
  5020. GP_4_17_FN, GPSR4_17,
  5021. GP_4_16_FN, GPSR4_16,
  5022. GP_4_15_FN, GPSR4_15,
  5023. GP_4_14_FN, GPSR4_14,
  5024. GP_4_13_FN, GPSR4_13,
  5025. GP_4_12_FN, GPSR4_12,
  5026. GP_4_11_FN, GPSR4_11,
  5027. GP_4_10_FN, GPSR4_10,
  5028. GP_4_9_FN, GPSR4_9,
  5029. GP_4_8_FN, GPSR4_8,
  5030. GP_4_7_FN, GPSR4_7,
  5031. GP_4_6_FN, GPSR4_6,
  5032. GP_4_5_FN, GPSR4_5,
  5033. GP_4_4_FN, GPSR4_4,
  5034. GP_4_3_FN, GPSR4_3,
  5035. GP_4_2_FN, GPSR4_2,
  5036. GP_4_1_FN, GPSR4_1,
  5037. GP_4_0_FN, GPSR4_0, ))
  5038. },
  5039. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  5040. 0, 0,
  5041. 0, 0,
  5042. 0, 0,
  5043. 0, 0,
  5044. 0, 0,
  5045. 0, 0,
  5046. GP_5_25_FN, GPSR5_25,
  5047. GP_5_24_FN, GPSR5_24,
  5048. GP_5_23_FN, GPSR5_23,
  5049. GP_5_22_FN, GPSR5_22,
  5050. GP_5_21_FN, GPSR5_21,
  5051. GP_5_20_FN, GPSR5_20,
  5052. GP_5_19_FN, GPSR5_19,
  5053. GP_5_18_FN, GPSR5_18,
  5054. GP_5_17_FN, GPSR5_17,
  5055. GP_5_16_FN, GPSR5_16,
  5056. GP_5_15_FN, GPSR5_15,
  5057. GP_5_14_FN, GPSR5_14,
  5058. GP_5_13_FN, GPSR5_13,
  5059. GP_5_12_FN, GPSR5_12,
  5060. GP_5_11_FN, GPSR5_11,
  5061. GP_5_10_FN, GPSR5_10,
  5062. GP_5_9_FN, GPSR5_9,
  5063. GP_5_8_FN, GPSR5_8,
  5064. GP_5_7_FN, GPSR5_7,
  5065. GP_5_6_FN, GPSR5_6,
  5066. GP_5_5_FN, GPSR5_5,
  5067. GP_5_4_FN, GPSR5_4,
  5068. GP_5_3_FN, GPSR5_3,
  5069. GP_5_2_FN, GPSR5_2,
  5070. GP_5_1_FN, GPSR5_1,
  5071. GP_5_0_FN, GPSR5_0, ))
  5072. },
  5073. { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
  5074. GP_6_31_FN, GPSR6_31,
  5075. GP_6_30_FN, GPSR6_30,
  5076. GP_6_29_FN, GPSR6_29,
  5077. GP_6_28_FN, GPSR6_28,
  5078. GP_6_27_FN, GPSR6_27,
  5079. GP_6_26_FN, GPSR6_26,
  5080. GP_6_25_FN, GPSR6_25,
  5081. GP_6_24_FN, GPSR6_24,
  5082. GP_6_23_FN, GPSR6_23,
  5083. GP_6_22_FN, GPSR6_22,
  5084. GP_6_21_FN, GPSR6_21,
  5085. GP_6_20_FN, GPSR6_20,
  5086. GP_6_19_FN, GPSR6_19,
  5087. GP_6_18_FN, GPSR6_18,
  5088. GP_6_17_FN, GPSR6_17,
  5089. GP_6_16_FN, GPSR6_16,
  5090. GP_6_15_FN, GPSR6_15,
  5091. GP_6_14_FN, GPSR6_14,
  5092. GP_6_13_FN, GPSR6_13,
  5093. GP_6_12_FN, GPSR6_12,
  5094. GP_6_11_FN, GPSR6_11,
  5095. GP_6_10_FN, GPSR6_10,
  5096. GP_6_9_FN, GPSR6_9,
  5097. GP_6_8_FN, GPSR6_8,
  5098. GP_6_7_FN, GPSR6_7,
  5099. GP_6_6_FN, GPSR6_6,
  5100. GP_6_5_FN, GPSR6_5,
  5101. GP_6_4_FN, GPSR6_4,
  5102. GP_6_3_FN, GPSR6_3,
  5103. GP_6_2_FN, GPSR6_2,
  5104. GP_6_1_FN, GPSR6_1,
  5105. GP_6_0_FN, GPSR6_0, ))
  5106. },
  5107. { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
  5108. 0, 0,
  5109. 0, 0,
  5110. 0, 0,
  5111. 0, 0,
  5112. 0, 0,
  5113. 0, 0,
  5114. 0, 0,
  5115. 0, 0,
  5116. 0, 0,
  5117. 0, 0,
  5118. 0, 0,
  5119. 0, 0,
  5120. 0, 0,
  5121. 0, 0,
  5122. 0, 0,
  5123. 0, 0,
  5124. 0, 0,
  5125. 0, 0,
  5126. 0, 0,
  5127. 0, 0,
  5128. 0, 0,
  5129. 0, 0,
  5130. 0, 0,
  5131. 0, 0,
  5132. 0, 0,
  5133. 0, 0,
  5134. 0, 0,
  5135. 0, 0,
  5136. GP_7_3_FN, GPSR7_3,
  5137. GP_7_2_FN, GPSR7_2,
  5138. GP_7_1_FN, GPSR7_1,
  5139. GP_7_0_FN, GPSR7_0, ))
  5140. },
  5141. #undef F_
  5142. #undef FM
  5143. #define F_(x, y) x,
  5144. #define FM(x) FN_##x,
  5145. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  5146. IP0_31_28
  5147. IP0_27_24
  5148. IP0_23_20
  5149. IP0_19_16
  5150. IP0_15_12
  5151. IP0_11_8
  5152. IP0_7_4
  5153. IP0_3_0 ))
  5154. },
  5155. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  5156. IP1_31_28
  5157. IP1_27_24
  5158. IP1_23_20
  5159. IP1_19_16
  5160. IP1_15_12
  5161. IP1_11_8
  5162. IP1_7_4
  5163. IP1_3_0 ))
  5164. },
  5165. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  5166. IP2_31_28
  5167. IP2_27_24
  5168. IP2_23_20
  5169. IP2_19_16
  5170. IP2_15_12
  5171. IP2_11_8
  5172. IP2_7_4
  5173. IP2_3_0 ))
  5174. },
  5175. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  5176. IP3_31_28
  5177. IP3_27_24
  5178. IP3_23_20
  5179. IP3_19_16
  5180. IP3_15_12
  5181. IP3_11_8
  5182. IP3_7_4
  5183. IP3_3_0 ))
  5184. },
  5185. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  5186. IP4_31_28
  5187. IP4_27_24
  5188. IP4_23_20
  5189. IP4_19_16
  5190. IP4_15_12
  5191. IP4_11_8
  5192. IP4_7_4
  5193. IP4_3_0 ))
  5194. },
  5195. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  5196. IP5_31_28
  5197. IP5_27_24
  5198. IP5_23_20
  5199. IP5_19_16
  5200. IP5_15_12
  5201. IP5_11_8
  5202. IP5_7_4
  5203. IP5_3_0 ))
  5204. },
  5205. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  5206. IP6_31_28
  5207. IP6_27_24
  5208. IP6_23_20
  5209. IP6_19_16
  5210. IP6_15_12
  5211. IP6_11_8
  5212. IP6_7_4
  5213. IP6_3_0 ))
  5214. },
  5215. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  5216. IP7_31_28
  5217. IP7_27_24
  5218. IP7_23_20
  5219. IP7_19_16
  5220. /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5221. IP7_11_8
  5222. IP7_7_4
  5223. IP7_3_0 ))
  5224. },
  5225. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  5226. IP8_31_28
  5227. IP8_27_24
  5228. IP8_23_20
  5229. IP8_19_16
  5230. IP8_15_12
  5231. IP8_11_8
  5232. IP8_7_4
  5233. IP8_3_0 ))
  5234. },
  5235. { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
  5236. IP9_31_28
  5237. IP9_27_24
  5238. IP9_23_20
  5239. IP9_19_16
  5240. IP9_15_12
  5241. IP9_11_8
  5242. IP9_7_4
  5243. IP9_3_0 ))
  5244. },
  5245. { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
  5246. IP10_31_28
  5247. IP10_27_24
  5248. IP10_23_20
  5249. IP10_19_16
  5250. IP10_15_12
  5251. IP10_11_8
  5252. IP10_7_4
  5253. IP10_3_0 ))
  5254. },
  5255. { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
  5256. IP11_31_28
  5257. IP11_27_24
  5258. IP11_23_20
  5259. IP11_19_16
  5260. IP11_15_12
  5261. IP11_11_8
  5262. IP11_7_4
  5263. IP11_3_0 ))
  5264. },
  5265. { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
  5266. IP12_31_28
  5267. IP12_27_24
  5268. IP12_23_20
  5269. IP12_19_16
  5270. IP12_15_12
  5271. IP12_11_8
  5272. IP12_7_4
  5273. IP12_3_0 ))
  5274. },
  5275. { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
  5276. IP13_31_28
  5277. IP13_27_24
  5278. IP13_23_20
  5279. IP13_19_16
  5280. IP13_15_12
  5281. IP13_11_8
  5282. IP13_7_4
  5283. IP13_3_0 ))
  5284. },
  5285. { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
  5286. IP14_31_28
  5287. IP14_27_24
  5288. IP14_23_20
  5289. IP14_19_16
  5290. IP14_15_12
  5291. IP14_11_8
  5292. IP14_7_4
  5293. IP14_3_0 ))
  5294. },
  5295. { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
  5296. IP15_31_28
  5297. IP15_27_24
  5298. IP15_23_20
  5299. IP15_19_16
  5300. IP15_15_12
  5301. IP15_11_8
  5302. IP15_7_4
  5303. IP15_3_0 ))
  5304. },
  5305. { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
  5306. IP16_31_28
  5307. IP16_27_24
  5308. IP16_23_20
  5309. IP16_19_16
  5310. IP16_15_12
  5311. IP16_11_8
  5312. IP16_7_4
  5313. IP16_3_0 ))
  5314. },
  5315. { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
  5316. IP17_31_28
  5317. IP17_27_24
  5318. IP17_23_20
  5319. IP17_19_16
  5320. IP17_15_12
  5321. IP17_11_8
  5322. IP17_7_4
  5323. IP17_3_0 ))
  5324. },
  5325. { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
  5326. /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5327. /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5328. /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5329. /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5330. /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5331. /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5332. IP18_7_4
  5333. IP18_3_0 ))
  5334. },
  5335. #undef F_
  5336. #undef FM
  5337. #define F_(x, y) x,
  5338. #define FM(x) FN_##x,
  5339. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  5340. GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
  5341. 1, 1, 1, 2, 2, 1, 2, 3),
  5342. GROUP(
  5343. MOD_SEL0_31_30_29
  5344. MOD_SEL0_28_27
  5345. MOD_SEL0_26_25_24
  5346. MOD_SEL0_23
  5347. MOD_SEL0_22
  5348. MOD_SEL0_21
  5349. MOD_SEL0_20
  5350. MOD_SEL0_19
  5351. MOD_SEL0_18_17
  5352. MOD_SEL0_16
  5353. 0, 0, /* RESERVED 15 */
  5354. MOD_SEL0_14_13
  5355. MOD_SEL0_12
  5356. MOD_SEL0_11
  5357. MOD_SEL0_10
  5358. MOD_SEL0_9_8
  5359. MOD_SEL0_7_6
  5360. MOD_SEL0_5
  5361. MOD_SEL0_4_3
  5362. /* RESERVED 2, 1, 0 */
  5363. 0, 0, 0, 0, 0, 0, 0, 0 ))
  5364. },
  5365. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
  5366. GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
  5367. 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
  5368. GROUP(
  5369. MOD_SEL1_31_30
  5370. MOD_SEL1_29_28_27
  5371. MOD_SEL1_26
  5372. MOD_SEL1_25_24
  5373. MOD_SEL1_23_22_21
  5374. MOD_SEL1_20
  5375. MOD_SEL1_19
  5376. MOD_SEL1_18_17
  5377. MOD_SEL1_16
  5378. MOD_SEL1_15_14
  5379. MOD_SEL1_13
  5380. MOD_SEL1_12
  5381. MOD_SEL1_11
  5382. MOD_SEL1_10
  5383. MOD_SEL1_9
  5384. 0, 0, 0, 0, /* RESERVED 8, 7 */
  5385. MOD_SEL1_6
  5386. MOD_SEL1_5
  5387. MOD_SEL1_4
  5388. MOD_SEL1_3
  5389. MOD_SEL1_2
  5390. MOD_SEL1_1
  5391. MOD_SEL1_0 ))
  5392. },
  5393. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
  5394. GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
  5395. 1, 4, 4, 4, 3, 1),
  5396. GROUP(
  5397. MOD_SEL2_31
  5398. MOD_SEL2_30
  5399. MOD_SEL2_29
  5400. MOD_SEL2_28_27
  5401. MOD_SEL2_26
  5402. MOD_SEL2_25_24_23
  5403. MOD_SEL2_22
  5404. MOD_SEL2_21
  5405. MOD_SEL2_20
  5406. MOD_SEL2_19
  5407. MOD_SEL2_18
  5408. MOD_SEL2_17
  5409. /* RESERVED 16 */
  5410. 0, 0,
  5411. /* RESERVED 15, 14, 13, 12 */
  5412. 0, 0, 0, 0, 0, 0, 0, 0,
  5413. 0, 0, 0, 0, 0, 0, 0, 0,
  5414. /* RESERVED 11, 10, 9, 8 */
  5415. 0, 0, 0, 0, 0, 0, 0, 0,
  5416. 0, 0, 0, 0, 0, 0, 0, 0,
  5417. /* RESERVED 7, 6, 5, 4 */
  5418. 0, 0, 0, 0, 0, 0, 0, 0,
  5419. 0, 0, 0, 0, 0, 0, 0, 0,
  5420. /* RESERVED 3, 2, 1 */
  5421. 0, 0, 0, 0, 0, 0, 0, 0,
  5422. MOD_SEL2_0 ))
  5423. },
  5424. { },
  5425. };
  5426. static const struct pinmux_drive_reg pinmux_drive_regs[] = {
  5427. { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
  5428. { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
  5429. { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
  5430. { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
  5431. { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
  5432. { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
  5433. { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
  5434. { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
  5435. { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
  5436. } },
  5437. { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
  5438. { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
  5439. { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
  5440. { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
  5441. { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
  5442. { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
  5443. { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
  5444. { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
  5445. { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
  5446. } },
  5447. { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
  5448. { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
  5449. { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
  5450. { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
  5451. { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
  5452. { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
  5453. { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
  5454. { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
  5455. { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
  5456. } },
  5457. { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
  5458. { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
  5459. { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
  5460. { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
  5461. { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
  5462. { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
  5463. { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
  5464. { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
  5465. { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
  5466. } },
  5467. { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
  5468. { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
  5469. { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
  5470. { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
  5471. { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
  5472. { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
  5473. { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
  5474. { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
  5475. { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
  5476. } },
  5477. { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
  5478. { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
  5479. { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
  5480. { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
  5481. { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
  5482. { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
  5483. { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
  5484. { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
  5485. { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
  5486. } },
  5487. { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
  5488. { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
  5489. { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
  5490. { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
  5491. { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
  5492. { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
  5493. { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
  5494. { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
  5495. { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
  5496. } },
  5497. { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
  5498. { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
  5499. { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
  5500. { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
  5501. { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
  5502. { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
  5503. { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
  5504. { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
  5505. { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
  5506. } },
  5507. { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
  5508. { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
  5509. { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
  5510. { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
  5511. { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
  5512. { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
  5513. { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
  5514. { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
  5515. { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
  5516. } },
  5517. { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
  5518. { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
  5519. { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
  5520. { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
  5521. { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
  5522. { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
  5523. { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
  5524. { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
  5525. { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
  5526. } },
  5527. { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
  5528. { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
  5529. { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
  5530. { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
  5531. { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
  5532. { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
  5533. { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
  5534. { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
  5535. { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
  5536. } },
  5537. { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
  5538. { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
  5539. { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
  5540. { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
  5541. { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
  5542. { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
  5543. { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
  5544. { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
  5545. { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
  5546. } },
  5547. { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
  5548. { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
  5549. { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
  5550. { PIN_TMS, 4, 2 }, /* TMS */
  5551. } },
  5552. { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
  5553. { PIN_TDO, 28, 2 }, /* TDO */
  5554. { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
  5555. { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
  5556. { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
  5557. { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
  5558. { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
  5559. { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
  5560. { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
  5561. } },
  5562. { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
  5563. { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
  5564. { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
  5565. { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
  5566. { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
  5567. { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
  5568. { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
  5569. { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
  5570. { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
  5571. } },
  5572. { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
  5573. { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
  5574. { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
  5575. { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
  5576. { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
  5577. { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
  5578. { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
  5579. { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
  5580. { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
  5581. } },
  5582. { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
  5583. { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
  5584. { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
  5585. { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
  5586. { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
  5587. { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
  5588. { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
  5589. { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
  5590. { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
  5591. } },
  5592. { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
  5593. { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
  5594. { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
  5595. { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
  5596. { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
  5597. { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
  5598. { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
  5599. { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
  5600. { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
  5601. } },
  5602. { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
  5603. { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
  5604. { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
  5605. { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
  5606. { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
  5607. { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
  5608. { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
  5609. { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
  5610. { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
  5611. } },
  5612. { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
  5613. { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
  5614. { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
  5615. { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
  5616. { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
  5617. { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
  5618. { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
  5619. { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
  5620. { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
  5621. } },
  5622. { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
  5623. { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
  5624. { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
  5625. { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
  5626. { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
  5627. { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
  5628. { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
  5629. { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
  5630. { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
  5631. } },
  5632. { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
  5633. { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
  5634. { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
  5635. { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
  5636. { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
  5637. { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
  5638. { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
  5639. { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
  5640. { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
  5641. } },
  5642. { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
  5643. { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
  5644. { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
  5645. { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
  5646. { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
  5647. { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
  5648. { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
  5649. { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
  5650. { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
  5651. } },
  5652. { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
  5653. { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
  5654. { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
  5655. { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
  5656. { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
  5657. { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
  5658. { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
  5659. { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
  5660. { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
  5661. } },
  5662. { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
  5663. { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
  5664. { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
  5665. { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
  5666. { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
  5667. { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
  5668. { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
  5669. { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
  5670. } },
  5671. { },
  5672. };
  5673. enum ioctrl_regs {
  5674. POCCTRL,
  5675. TDSELCTRL,
  5676. };
  5677. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  5678. [POCCTRL] = { 0xe6060380, },
  5679. [TDSELCTRL] = { 0xe60603c0, },
  5680. { /* sentinel */ },
  5681. };
  5682. static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
  5683. {
  5684. int bit = -EINVAL;
  5685. *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
  5686. if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
  5687. bit = pin & 0x1f;
  5688. if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
  5689. bit = (pin & 0x1f) + 12;
  5690. return bit;
  5691. }
  5692. static const struct pinmux_bias_reg pinmux_bias_regs[] = {
  5693. { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
  5694. [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
  5695. [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
  5696. [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
  5697. [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
  5698. [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
  5699. [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
  5700. [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
  5701. [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
  5702. [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
  5703. [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
  5704. [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
  5705. [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
  5706. [12] = PIN_RPC_INT_N, /* RPC_INT# */
  5707. [13] = PIN_RPC_WP_N, /* RPC_WP# */
  5708. [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
  5709. [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
  5710. [16] = PIN_AVB_RXC, /* AVB_RXC */
  5711. [17] = PIN_AVB_RD0, /* AVB_RD0 */
  5712. [18] = PIN_AVB_RD1, /* AVB_RD1 */
  5713. [19] = PIN_AVB_RD2, /* AVB_RD2 */
  5714. [20] = PIN_AVB_RD3, /* AVB_RD3 */
  5715. [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
  5716. [22] = PIN_AVB_TXC, /* AVB_TXC */
  5717. [23] = PIN_AVB_TD0, /* AVB_TD0 */
  5718. [24] = PIN_AVB_TD1, /* AVB_TD1 */
  5719. [25] = PIN_AVB_TD2, /* AVB_TD2 */
  5720. [26] = PIN_AVB_TD3, /* AVB_TD3 */
  5721. [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
  5722. [28] = PIN_AVB_MDIO, /* AVB_MDIO */
  5723. [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
  5724. [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
  5725. [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
  5726. } },
  5727. { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
  5728. [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
  5729. [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
  5730. [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
  5731. [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
  5732. [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
  5733. [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
  5734. [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
  5735. [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
  5736. [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
  5737. [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
  5738. [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
  5739. [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
  5740. [12] = RCAR_GP_PIN(1, 0), /* A0 */
  5741. [13] = RCAR_GP_PIN(1, 1), /* A1 */
  5742. [14] = RCAR_GP_PIN(1, 2), /* A2 */
  5743. [15] = RCAR_GP_PIN(1, 3), /* A3 */
  5744. [16] = RCAR_GP_PIN(1, 4), /* A4 */
  5745. [17] = RCAR_GP_PIN(1, 5), /* A5 */
  5746. [18] = RCAR_GP_PIN(1, 6), /* A6 */
  5747. [19] = RCAR_GP_PIN(1, 7), /* A7 */
  5748. [20] = RCAR_GP_PIN(1, 8), /* A8 */
  5749. [21] = RCAR_GP_PIN(1, 9), /* A9 */
  5750. [22] = RCAR_GP_PIN(1, 10), /* A10 */
  5751. [23] = RCAR_GP_PIN(1, 11), /* A11 */
  5752. [24] = RCAR_GP_PIN(1, 12), /* A12 */
  5753. [25] = RCAR_GP_PIN(1, 13), /* A13 */
  5754. [26] = RCAR_GP_PIN(1, 14), /* A14 */
  5755. [27] = RCAR_GP_PIN(1, 15), /* A15 */
  5756. [28] = RCAR_GP_PIN(1, 16), /* A16 */
  5757. [29] = RCAR_GP_PIN(1, 17), /* A17 */
  5758. [30] = RCAR_GP_PIN(1, 18), /* A18 */
  5759. [31] = RCAR_GP_PIN(1, 19), /* A19 */
  5760. } },
  5761. { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
  5762. [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
  5763. [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
  5764. [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
  5765. [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
  5766. [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
  5767. [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
  5768. [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
  5769. [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
  5770. [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
  5771. [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
  5772. [10] = RCAR_GP_PIN(0, 0), /* D0 */
  5773. [11] = RCAR_GP_PIN(0, 1), /* D1 */
  5774. [12] = RCAR_GP_PIN(0, 2), /* D2 */
  5775. [13] = RCAR_GP_PIN(0, 3), /* D3 */
  5776. [14] = RCAR_GP_PIN(0, 4), /* D4 */
  5777. [15] = RCAR_GP_PIN(0, 5), /* D5 */
  5778. [16] = RCAR_GP_PIN(0, 6), /* D6 */
  5779. [17] = RCAR_GP_PIN(0, 7), /* D7 */
  5780. [18] = RCAR_GP_PIN(0, 8), /* D8 */
  5781. [19] = RCAR_GP_PIN(0, 9), /* D9 */
  5782. [20] = RCAR_GP_PIN(0, 10), /* D10 */
  5783. [21] = RCAR_GP_PIN(0, 11), /* D11 */
  5784. [22] = RCAR_GP_PIN(0, 12), /* D12 */
  5785. [23] = RCAR_GP_PIN(0, 13), /* D13 */
  5786. [24] = RCAR_GP_PIN(0, 14), /* D14 */
  5787. [25] = RCAR_GP_PIN(0, 15), /* D15 */
  5788. [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
  5789. [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
  5790. [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
  5791. [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
  5792. [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
  5793. [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
  5794. } },
  5795. { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
  5796. [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
  5797. [ 1] = SH_PFC_PIN_NONE,
  5798. [ 2] = PIN_FSCLKST, /* FSCLKST */
  5799. [ 3] = PIN_EXTALR, /* EXTALR*/
  5800. [ 4] = PIN_TRST_N, /* TRST# */
  5801. [ 5] = PIN_TCK, /* TCK */
  5802. [ 6] = PIN_TMS, /* TMS */
  5803. [ 7] = PIN_TDI, /* TDI */
  5804. [ 8] = SH_PFC_PIN_NONE,
  5805. [ 9] = PIN_ASEBRK, /* ASEBRK */
  5806. [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
  5807. [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
  5808. [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
  5809. [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
  5810. [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
  5811. [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
  5812. [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
  5813. [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
  5814. [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
  5815. [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
  5816. [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
  5817. [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
  5818. [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
  5819. [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
  5820. [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
  5821. [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
  5822. [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
  5823. [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
  5824. [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
  5825. [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
  5826. [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
  5827. [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
  5828. } },
  5829. { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
  5830. [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
  5831. [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
  5832. [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
  5833. [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
  5834. [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
  5835. [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
  5836. [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
  5837. [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
  5838. [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
  5839. [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
  5840. [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
  5841. [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
  5842. [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
  5843. [13] = RCAR_GP_PIN(5, 1), /* RX0 */
  5844. [14] = RCAR_GP_PIN(5, 2), /* TX0 */
  5845. [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
  5846. [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
  5847. [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
  5848. [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
  5849. [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
  5850. [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
  5851. [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
  5852. [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
  5853. [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
  5854. [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
  5855. [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
  5856. [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
  5857. [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
  5858. [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
  5859. [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
  5860. [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
  5861. [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
  5862. } },
  5863. { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
  5864. [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
  5865. [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
  5866. [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
  5867. [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
  5868. [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
  5869. [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
  5870. [ 6] = PIN_MLB_REF, /* MLB_REF */
  5871. [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
  5872. [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
  5873. [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
  5874. [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
  5875. [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
  5876. [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
  5877. [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
  5878. [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
  5879. [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
  5880. [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
  5881. [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
  5882. [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
  5883. [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
  5884. [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
  5885. [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
  5886. [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
  5887. [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
  5888. [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
  5889. [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
  5890. [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
  5891. [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
  5892. [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
  5893. [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
  5894. [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
  5895. [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
  5896. } },
  5897. { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
  5898. [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
  5899. [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
  5900. [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
  5901. [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
  5902. [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
  5903. [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
  5904. [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
  5905. [ 7] = SH_PFC_PIN_NONE,
  5906. [ 8] = SH_PFC_PIN_NONE,
  5907. [ 9] = SH_PFC_PIN_NONE,
  5908. [10] = SH_PFC_PIN_NONE,
  5909. [11] = SH_PFC_PIN_NONE,
  5910. [12] = SH_PFC_PIN_NONE,
  5911. [13] = SH_PFC_PIN_NONE,
  5912. [14] = SH_PFC_PIN_NONE,
  5913. [15] = SH_PFC_PIN_NONE,
  5914. [16] = SH_PFC_PIN_NONE,
  5915. [17] = SH_PFC_PIN_NONE,
  5916. [18] = SH_PFC_PIN_NONE,
  5917. [19] = SH_PFC_PIN_NONE,
  5918. [20] = SH_PFC_PIN_NONE,
  5919. [21] = SH_PFC_PIN_NONE,
  5920. [22] = SH_PFC_PIN_NONE,
  5921. [23] = SH_PFC_PIN_NONE,
  5922. [24] = SH_PFC_PIN_NONE,
  5923. [25] = SH_PFC_PIN_NONE,
  5924. [26] = SH_PFC_PIN_NONE,
  5925. [27] = SH_PFC_PIN_NONE,
  5926. [28] = SH_PFC_PIN_NONE,
  5927. [29] = SH_PFC_PIN_NONE,
  5928. [30] = SH_PFC_PIN_NONE,
  5929. [31] = SH_PFC_PIN_NONE,
  5930. } },
  5931. { /* sentinel */ },
  5932. };
  5933. static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
  5934. unsigned int pin)
  5935. {
  5936. const struct pinmux_bias_reg *reg;
  5937. unsigned int bit;
  5938. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  5939. if (!reg)
  5940. return PIN_CONFIG_BIAS_DISABLE;
  5941. if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
  5942. return PIN_CONFIG_BIAS_DISABLE;
  5943. else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
  5944. return PIN_CONFIG_BIAS_PULL_UP;
  5945. else
  5946. return PIN_CONFIG_BIAS_PULL_DOWN;
  5947. }
  5948. static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  5949. unsigned int bias)
  5950. {
  5951. const struct pinmux_bias_reg *reg;
  5952. u32 enable, updown;
  5953. unsigned int bit;
  5954. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  5955. if (!reg)
  5956. return;
  5957. enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
  5958. if (bias != PIN_CONFIG_BIAS_DISABLE)
  5959. enable |= BIT(bit);
  5960. updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
  5961. if (bias == PIN_CONFIG_BIAS_PULL_UP)
  5962. updown |= BIT(bit);
  5963. sh_pfc_write(pfc, reg->pud, updown);
  5964. sh_pfc_write(pfc, reg->puen, enable);
  5965. }
  5966. static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
  5967. .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
  5968. .get_bias = r8a7796_pinmux_get_bias,
  5969. .set_bias = r8a7796_pinmux_set_bias,
  5970. };
  5971. #ifdef CONFIG_PINCTRL_PFC_R8A774A1
  5972. const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
  5973. .name = "r8a774a1_pfc",
  5974. .ops = &r8a7796_pinmux_ops,
  5975. .unlock_reg = 0xe6060000, /* PMMR */
  5976. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5977. .pins = pinmux_pins,
  5978. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5979. .groups = pinmux_groups.common,
  5980. .nr_groups = ARRAY_SIZE(pinmux_groups.common),
  5981. .functions = pinmux_functions.common,
  5982. .nr_functions = ARRAY_SIZE(pinmux_functions.common),
  5983. .cfg_regs = pinmux_config_regs,
  5984. .drive_regs = pinmux_drive_regs,
  5985. .bias_regs = pinmux_bias_regs,
  5986. .ioctrl_regs = pinmux_ioctrl_regs,
  5987. .pinmux_data = pinmux_data,
  5988. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5989. };
  5990. #endif
  5991. #ifdef CONFIG_PINCTRL_PFC_R8A7796
  5992. const struct sh_pfc_soc_info r8a7796_pinmux_info = {
  5993. .name = "r8a77960_pfc",
  5994. .ops = &r8a7796_pinmux_ops,
  5995. .unlock_reg = 0xe6060000, /* PMMR */
  5996. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5997. .pins = pinmux_pins,
  5998. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5999. .groups = pinmux_groups.common,
  6000. .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
  6001. ARRAY_SIZE(pinmux_groups.automotive),
  6002. .functions = pinmux_functions.common,
  6003. .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
  6004. ARRAY_SIZE(pinmux_functions.automotive),
  6005. .cfg_regs = pinmux_config_regs,
  6006. .drive_regs = pinmux_drive_regs,
  6007. .bias_regs = pinmux_bias_regs,
  6008. .ioctrl_regs = pinmux_ioctrl_regs,
  6009. .pinmux_data = pinmux_data,
  6010. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  6011. };
  6012. #endif