pfc-r8a7794.c 168 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7794/r8a7745 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2014-2015 Renesas Electronics Corporation
  6. * Copyright (C) 2015 Renesas Solutions Corp.
  7. * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <dm/pinctrl.h>
  13. #include <linux/kernel.h>
  14. #include "sh_pfc.h"
  15. #define CPU_ALL_GP(fn, sfx) \
  16. PORT_GP_32(0, fn, sfx), \
  17. PORT_GP_26(1, fn, sfx), \
  18. PORT_GP_32(2, fn, sfx), \
  19. PORT_GP_32(3, fn, sfx), \
  20. PORT_GP_32(4, fn, sfx), \
  21. PORT_GP_28(5, fn, sfx), \
  22. PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  23. PORT_GP_1(6, 24, fn, sfx), \
  24. PORT_GP_1(6, 25, fn, sfx)
  25. enum {
  26. PINMUX_RESERVED = 0,
  27. PINMUX_DATA_BEGIN,
  28. GP_ALL(DATA),
  29. PINMUX_DATA_END,
  30. PINMUX_FUNCTION_BEGIN,
  31. GP_ALL(FN),
  32. /* GPSR0 */
  33. FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  34. FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  35. FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  36. FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  37. FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  38. FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  39. FN_IP2_17_16,
  40. /* GPSR1 */
  41. FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  42. FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  43. FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  44. FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  45. FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  46. /* GPSR2 */
  47. FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  48. FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  49. FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  50. FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  51. FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  52. FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  53. FN_IP6_5_4, FN_IP6_7_6,
  54. /* GPSR3 */
  55. FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  56. FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  57. FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  58. FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  59. FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  60. FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  61. FN_IP8_22_20,
  62. /* GPSR4 */
  63. FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  64. FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  65. FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  66. FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  67. FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  68. FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  69. FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  70. /* GPSR5 */
  71. FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  72. FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  73. FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  74. FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  75. FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  76. FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  77. /* GPSR6 */
  78. FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  79. FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  80. FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  81. FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  82. FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  83. /* IPSR0 */
  84. FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  85. FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
  86. FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
  87. FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
  88. FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
  89. FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
  90. FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
  91. FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
  92. /* IPSR1 */
  93. FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
  94. FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
  95. FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
  96. FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
  97. FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
  98. FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
  99. FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
  100. FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
  101. FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
  102. FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
  103. FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
  104. FN_A1, FN_SCIFB1_TXD,
  105. FN_A3, FN_SCIFB0_SCK,
  106. FN_A4, FN_SCIFB0_TXD,
  107. FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
  108. FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
  109. /* IPSR2 */
  110. FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
  111. FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
  112. FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
  113. FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
  114. FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
  115. FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
  116. FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
  117. FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
  118. FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
  119. FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
  120. FN_TPUTO2_B,
  121. FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
  122. FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
  123. FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
  124. FN_A20, FN_SPCLK,
  125. /* IPSR3 */
  126. FN_A21, FN_MOSI_IO0,
  127. FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
  128. FN_A23, FN_IO2, FN_ATAWR1_N,
  129. FN_A24, FN_IO3, FN_EX_WAIT2,
  130. FN_A25, FN_SSL, FN_ATARD1_N,
  131. FN_CS0_N, FN_VI1_DATA8,
  132. FN_CS1_N_A26, FN_VI1_DATA9,
  133. FN_EX_CS0_N, FN_VI1_DATA10,
  134. FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
  135. FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
  136. FN_SCIFB2_TXD,
  137. FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
  138. FN_SCIFB2_SCK,
  139. FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
  140. FN_SCIFB2_CTS_N,
  141. FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
  142. FN_SCIFB2_RTS_N,
  143. FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
  144. FN_RD_N, FN_ATACS11_N,
  145. FN_RD_WR_N, FN_ATAG1_N,
  146. /* IPSR4 */
  147. FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
  148. FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
  149. FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
  150. FN_DU0_DR2, FN_LCDOUT18,
  151. FN_DU0_DR3, FN_LCDOUT19,
  152. FN_DU0_DR4, FN_LCDOUT20,
  153. FN_DU0_DR5, FN_LCDOUT21,
  154. FN_DU0_DR6, FN_LCDOUT22,
  155. FN_DU0_DR7, FN_LCDOUT23,
  156. FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
  157. FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
  158. FN_DU0_DG2, FN_LCDOUT10,
  159. FN_DU0_DG3, FN_LCDOUT11,
  160. FN_DU0_DG4, FN_LCDOUT12,
  161. /* IPSR5 */
  162. FN_DU0_DG5, FN_LCDOUT13,
  163. FN_DU0_DG6, FN_LCDOUT14,
  164. FN_DU0_DG7, FN_LCDOUT15,
  165. FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
  166. FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
  167. FN_DU0_DB2, FN_LCDOUT2,
  168. FN_DU0_DB3, FN_LCDOUT3,
  169. FN_DU0_DB4, FN_LCDOUT4,
  170. FN_DU0_DB5, FN_LCDOUT5,
  171. FN_DU0_DB6, FN_LCDOUT6,
  172. FN_DU0_DB7, FN_LCDOUT7,
  173. FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
  174. FN_DU0_DOTCLKOUT0, FN_QCLK,
  175. FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
  176. FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
  177. /* IPSR6 */
  178. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
  179. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
  180. FN_DU0_DISP, FN_QPOLA,
  181. FN_DU0_CDE, FN_QPOLB,
  182. FN_VI0_CLK, FN_AVB_RX_CLK,
  183. FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
  184. FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
  185. FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
  186. FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
  187. FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
  188. FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
  189. FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
  190. FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
  191. FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
  192. FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
  193. FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
  194. FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
  195. FN_AVB_TX_EN,
  196. FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
  197. FN_ADIDATA,
  198. /* IPSR7 */
  199. FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
  200. FN_ADICS_SAMP,
  201. FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
  202. FN_ADICLK,
  203. FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
  204. FN_ADICHS0,
  205. FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
  206. FN_ADICHS1,
  207. FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
  208. FN_ADICHS2,
  209. FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
  210. FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
  211. FN_SSI_WS5_B,
  212. FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
  213. FN_SSI_SDATA5_B,
  214. FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
  215. FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
  216. FN_SSI_WS6_B,
  217. FN_DREQ0_N, FN_SCIFB1_RXD,
  218. /* IPSR8 */
  219. FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
  220. FN_SSI_SDATA6_B,
  221. FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
  222. FN_SSI_SCK78_B,
  223. FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
  224. FN_SSI_WS78_B,
  225. FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
  226. FN_AVB_MAGIC, FN_SSI_SDATA7_B,
  227. FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
  228. FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
  229. FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
  230. FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
  231. FN_CAN1_RX_D, FN_TPUTO0_B,
  232. FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
  233. FN_CAN1_TX_D,
  234. FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
  235. FN_TPUTO1_B,
  236. FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
  237. FN_BPFCLK_C,
  238. FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
  239. FN_FMCLK_C,
  240. /* IPSR9 */
  241. FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
  242. FN_FMIN_C,
  243. FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
  244. FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
  245. FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
  246. FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
  247. FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
  248. FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
  249. FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
  250. FN_SPEEDIN_B,
  251. FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
  252. FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
  253. FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
  254. /* IPSR10 */
  255. FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
  256. FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
  257. FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
  258. FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
  259. FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
  260. FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
  261. FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
  262. FN_SSI_SCK4_B,
  263. FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
  264. FN_SSI_WS4_B,
  265. FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
  266. FN_SSI_SDATA4_B,
  267. FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
  268. FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
  269. /* IPSR11 */
  270. FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
  271. FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
  272. FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
  273. FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
  274. FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
  275. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
  276. FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
  277. FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
  278. FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
  279. FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
  280. FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
  281. FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
  282. /* IPSR12 */
  283. FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
  284. FN_DREQ1_N_B,
  285. FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
  286. FN_CAN1_RX_C, FN_DACK1_B,
  287. FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
  288. FN_CAN1_TX_C, FN_DREQ2_N,
  289. FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
  290. FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
  291. FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
  292. FN_DACK2, FN_ETH_MDIO_B,
  293. FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
  294. FN_ETH_CRS_DV_B,
  295. FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
  296. FN_ETH_RX_ER_B,
  297. FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
  298. FN_ETH_RXD0_B,
  299. FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
  300. /* IPSR13 */
  301. FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
  302. FN_ATACS00_N, FN_ETH_LINK_B,
  303. FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
  304. FN_ATACS10_N, FN_ETH_REFCLK_B,
  305. FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
  306. FN_ETH_TXD1_B,
  307. FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
  308. FN_ETH_TX_EN_B,
  309. FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
  310. FN_ATADIR0_N, FN_ETH_MAGIC_B,
  311. FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
  312. FN_TS_SDATA_C, FN_ETH_TXD0_B,
  313. FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
  314. FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
  315. FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
  316. FN_TS_SDEN_C, FN_FMCLK_E,
  317. FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
  318. FN_TS_SPSYNC_C, FN_FMIN_E,
  319. /* MOD_SEL */
  320. FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
  321. FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
  322. FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
  323. FN_SEL_DARC_4,
  324. FN_SEL_ETH_0, FN_SEL_ETH_1,
  325. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
  326. FN_SEL_I2C00_4,
  327. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
  328. FN_SEL_I2C01_4,
  329. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  330. FN_SEL_I2C02_4,
  331. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  332. FN_SEL_I2C03_4,
  333. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
  334. FN_SEL_I2C04_4,
  335. FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
  336. /* MOD_SEL2 */
  337. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
  338. FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
  339. FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
  340. FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
  341. FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
  342. FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
  343. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
  344. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
  345. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
  346. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
  347. FN_SEL_TMU_0, FN_SEL_TMU_1,
  348. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  349. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  350. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  351. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  352. /* MOD_SEL3 */
  353. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  354. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
  355. FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
  356. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  357. FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
  358. FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
  359. FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
  360. FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
  361. FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
  362. FN_SEL_SSI9_1,
  363. PINMUX_FUNCTION_END,
  364. PINMUX_MARK_BEGIN,
  365. A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
  366. USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
  367. SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
  368. SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
  369. SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
  370. SD1_DATA2_MARK, SD1_DATA3_MARK,
  371. /* IPSR0 */
  372. SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
  373. MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
  374. SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
  375. SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
  376. MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
  377. CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
  378. CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
  379. SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
  380. SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
  381. SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
  382. /* IPSR1 */
  383. D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
  384. D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
  385. D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
  386. D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
  387. D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
  388. D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
  389. D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
  390. D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
  391. D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
  392. D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
  393. A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
  394. A1_MARK, SCIFB1_TXD_MARK,
  395. A3_MARK, SCIFB0_SCK_MARK,
  396. A4_MARK, SCIFB0_TXD_MARK,
  397. A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
  398. A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
  399. /* IPSR2 */
  400. A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
  401. A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
  402. A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
  403. A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
  404. A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
  405. A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
  406. A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
  407. A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
  408. A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
  409. A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
  410. CAN_CLK_C_MARK, TPUTO2_B_MARK,
  411. A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
  412. A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
  413. A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
  414. A20_MARK, SPCLK_MARK,
  415. /* IPSR3 */
  416. A21_MARK, MOSI_IO0_MARK,
  417. A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
  418. A23_MARK, IO2_MARK, ATAWR1_N_MARK,
  419. A24_MARK, IO3_MARK, EX_WAIT2_MARK,
  420. A25_MARK, SSL_MARK, ATARD1_N_MARK,
  421. CS0_N_MARK, VI1_DATA8_MARK,
  422. CS1_N_A26_MARK, VI1_DATA9_MARK,
  423. EX_CS0_N_MARK, VI1_DATA10_MARK,
  424. EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
  425. EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
  426. TPUTO3_MARK, SCIFB2_TXD_MARK,
  427. EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
  428. BPFCLK_MARK, SCIFB2_SCK_MARK,
  429. EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
  430. FMCLK_MARK, SCIFB2_CTS_N_MARK,
  431. EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
  432. FMIN_MARK, SCIFB2_RTS_N_MARK,
  433. BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
  434. RD_N_MARK, ATACS11_N_MARK,
  435. RD_WR_N_MARK, ATAG1_N_MARK,
  436. /* IPSR4 */
  437. EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
  438. DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
  439. DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
  440. DU0_DR2_MARK, LCDOUT18_MARK,
  441. DU0_DR3_MARK, LCDOUT19_MARK,
  442. DU0_DR4_MARK, LCDOUT20_MARK,
  443. DU0_DR5_MARK, LCDOUT21_MARK,
  444. DU0_DR6_MARK, LCDOUT22_MARK,
  445. DU0_DR7_MARK, LCDOUT23_MARK,
  446. DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
  447. DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
  448. DU0_DG2_MARK, LCDOUT10_MARK,
  449. DU0_DG3_MARK, LCDOUT11_MARK,
  450. DU0_DG4_MARK, LCDOUT12_MARK,
  451. /* IPSR5 */
  452. DU0_DG5_MARK, LCDOUT13_MARK,
  453. DU0_DG6_MARK, LCDOUT14_MARK,
  454. DU0_DG7_MARK, LCDOUT15_MARK,
  455. DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
  456. CAN0_RX_C_MARK,
  457. DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
  458. CAN0_TX_C_MARK,
  459. DU0_DB2_MARK, LCDOUT2_MARK,
  460. DU0_DB3_MARK, LCDOUT3_MARK,
  461. DU0_DB4_MARK, LCDOUT4_MARK,
  462. DU0_DB5_MARK, LCDOUT5_MARK,
  463. DU0_DB6_MARK, LCDOUT6_MARK,
  464. DU0_DB7_MARK, LCDOUT7_MARK,
  465. DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
  466. DU0_DOTCLKOUT0_MARK, QCLK_MARK,
  467. DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
  468. DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
  469. /* IPSR6 */
  470. DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
  471. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
  472. DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
  473. VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
  474. VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
  475. VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
  476. VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
  477. VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
  478. VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
  479. VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
  480. VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
  481. VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
  482. AVB_RXD7_MARK,
  483. VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
  484. AVB_RX_ER_MARK,
  485. VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
  486. AVB_COL_MARK,
  487. VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
  488. AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
  489. ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
  490. AVB_TX_CLK_MARK, ADIDATA_MARK,
  491. /* IPSR7 */
  492. ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
  493. AVB_TXD0_MARK, ADICS_SAMP_MARK,
  494. ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
  495. AVB_TXD1_MARK, ADICLK_MARK,
  496. ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
  497. AVB_TXD2_MARK, ADICHS0_MARK,
  498. ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
  499. AVB_TXD3_MARK, ADICHS1_MARK,
  500. ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
  501. AVB_TXD4_MARK, ADICHS2_MARK,
  502. ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
  503. SSI_SCK5_B_MARK,
  504. ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
  505. AVB_TXD6_MARK, SSI_WS5_B_MARK,
  506. ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
  507. AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
  508. ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
  509. SSI_SCK6_B_MARK,
  510. ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
  511. AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
  512. DREQ0_N_MARK, SCIFB1_RXD_MARK,
  513. /* IPSR8 */
  514. ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
  515. AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
  516. I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
  517. HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
  518. AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
  519. SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
  520. HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
  521. AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
  522. HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
  523. I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
  524. AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
  525. SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
  526. CAN1_TX_D_MARK,
  527. I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
  528. TS_SDATA_D_MARK, TPUTO1_B_MARK,
  529. I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
  530. BPFCLK_C_MARK,
  531. MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
  532. TS_SDEN_D_MARK, FMCLK_C_MARK,
  533. /* IPSR9 */
  534. MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
  535. TS_SPSYNC_D_MARK, FMIN_C_MARK,
  536. MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
  537. MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
  538. MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
  539. FMCLK_B_MARK,
  540. MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
  541. FMIN_B_MARK,
  542. HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
  543. HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
  544. HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
  545. SPEEDIN_B_MARK,
  546. HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
  547. SSI_SCK1_B_MARK,
  548. HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
  549. SSI_WS1_B_MARK,
  550. SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
  551. CAN_TXCLK_MARK,
  552. /* IPSR10 */
  553. SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
  554. SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
  555. SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
  556. SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
  557. SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
  558. SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
  559. SSI_SDATA9_B_MARK,
  560. SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
  561. AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
  562. SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
  563. AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
  564. I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
  565. SSI_SDATA4_B_MARK,
  566. I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
  567. SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
  568. /* IPSR11 */
  569. SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
  570. SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
  571. SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
  572. SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
  573. DU1_EXVSYNC_DU1_VSYNC_MARK,
  574. SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
  575. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  576. SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
  577. SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
  578. SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
  579. CAN_CLK_D_MARK,
  580. SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
  581. SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
  582. SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
  583. /* IPSR12 */
  584. SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
  585. DREQ1_N_B_MARK,
  586. SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
  587. CAN1_RX_C_MARK, DACK1_B_MARK,
  588. SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
  589. CAN1_TX_C_MARK, DREQ2_N_MARK,
  590. SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
  591. SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
  592. SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
  593. SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
  594. DACK2_MARK, ETH_MDIO_B_MARK,
  595. SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
  596. CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
  597. SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
  598. CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
  599. SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
  600. ETH_RXD0_B_MARK,
  601. SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
  602. ETH_RXD1_B_MARK,
  603. /* IPSR13 */
  604. SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
  605. ATACS00_N_MARK, ETH_LINK_B_MARK,
  606. SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
  607. VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
  608. SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
  609. EX_WAIT1_MARK, ETH_TXD1_B_MARK,
  610. SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
  611. ATARD0_N_MARK, ETH_TX_EN_B_MARK,
  612. SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
  613. ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
  614. AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
  615. TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
  616. AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
  617. TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
  618. AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
  619. TS_SDEN_C_MARK, FMCLK_E_MARK,
  620. AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
  621. TS_SPSYNC_C_MARK, FMIN_E_MARK,
  622. PINMUX_MARK_END,
  623. };
  624. static const u16 pinmux_data[] = {
  625. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  626. PINMUX_SINGLE(A2),
  627. PINMUX_SINGLE(WE0_N),
  628. PINMUX_SINGLE(WE1_N),
  629. PINMUX_SINGLE(DACK0),
  630. PINMUX_SINGLE(USB0_PWEN),
  631. PINMUX_SINGLE(USB0_OVC),
  632. PINMUX_SINGLE(USB1_PWEN),
  633. PINMUX_SINGLE(USB1_OVC),
  634. PINMUX_SINGLE(SD0_CLK),
  635. PINMUX_SINGLE(SD0_CMD),
  636. PINMUX_SINGLE(SD0_DATA0),
  637. PINMUX_SINGLE(SD0_DATA1),
  638. PINMUX_SINGLE(SD0_DATA2),
  639. PINMUX_SINGLE(SD0_DATA3),
  640. PINMUX_SINGLE(SD0_CD),
  641. PINMUX_SINGLE(SD0_WP),
  642. PINMUX_SINGLE(SD1_CLK),
  643. PINMUX_SINGLE(SD1_CMD),
  644. PINMUX_SINGLE(SD1_DATA0),
  645. PINMUX_SINGLE(SD1_DATA1),
  646. PINMUX_SINGLE(SD1_DATA2),
  647. PINMUX_SINGLE(SD1_DATA3),
  648. /* IPSR0 */
  649. PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
  650. PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
  651. PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
  652. PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
  653. PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
  654. PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
  655. PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
  656. PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
  657. PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
  658. PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
  659. PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
  660. PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
  661. PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
  662. PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
  663. PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
  664. PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
  665. PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
  666. PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
  667. PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
  668. PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
  669. PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
  670. PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
  671. PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
  672. PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
  673. PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
  674. PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
  675. PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
  676. PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
  677. PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
  678. PINMUX_IPSR_GPSR(IP0_23_22, D0),
  679. PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
  680. PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
  681. PINMUX_IPSR_GPSR(IP0_24, D1),
  682. PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
  683. PINMUX_IPSR_GPSR(IP0_25, D2),
  684. PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
  685. PINMUX_IPSR_GPSR(IP0_27_26, D3),
  686. PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
  687. PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
  688. PINMUX_IPSR_GPSR(IP0_29_28, D4),
  689. PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
  690. PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
  691. PINMUX_IPSR_GPSR(IP0_31_30, D5),
  692. PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
  693. PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
  694. /* IPSR1 */
  695. PINMUX_IPSR_GPSR(IP1_1_0, D6),
  696. PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
  697. PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
  698. PINMUX_IPSR_GPSR(IP1_3_2, D7),
  699. PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
  700. PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
  701. PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
  702. PINMUX_IPSR_GPSR(IP1_5_4, D8),
  703. PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
  704. PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
  705. PINMUX_IPSR_GPSR(IP1_7_6, D9),
  706. PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
  707. PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
  708. PINMUX_IPSR_GPSR(IP1_10_8, D10),
  709. PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
  710. PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
  711. PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
  712. PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
  713. PINMUX_IPSR_GPSR(IP1_12_11, D11),
  714. PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
  715. PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
  716. PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
  717. PINMUX_IPSR_GPSR(IP1_14_13, D12),
  718. PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
  719. PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
  720. PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
  721. PINMUX_IPSR_GPSR(IP1_17_15, D13),
  722. PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
  723. PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
  724. PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
  725. PINMUX_IPSR_GPSR(IP1_19_18, D14),
  726. PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
  727. PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
  728. PINMUX_IPSR_GPSR(IP1_21_20, D15),
  729. PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
  730. PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
  731. PINMUX_IPSR_GPSR(IP1_23_22, A0),
  732. PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
  733. PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
  734. PINMUX_IPSR_GPSR(IP1_24, A1),
  735. PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
  736. PINMUX_IPSR_GPSR(IP1_26, A3),
  737. PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
  738. PINMUX_IPSR_GPSR(IP1_27, A4),
  739. PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
  740. PINMUX_IPSR_GPSR(IP1_29_28, A5),
  741. PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
  742. PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
  743. PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
  744. PINMUX_IPSR_GPSR(IP1_31_30, A6),
  745. PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
  746. PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
  747. PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
  748. /* IPSR2 */
  749. PINMUX_IPSR_GPSR(IP2_1_0, A7),
  750. PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
  751. PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
  752. PINMUX_IPSR_GPSR(IP2_3_2, A8),
  753. PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
  754. PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
  755. PINMUX_IPSR_GPSR(IP2_5_4, A9),
  756. PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
  757. PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
  758. PINMUX_IPSR_GPSR(IP2_7_6, A10),
  759. PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
  760. PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
  761. PINMUX_IPSR_GPSR(IP2_9_8, A11),
  762. PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
  763. PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
  764. PINMUX_IPSR_GPSR(IP2_11_10, A12),
  765. PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
  766. PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
  767. PINMUX_IPSR_GPSR(IP2_13_12, A13),
  768. PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
  769. PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
  770. PINMUX_IPSR_GPSR(IP2_15_14, A14),
  771. PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
  772. PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
  773. PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
  774. PINMUX_IPSR_GPSR(IP2_17_16, A15),
  775. PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
  776. PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
  777. PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
  778. PINMUX_IPSR_GPSR(IP2_20_18, A16),
  779. PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
  780. PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
  781. PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
  782. PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
  783. PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
  784. PINMUX_IPSR_GPSR(IP2_23_21, A17),
  785. PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
  786. PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
  787. PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
  788. PINMUX_IPSR_GPSR(IP2_26_24, A18),
  789. PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
  790. PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
  791. PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
  792. PINMUX_IPSR_GPSR(IP2_29_27, A19),
  793. PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
  794. PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
  795. PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
  796. PINMUX_IPSR_GPSR(IP2_31_30, A20),
  797. PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
  798. /* IPSR3 */
  799. PINMUX_IPSR_GPSR(IP3_1_0, A21),
  800. PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
  801. PINMUX_IPSR_GPSR(IP3_3_2, A22),
  802. PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
  803. PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
  804. PINMUX_IPSR_GPSR(IP3_5_4, A23),
  805. PINMUX_IPSR_GPSR(IP3_5_4, IO2),
  806. PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
  807. PINMUX_IPSR_GPSR(IP3_7_6, A24),
  808. PINMUX_IPSR_GPSR(IP3_7_6, IO3),
  809. PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
  810. PINMUX_IPSR_GPSR(IP3_9_8, A25),
  811. PINMUX_IPSR_GPSR(IP3_9_8, SSL),
  812. PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
  813. PINMUX_IPSR_GPSR(IP3_10, CS0_N),
  814. PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
  815. PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
  816. PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
  817. PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
  818. PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
  819. PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
  820. PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
  821. PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
  822. PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
  823. PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
  824. PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
  825. PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
  826. PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
  827. PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
  828. PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
  829. PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
  830. PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
  831. PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
  832. PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
  833. PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
  834. PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
  835. PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
  836. PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
  837. PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
  838. PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
  839. PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
  840. PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
  841. PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
  842. PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
  843. PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
  844. PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
  845. PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
  846. PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
  847. PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
  848. PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
  849. PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
  850. PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
  851. PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
  852. PINMUX_IPSR_GPSR(IP3_30, RD_N),
  853. PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
  854. PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
  855. PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
  856. /* IPSR4 */
  857. PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
  858. PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
  859. PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
  860. PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
  861. PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
  862. PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
  863. PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
  864. PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
  865. PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
  866. PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
  867. PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
  868. PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
  869. PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
  870. PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
  871. PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
  872. PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
  873. PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
  874. PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
  875. PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
  876. PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
  877. PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
  878. PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
  879. PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
  880. PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
  881. PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
  882. PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
  883. PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
  884. PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
  885. PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
  886. PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
  887. PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
  888. PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
  889. PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
  890. PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
  891. PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
  892. PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
  893. PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
  894. /* IPSR5 */
  895. PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
  896. PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
  897. PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
  898. PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
  899. PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
  900. PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
  901. PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
  902. PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
  903. PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
  904. PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
  905. PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
  906. PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
  907. PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
  908. PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
  909. PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
  910. PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
  911. PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
  912. PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
  913. PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
  914. PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
  915. PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
  916. PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
  917. PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
  918. PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
  919. PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
  920. PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
  921. PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
  922. PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
  923. PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
  924. PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
  925. PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
  926. PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
  927. PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
  928. PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
  929. PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
  930. PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
  931. /* IPSR6 */
  932. PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
  933. PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
  934. PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
  935. PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
  936. PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
  937. PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
  938. PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
  939. PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
  940. PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
  941. PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
  942. PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
  943. PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
  944. PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
  945. PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
  946. PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
  947. PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
  948. PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
  949. PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
  950. PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
  951. PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
  952. PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
  953. PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
  954. PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
  955. PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
  956. PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
  957. PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
  958. PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
  959. PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
  960. PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
  961. PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
  962. PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
  963. PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
  964. PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
  965. PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
  966. PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
  967. PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
  968. PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
  969. PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
  970. PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
  971. PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
  972. PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
  973. PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
  974. PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
  975. PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
  976. PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
  977. PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
  978. PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
  979. PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
  980. PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
  981. PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
  982. PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
  983. PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
  984. /* IPSR7 */
  985. PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
  986. PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
  987. PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
  988. PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
  989. PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
  990. PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
  991. PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
  992. PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
  993. PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
  994. PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
  995. PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
  996. PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
  997. PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
  998. PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
  999. PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
  1000. PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
  1001. PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
  1002. PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
  1003. PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
  1004. PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
  1005. PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
  1006. PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
  1007. PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
  1008. PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
  1009. PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
  1010. PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
  1011. PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
  1012. PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
  1013. PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
  1014. PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
  1015. PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
  1016. PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
  1017. PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
  1018. PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
  1019. PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
  1020. PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
  1021. PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
  1022. PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
  1023. PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
  1024. PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
  1025. PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
  1026. PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
  1027. PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
  1028. PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
  1029. PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
  1030. PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
  1031. PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
  1032. PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
  1033. PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
  1034. PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
  1035. PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
  1036. PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
  1037. PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
  1038. PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
  1039. PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
  1040. PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
  1041. PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
  1042. PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
  1043. PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
  1044. PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
  1045. /* IPSR8 */
  1046. PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
  1047. PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
  1048. PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
  1049. PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
  1050. PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
  1051. PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
  1052. PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
  1053. PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
  1054. PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
  1055. PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
  1056. PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
  1057. PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
  1058. PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
  1059. PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
  1060. PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
  1061. PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
  1062. PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
  1063. PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
  1064. PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
  1065. PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
  1066. PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
  1067. PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
  1068. PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
  1069. PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
  1070. PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
  1071. PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
  1072. PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
  1073. PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
  1074. PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
  1075. PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
  1076. PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
  1077. PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
  1078. PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
  1079. PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
  1080. PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
  1081. PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
  1082. PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
  1083. PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
  1084. PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
  1085. PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
  1086. PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
  1087. PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
  1088. PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
  1089. PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
  1090. PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
  1091. PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
  1092. PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
  1093. PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
  1094. PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
  1095. PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
  1096. PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
  1097. PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
  1098. PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
  1099. PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
  1100. PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
  1101. PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
  1102. PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
  1103. PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
  1104. PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
  1105. PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
  1106. PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
  1107. PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
  1108. PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
  1109. PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
  1110. PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
  1111. /* IPSR9 */
  1112. PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
  1113. PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
  1114. PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
  1115. PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
  1116. PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
  1117. PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
  1118. PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
  1119. PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
  1120. PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
  1121. PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
  1122. PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
  1123. PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
  1124. PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
  1125. PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
  1126. PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
  1127. PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
  1128. PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
  1129. PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
  1130. PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
  1131. PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
  1132. PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
  1133. PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
  1134. PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
  1135. PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
  1136. PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
  1137. PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
  1138. PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
  1139. PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
  1140. PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
  1141. PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
  1142. PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
  1143. PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
  1144. PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
  1145. PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
  1146. PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
  1147. PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
  1148. PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
  1149. PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
  1150. PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
  1151. PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
  1152. PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
  1153. PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
  1154. PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
  1155. PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
  1156. PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
  1157. PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
  1158. PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
  1159. PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
  1160. PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
  1161. PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
  1162. PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
  1163. PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
  1164. PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
  1165. PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
  1166. PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
  1167. /* IPSR10 */
  1168. PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
  1169. PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
  1170. PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
  1171. PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
  1172. PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
  1173. PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
  1174. PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
  1175. PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
  1176. PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
  1177. PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
  1178. PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
  1179. PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
  1180. PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
  1181. PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
  1182. PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
  1183. PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
  1184. PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
  1185. PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
  1186. PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
  1187. PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
  1188. PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
  1189. PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
  1190. PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
  1191. PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
  1192. PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
  1193. PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
  1194. PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
  1195. PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
  1196. PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
  1197. PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
  1198. PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
  1199. PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
  1200. PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
  1201. PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
  1202. PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
  1203. PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
  1204. PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
  1205. PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
  1206. PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
  1207. PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
  1208. PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
  1209. PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
  1210. PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
  1211. PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
  1212. PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
  1213. PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
  1214. PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
  1215. PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
  1216. PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
  1217. /* IPSR11 */
  1218. PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
  1219. PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
  1220. PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
  1221. PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
  1222. PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
  1223. PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
  1224. PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
  1225. PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
  1226. PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
  1227. PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
  1228. PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
  1229. PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
  1230. PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
  1231. PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
  1232. PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
  1233. PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
  1234. PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
  1235. PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
  1236. PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
  1237. PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
  1238. PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
  1239. PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
  1240. PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
  1241. PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
  1242. PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
  1243. PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
  1244. PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
  1245. PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
  1246. PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
  1247. PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
  1248. PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
  1249. PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
  1250. PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
  1251. PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
  1252. PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
  1253. PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
  1254. PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
  1255. PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
  1256. PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
  1257. PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
  1258. PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
  1259. PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
  1260. PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
  1261. PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
  1262. /* IPSR12 */
  1263. PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
  1264. PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
  1265. PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
  1266. PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
  1267. PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
  1268. PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
  1269. PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
  1270. PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
  1271. PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
  1272. PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
  1273. PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
  1274. PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
  1275. PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
  1276. PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
  1277. PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
  1278. PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
  1279. PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
  1280. PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
  1281. PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
  1282. PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
  1283. PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
  1284. PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
  1285. PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
  1286. PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
  1287. PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
  1288. PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
  1289. PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
  1290. PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
  1291. PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
  1292. PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
  1293. PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
  1294. PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
  1295. PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
  1296. PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
  1297. PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
  1298. PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
  1299. PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
  1300. PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
  1301. PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
  1302. PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
  1303. PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
  1304. PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
  1305. PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
  1306. PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
  1307. PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
  1308. PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
  1309. PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
  1310. PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
  1311. PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
  1312. PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
  1313. PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
  1314. PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
  1315. PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
  1316. PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
  1317. PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
  1318. /* IPSR13 */
  1319. PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
  1320. PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
  1321. PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
  1322. PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
  1323. PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
  1324. PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
  1325. PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
  1326. PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
  1327. PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
  1328. PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
  1329. PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
  1330. PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
  1331. PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
  1332. PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
  1333. PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
  1334. PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
  1335. PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
  1336. PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
  1337. PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
  1338. PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
  1339. PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
  1340. PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
  1341. PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
  1342. PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
  1343. PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
  1344. PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
  1345. PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
  1346. PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
  1347. PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
  1348. PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
  1349. PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
  1350. PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
  1351. PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
  1352. PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
  1353. PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
  1354. PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
  1355. PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
  1356. PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
  1357. PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
  1358. PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
  1359. PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
  1360. PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
  1361. PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
  1362. PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
  1363. PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
  1364. PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
  1365. PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
  1366. PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
  1367. PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
  1368. PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
  1369. PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
  1370. PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
  1371. PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
  1372. PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
  1373. PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
  1374. };
  1375. static const struct sh_pfc_pin pinmux_pins[] = {
  1376. PINMUX_GPIO_GP_ALL(),
  1377. };
  1378. /* - Audio Clock ------------------------------------------------------------ */
  1379. static const unsigned int audio_clka_pins[] = {
  1380. /* CLKA */
  1381. RCAR_GP_PIN(5, 20),
  1382. };
  1383. static const unsigned int audio_clka_mux[] = {
  1384. AUDIO_CLKA_MARK,
  1385. };
  1386. static const unsigned int audio_clka_b_pins[] = {
  1387. /* CLKA */
  1388. RCAR_GP_PIN(3, 25),
  1389. };
  1390. static const unsigned int audio_clka_b_mux[] = {
  1391. AUDIO_CLKA_B_MARK,
  1392. };
  1393. static const unsigned int audio_clka_c_pins[] = {
  1394. /* CLKA */
  1395. RCAR_GP_PIN(4, 20),
  1396. };
  1397. static const unsigned int audio_clka_c_mux[] = {
  1398. AUDIO_CLKA_C_MARK,
  1399. };
  1400. static const unsigned int audio_clka_d_pins[] = {
  1401. /* CLKA */
  1402. RCAR_GP_PIN(5, 0),
  1403. };
  1404. static const unsigned int audio_clka_d_mux[] = {
  1405. AUDIO_CLKA_D_MARK,
  1406. };
  1407. static const unsigned int audio_clkb_pins[] = {
  1408. /* CLKB */
  1409. RCAR_GP_PIN(5, 21),
  1410. };
  1411. static const unsigned int audio_clkb_mux[] = {
  1412. AUDIO_CLKB_MARK,
  1413. };
  1414. static const unsigned int audio_clkb_b_pins[] = {
  1415. /* CLKB */
  1416. RCAR_GP_PIN(3, 26),
  1417. };
  1418. static const unsigned int audio_clkb_b_mux[] = {
  1419. AUDIO_CLKB_B_MARK,
  1420. };
  1421. static const unsigned int audio_clkb_c_pins[] = {
  1422. /* CLKB */
  1423. RCAR_GP_PIN(4, 21),
  1424. };
  1425. static const unsigned int audio_clkb_c_mux[] = {
  1426. AUDIO_CLKB_C_MARK,
  1427. };
  1428. static const unsigned int audio_clkc_pins[] = {
  1429. /* CLKC */
  1430. RCAR_GP_PIN(5, 22),
  1431. };
  1432. static const unsigned int audio_clkc_mux[] = {
  1433. AUDIO_CLKC_MARK,
  1434. };
  1435. static const unsigned int audio_clkc_b_pins[] = {
  1436. /* CLKC */
  1437. RCAR_GP_PIN(3, 29),
  1438. };
  1439. static const unsigned int audio_clkc_b_mux[] = {
  1440. AUDIO_CLKC_B_MARK,
  1441. };
  1442. static const unsigned int audio_clkc_c_pins[] = {
  1443. /* CLKC */
  1444. RCAR_GP_PIN(4, 22),
  1445. };
  1446. static const unsigned int audio_clkc_c_mux[] = {
  1447. AUDIO_CLKC_C_MARK,
  1448. };
  1449. static const unsigned int audio_clkout_pins[] = {
  1450. /* CLKOUT */
  1451. RCAR_GP_PIN(5, 23),
  1452. };
  1453. static const unsigned int audio_clkout_mux[] = {
  1454. AUDIO_CLKOUT_MARK,
  1455. };
  1456. static const unsigned int audio_clkout_b_pins[] = {
  1457. /* CLKOUT */
  1458. RCAR_GP_PIN(3, 12),
  1459. };
  1460. static const unsigned int audio_clkout_b_mux[] = {
  1461. AUDIO_CLKOUT_B_MARK,
  1462. };
  1463. static const unsigned int audio_clkout_c_pins[] = {
  1464. /* CLKOUT */
  1465. RCAR_GP_PIN(4, 23),
  1466. };
  1467. static const unsigned int audio_clkout_c_mux[] = {
  1468. AUDIO_CLKOUT_C_MARK,
  1469. };
  1470. /* - AVB -------------------------------------------------------------------- */
  1471. static const unsigned int avb_link_pins[] = {
  1472. RCAR_GP_PIN(3, 26),
  1473. };
  1474. static const unsigned int avb_link_mux[] = {
  1475. AVB_LINK_MARK,
  1476. };
  1477. static const unsigned int avb_magic_pins[] = {
  1478. RCAR_GP_PIN(3, 27),
  1479. };
  1480. static const unsigned int avb_magic_mux[] = {
  1481. AVB_MAGIC_MARK,
  1482. };
  1483. static const unsigned int avb_phy_int_pins[] = {
  1484. RCAR_GP_PIN(3, 28),
  1485. };
  1486. static const unsigned int avb_phy_int_mux[] = {
  1487. AVB_PHY_INT_MARK,
  1488. };
  1489. static const unsigned int avb_mdio_pins[] = {
  1490. RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
  1491. };
  1492. static const unsigned int avb_mdio_mux[] = {
  1493. AVB_MDC_MARK, AVB_MDIO_MARK,
  1494. };
  1495. static const unsigned int avb_mii_pins[] = {
  1496. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  1497. RCAR_GP_PIN(3, 17),
  1498. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  1499. RCAR_GP_PIN(3, 5),
  1500. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  1501. RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
  1502. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
  1503. };
  1504. static const unsigned int avb_mii_mux[] = {
  1505. AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1506. AVB_TXD3_MARK,
  1507. AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1508. AVB_RXD3_MARK,
  1509. AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
  1510. AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
  1511. AVB_TX_CLK_MARK, AVB_COL_MARK,
  1512. };
  1513. static const unsigned int avb_gmii_pins[] = {
  1514. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  1515. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
  1516. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  1517. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  1518. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  1519. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1520. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  1521. RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
  1522. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
  1523. RCAR_GP_PIN(3, 11),
  1524. };
  1525. static const unsigned int avb_gmii_mux[] = {
  1526. AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1527. AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
  1528. AVB_TXD6_MARK, AVB_TXD7_MARK,
  1529. AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1530. AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
  1531. AVB_RXD6_MARK, AVB_RXD7_MARK,
  1532. AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
  1533. AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
  1534. AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
  1535. AVB_COL_MARK,
  1536. };
  1537. /* - CAN -------------------------------------------------------------------- */
  1538. static const unsigned int can0_data_pins[] = {
  1539. /* TX, RX */
  1540. RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
  1541. };
  1542. static const unsigned int can0_data_mux[] = {
  1543. CAN0_TX_MARK, CAN0_RX_MARK,
  1544. };
  1545. static const unsigned int can0_data_b_pins[] = {
  1546. /* TX, RX */
  1547. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
  1548. };
  1549. static const unsigned int can0_data_b_mux[] = {
  1550. CAN0_TX_B_MARK, CAN0_RX_B_MARK,
  1551. };
  1552. static const unsigned int can0_data_c_pins[] = {
  1553. /* TX, RX */
  1554. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
  1555. };
  1556. static const unsigned int can0_data_c_mux[] = {
  1557. CAN0_TX_C_MARK, CAN0_RX_C_MARK,
  1558. };
  1559. static const unsigned int can0_data_d_pins[] = {
  1560. /* TX, RX */
  1561. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
  1562. };
  1563. static const unsigned int can0_data_d_mux[] = {
  1564. CAN0_TX_D_MARK, CAN0_RX_D_MARK,
  1565. };
  1566. static const unsigned int can1_data_pins[] = {
  1567. /* TX, RX */
  1568. RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
  1569. };
  1570. static const unsigned int can1_data_mux[] = {
  1571. CAN1_TX_MARK, CAN1_RX_MARK,
  1572. };
  1573. static const unsigned int can1_data_b_pins[] = {
  1574. /* TX, RX */
  1575. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
  1576. };
  1577. static const unsigned int can1_data_b_mux[] = {
  1578. CAN1_TX_B_MARK, CAN1_RX_B_MARK,
  1579. };
  1580. static const unsigned int can1_data_c_pins[] = {
  1581. /* TX, RX */
  1582. RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
  1583. };
  1584. static const unsigned int can1_data_c_mux[] = {
  1585. CAN1_TX_C_MARK, CAN1_RX_C_MARK,
  1586. };
  1587. static const unsigned int can1_data_d_pins[] = {
  1588. /* TX, RX */
  1589. RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
  1590. };
  1591. static const unsigned int can1_data_d_mux[] = {
  1592. CAN1_TX_D_MARK, CAN1_RX_D_MARK,
  1593. };
  1594. static const unsigned int can_clk_pins[] = {
  1595. /* CLK */
  1596. RCAR_GP_PIN(3, 31),
  1597. };
  1598. static const unsigned int can_clk_mux[] = {
  1599. CAN_CLK_MARK,
  1600. };
  1601. static const unsigned int can_clk_b_pins[] = {
  1602. /* CLK */
  1603. RCAR_GP_PIN(1, 23),
  1604. };
  1605. static const unsigned int can_clk_b_mux[] = {
  1606. CAN_CLK_B_MARK,
  1607. };
  1608. static const unsigned int can_clk_c_pins[] = {
  1609. /* CLK */
  1610. RCAR_GP_PIN(1, 0),
  1611. };
  1612. static const unsigned int can_clk_c_mux[] = {
  1613. CAN_CLK_C_MARK,
  1614. };
  1615. static const unsigned int can_clk_d_pins[] = {
  1616. /* CLK */
  1617. RCAR_GP_PIN(5, 0),
  1618. };
  1619. static const unsigned int can_clk_d_mux[] = {
  1620. CAN_CLK_D_MARK,
  1621. };
  1622. /* - DU --------------------------------------------------------------------- */
  1623. static const unsigned int du0_rgb666_pins[] = {
  1624. /* R[7:2], G[7:2], B[7:2] */
  1625. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
  1626. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1627. RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1628. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1629. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  1630. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
  1631. };
  1632. static const unsigned int du0_rgb666_mux[] = {
  1633. DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
  1634. DU0_DR3_MARK, DU0_DR2_MARK,
  1635. DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
  1636. DU0_DG3_MARK, DU0_DG2_MARK,
  1637. DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
  1638. DU0_DB3_MARK, DU0_DB2_MARK,
  1639. };
  1640. static const unsigned int du0_rgb888_pins[] = {
  1641. /* R[7:0], G[7:0], B[7:0] */
  1642. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
  1643. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1644. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
  1645. RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1646. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1647. RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
  1648. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  1649. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
  1650. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
  1651. };
  1652. static const unsigned int du0_rgb888_mux[] = {
  1653. DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
  1654. DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
  1655. DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
  1656. DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
  1657. DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
  1658. DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
  1659. };
  1660. static const unsigned int du0_clk0_out_pins[] = {
  1661. /* DOTCLKOUT0 */
  1662. RCAR_GP_PIN(2, 25),
  1663. };
  1664. static const unsigned int du0_clk0_out_mux[] = {
  1665. DU0_DOTCLKOUT0_MARK
  1666. };
  1667. static const unsigned int du0_clk1_out_pins[] = {
  1668. /* DOTCLKOUT1 */
  1669. RCAR_GP_PIN(2, 26),
  1670. };
  1671. static const unsigned int du0_clk1_out_mux[] = {
  1672. DU0_DOTCLKOUT1_MARK
  1673. };
  1674. static const unsigned int du0_clk_in_pins[] = {
  1675. /* CLKIN */
  1676. RCAR_GP_PIN(2, 24),
  1677. };
  1678. static const unsigned int du0_clk_in_mux[] = {
  1679. DU0_DOTCLKIN_MARK
  1680. };
  1681. static const unsigned int du0_sync_pins[] = {
  1682. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1683. RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
  1684. };
  1685. static const unsigned int du0_sync_mux[] = {
  1686. DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
  1687. };
  1688. static const unsigned int du0_oddf_pins[] = {
  1689. /* EXODDF/ODDF/DISP/CDE */
  1690. RCAR_GP_PIN(2, 29),
  1691. };
  1692. static const unsigned int du0_oddf_mux[] = {
  1693. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
  1694. };
  1695. static const unsigned int du0_cde_pins[] = {
  1696. /* CDE */
  1697. RCAR_GP_PIN(2, 31),
  1698. };
  1699. static const unsigned int du0_cde_mux[] = {
  1700. DU0_CDE_MARK,
  1701. };
  1702. static const unsigned int du0_disp_pins[] = {
  1703. /* DISP */
  1704. RCAR_GP_PIN(2, 30),
  1705. };
  1706. static const unsigned int du0_disp_mux[] = {
  1707. DU0_DISP_MARK
  1708. };
  1709. static const unsigned int du1_rgb666_pins[] = {
  1710. /* R[7:2], G[7:2], B[7:2] */
  1711. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
  1712. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1713. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
  1714. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
  1715. RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
  1716. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
  1717. };
  1718. static const unsigned int du1_rgb666_mux[] = {
  1719. DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
  1720. DU1_DR3_MARK, DU1_DR2_MARK,
  1721. DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
  1722. DU1_DG3_MARK, DU1_DG2_MARK,
  1723. DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
  1724. DU1_DB3_MARK, DU1_DB2_MARK,
  1725. };
  1726. static const unsigned int du1_rgb888_pins[] = {
  1727. /* R[7:0], G[7:0], B[7:0] */
  1728. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
  1729. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1730. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
  1731. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
  1732. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
  1733. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
  1734. RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
  1735. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
  1736. RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
  1737. };
  1738. static const unsigned int du1_rgb888_mux[] = {
  1739. DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
  1740. DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
  1741. DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
  1742. DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
  1743. DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
  1744. DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
  1745. };
  1746. static const unsigned int du1_clk0_out_pins[] = {
  1747. /* DOTCLKOUT0 */
  1748. RCAR_GP_PIN(4, 25),
  1749. };
  1750. static const unsigned int du1_clk0_out_mux[] = {
  1751. DU1_DOTCLKOUT0_MARK
  1752. };
  1753. static const unsigned int du1_clk1_out_pins[] = {
  1754. /* DOTCLKOUT1 */
  1755. RCAR_GP_PIN(4, 26),
  1756. };
  1757. static const unsigned int du1_clk1_out_mux[] = {
  1758. DU1_DOTCLKOUT1_MARK
  1759. };
  1760. static const unsigned int du1_clk_in_pins[] = {
  1761. /* DOTCLKIN */
  1762. RCAR_GP_PIN(4, 24),
  1763. };
  1764. static const unsigned int du1_clk_in_mux[] = {
  1765. DU1_DOTCLKIN_MARK
  1766. };
  1767. static const unsigned int du1_sync_pins[] = {
  1768. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1769. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
  1770. };
  1771. static const unsigned int du1_sync_mux[] = {
  1772. DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
  1773. };
  1774. static const unsigned int du1_oddf_pins[] = {
  1775. /* EXODDF/ODDF/DISP/CDE */
  1776. RCAR_GP_PIN(4, 29),
  1777. };
  1778. static const unsigned int du1_oddf_mux[] = {
  1779. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  1780. };
  1781. static const unsigned int du1_cde_pins[] = {
  1782. /* CDE */
  1783. RCAR_GP_PIN(4, 31),
  1784. };
  1785. static const unsigned int du1_cde_mux[] = {
  1786. DU1_CDE_MARK
  1787. };
  1788. static const unsigned int du1_disp_pins[] = {
  1789. /* DISP */
  1790. RCAR_GP_PIN(4, 30),
  1791. };
  1792. static const unsigned int du1_disp_mux[] = {
  1793. DU1_DISP_MARK
  1794. };
  1795. /* - ETH -------------------------------------------------------------------- */
  1796. static const unsigned int eth_link_pins[] = {
  1797. /* LINK */
  1798. RCAR_GP_PIN(3, 18),
  1799. };
  1800. static const unsigned int eth_link_mux[] = {
  1801. ETH_LINK_MARK,
  1802. };
  1803. static const unsigned int eth_magic_pins[] = {
  1804. /* MAGIC */
  1805. RCAR_GP_PIN(3, 22),
  1806. };
  1807. static const unsigned int eth_magic_mux[] = {
  1808. ETH_MAGIC_MARK,
  1809. };
  1810. static const unsigned int eth_mdio_pins[] = {
  1811. /* MDC, MDIO */
  1812. RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
  1813. };
  1814. static const unsigned int eth_mdio_mux[] = {
  1815. ETH_MDC_MARK, ETH_MDIO_MARK,
  1816. };
  1817. static const unsigned int eth_rmii_pins[] = {
  1818. /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
  1819. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
  1820. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
  1821. RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
  1822. };
  1823. static const unsigned int eth_rmii_mux[] = {
  1824. ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
  1825. ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
  1826. };
  1827. static const unsigned int eth_link_b_pins[] = {
  1828. /* LINK */
  1829. RCAR_GP_PIN(5, 15),
  1830. };
  1831. static const unsigned int eth_link_b_mux[] = {
  1832. ETH_LINK_B_MARK,
  1833. };
  1834. static const unsigned int eth_magic_b_pins[] = {
  1835. /* MAGIC */
  1836. RCAR_GP_PIN(5, 19),
  1837. };
  1838. static const unsigned int eth_magic_b_mux[] = {
  1839. ETH_MAGIC_B_MARK,
  1840. };
  1841. static const unsigned int eth_mdio_b_pins[] = {
  1842. /* MDC, MDIO */
  1843. RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
  1844. };
  1845. static const unsigned int eth_mdio_b_mux[] = {
  1846. ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
  1847. };
  1848. static const unsigned int eth_rmii_b_pins[] = {
  1849. /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
  1850. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
  1851. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
  1852. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
  1853. };
  1854. static const unsigned int eth_rmii_b_mux[] = {
  1855. ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
  1856. ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
  1857. };
  1858. /* - HSCIF0 ----------------------------------------------------------------- */
  1859. static const unsigned int hscif0_data_pins[] = {
  1860. /* RX, TX */
  1861. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  1862. };
  1863. static const unsigned int hscif0_data_mux[] = {
  1864. HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
  1865. };
  1866. static const unsigned int hscif0_clk_pins[] = {
  1867. /* SCK */
  1868. RCAR_GP_PIN(3, 29),
  1869. };
  1870. static const unsigned int hscif0_clk_mux[] = {
  1871. HSCIF0_HSCK_MARK,
  1872. };
  1873. static const unsigned int hscif0_ctrl_pins[] = {
  1874. /* RTS, CTS */
  1875. RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
  1876. };
  1877. static const unsigned int hscif0_ctrl_mux[] = {
  1878. HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
  1879. };
  1880. static const unsigned int hscif0_data_b_pins[] = {
  1881. /* RX, TX */
  1882. RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
  1883. };
  1884. static const unsigned int hscif0_data_b_mux[] = {
  1885. HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
  1886. };
  1887. static const unsigned int hscif0_clk_b_pins[] = {
  1888. /* SCK */
  1889. RCAR_GP_PIN(1, 0),
  1890. };
  1891. static const unsigned int hscif0_clk_b_mux[] = {
  1892. HSCIF0_HSCK_B_MARK,
  1893. };
  1894. /* - HSCIF1 ----------------------------------------------------------------- */
  1895. static const unsigned int hscif1_data_pins[] = {
  1896. /* RX, TX */
  1897. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  1898. };
  1899. static const unsigned int hscif1_data_mux[] = {
  1900. HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
  1901. };
  1902. static const unsigned int hscif1_clk_pins[] = {
  1903. /* SCK */
  1904. RCAR_GP_PIN(4, 10),
  1905. };
  1906. static const unsigned int hscif1_clk_mux[] = {
  1907. HSCIF1_HSCK_MARK,
  1908. };
  1909. static const unsigned int hscif1_ctrl_pins[] = {
  1910. /* RTS, CTS */
  1911. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
  1912. };
  1913. static const unsigned int hscif1_ctrl_mux[] = {
  1914. HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
  1915. };
  1916. static const unsigned int hscif1_data_b_pins[] = {
  1917. /* RX, TX */
  1918. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1919. };
  1920. static const unsigned int hscif1_data_b_mux[] = {
  1921. HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
  1922. };
  1923. static const unsigned int hscif1_ctrl_b_pins[] = {
  1924. /* RTS, CTS */
  1925. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
  1926. };
  1927. static const unsigned int hscif1_ctrl_b_mux[] = {
  1928. HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
  1929. };
  1930. /* - HSCIF2 ----------------------------------------------------------------- */
  1931. static const unsigned int hscif2_data_pins[] = {
  1932. /* RX, TX */
  1933. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  1934. };
  1935. static const unsigned int hscif2_data_mux[] = {
  1936. HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
  1937. };
  1938. static const unsigned int hscif2_clk_pins[] = {
  1939. /* SCK */
  1940. RCAR_GP_PIN(0, 10),
  1941. };
  1942. static const unsigned int hscif2_clk_mux[] = {
  1943. HSCIF2_HSCK_MARK,
  1944. };
  1945. static const unsigned int hscif2_ctrl_pins[] = {
  1946. /* RTS, CTS */
  1947. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
  1948. };
  1949. static const unsigned int hscif2_ctrl_mux[] = {
  1950. HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
  1951. };
  1952. /* - I2C0 ------------------------------------------------------------------- */
  1953. static const unsigned int i2c0_pins[] = {
  1954. /* SCL, SDA */
  1955. RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
  1956. };
  1957. static const unsigned int i2c0_mux[] = {
  1958. I2C0_SCL_MARK, I2C0_SDA_MARK,
  1959. };
  1960. static const unsigned int i2c0_b_pins[] = {
  1961. /* SCL, SDA */
  1962. RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
  1963. };
  1964. static const unsigned int i2c0_b_mux[] = {
  1965. I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
  1966. };
  1967. static const unsigned int i2c0_c_pins[] = {
  1968. /* SCL, SDA */
  1969. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  1970. };
  1971. static const unsigned int i2c0_c_mux[] = {
  1972. I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
  1973. };
  1974. static const unsigned int i2c0_d_pins[] = {
  1975. /* SCL, SDA */
  1976. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  1977. };
  1978. static const unsigned int i2c0_d_mux[] = {
  1979. I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
  1980. };
  1981. static const unsigned int i2c0_e_pins[] = {
  1982. /* SCL, SDA */
  1983. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  1984. };
  1985. static const unsigned int i2c0_e_mux[] = {
  1986. I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
  1987. };
  1988. /* - I2C1 ------------------------------------------------------------------- */
  1989. static const unsigned int i2c1_pins[] = {
  1990. /* SCL, SDA */
  1991. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  1992. };
  1993. static const unsigned int i2c1_mux[] = {
  1994. I2C1_SCL_MARK, I2C1_SDA_MARK,
  1995. };
  1996. static const unsigned int i2c1_b_pins[] = {
  1997. /* SCL, SDA */
  1998. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  1999. };
  2000. static const unsigned int i2c1_b_mux[] = {
  2001. I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
  2002. };
  2003. static const unsigned int i2c1_c_pins[] = {
  2004. /* SCL, SDA */
  2005. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  2006. };
  2007. static const unsigned int i2c1_c_mux[] = {
  2008. I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
  2009. };
  2010. static const unsigned int i2c1_d_pins[] = {
  2011. /* SCL, SDA */
  2012. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
  2013. };
  2014. static const unsigned int i2c1_d_mux[] = {
  2015. I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
  2016. };
  2017. static const unsigned int i2c1_e_pins[] = {
  2018. /* SCL, SDA */
  2019. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  2020. };
  2021. static const unsigned int i2c1_e_mux[] = {
  2022. I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
  2023. };
  2024. /* - I2C2 ------------------------------------------------------------------- */
  2025. static const unsigned int i2c2_pins[] = {
  2026. /* SCL, SDA */
  2027. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  2028. };
  2029. static const unsigned int i2c2_mux[] = {
  2030. I2C2_SCL_MARK, I2C2_SDA_MARK,
  2031. };
  2032. static const unsigned int i2c2_b_pins[] = {
  2033. /* SCL, SDA */
  2034. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  2035. };
  2036. static const unsigned int i2c2_b_mux[] = {
  2037. I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
  2038. };
  2039. static const unsigned int i2c2_c_pins[] = {
  2040. /* SCL, SDA */
  2041. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  2042. };
  2043. static const unsigned int i2c2_c_mux[] = {
  2044. I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
  2045. };
  2046. static const unsigned int i2c2_d_pins[] = {
  2047. /* SCL, SDA */
  2048. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  2049. };
  2050. static const unsigned int i2c2_d_mux[] = {
  2051. I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
  2052. };
  2053. static const unsigned int i2c2_e_pins[] = {
  2054. /* SCL, SDA */
  2055. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
  2056. };
  2057. static const unsigned int i2c2_e_mux[] = {
  2058. I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
  2059. };
  2060. /* - I2C3 ------------------------------------------------------------------- */
  2061. static const unsigned int i2c3_pins[] = {
  2062. /* SCL, SDA */
  2063. RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
  2064. };
  2065. static const unsigned int i2c3_mux[] = {
  2066. I2C3_SCL_MARK, I2C3_SDA_MARK,
  2067. };
  2068. static const unsigned int i2c3_b_pins[] = {
  2069. /* SCL, SDA */
  2070. RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
  2071. };
  2072. static const unsigned int i2c3_b_mux[] = {
  2073. I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
  2074. };
  2075. static const unsigned int i2c3_c_pins[] = {
  2076. /* SCL, SDA */
  2077. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
  2078. };
  2079. static const unsigned int i2c3_c_mux[] = {
  2080. I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
  2081. };
  2082. static const unsigned int i2c3_d_pins[] = {
  2083. /* SCL, SDA */
  2084. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  2085. };
  2086. static const unsigned int i2c3_d_mux[] = {
  2087. I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
  2088. };
  2089. static const unsigned int i2c3_e_pins[] = {
  2090. /* SCL, SDA */
  2091. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  2092. };
  2093. static const unsigned int i2c3_e_mux[] = {
  2094. I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
  2095. };
  2096. /* - I2C4 ------------------------------------------------------------------- */
  2097. static const unsigned int i2c4_pins[] = {
  2098. /* SCL, SDA */
  2099. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  2100. };
  2101. static const unsigned int i2c4_mux[] = {
  2102. I2C4_SCL_MARK, I2C4_SDA_MARK,
  2103. };
  2104. static const unsigned int i2c4_b_pins[] = {
  2105. /* SCL, SDA */
  2106. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  2107. };
  2108. static const unsigned int i2c4_b_mux[] = {
  2109. I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
  2110. };
  2111. static const unsigned int i2c4_c_pins[] = {
  2112. /* SCL, SDA */
  2113. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2114. };
  2115. static const unsigned int i2c4_c_mux[] = {
  2116. I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
  2117. };
  2118. static const unsigned int i2c4_d_pins[] = {
  2119. /* SCL, SDA */
  2120. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  2121. };
  2122. static const unsigned int i2c4_d_mux[] = {
  2123. I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
  2124. };
  2125. static const unsigned int i2c4_e_pins[] = {
  2126. /* SCL, SDA */
  2127. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  2128. };
  2129. static const unsigned int i2c4_e_mux[] = {
  2130. I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
  2131. };
  2132. /* - I2C5 ------------------------------------------------------------------- */
  2133. static const unsigned int i2c5_pins[] = {
  2134. /* SCL, SDA */
  2135. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  2136. };
  2137. static const unsigned int i2c5_mux[] = {
  2138. I2C5_SCL_MARK, I2C5_SDA_MARK,
  2139. };
  2140. static const unsigned int i2c5_b_pins[] = {
  2141. /* SCL, SDA */
  2142. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2143. };
  2144. static const unsigned int i2c5_b_mux[] = {
  2145. I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
  2146. };
  2147. static const unsigned int i2c5_c_pins[] = {
  2148. /* SCL, SDA */
  2149. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
  2150. };
  2151. static const unsigned int i2c5_c_mux[] = {
  2152. I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
  2153. };
  2154. static const unsigned int i2c5_d_pins[] = {
  2155. /* SCL, SDA */
  2156. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  2157. };
  2158. static const unsigned int i2c5_d_mux[] = {
  2159. I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
  2160. };
  2161. /* - INTC ------------------------------------------------------------------- */
  2162. static const unsigned int intc_irq0_pins[] = {
  2163. /* IRQ0 */
  2164. RCAR_GP_PIN(4, 4),
  2165. };
  2166. static const unsigned int intc_irq0_mux[] = {
  2167. IRQ0_MARK,
  2168. };
  2169. static const unsigned int intc_irq1_pins[] = {
  2170. /* IRQ1 */
  2171. RCAR_GP_PIN(4, 18),
  2172. };
  2173. static const unsigned int intc_irq1_mux[] = {
  2174. IRQ1_MARK,
  2175. };
  2176. static const unsigned int intc_irq2_pins[] = {
  2177. /* IRQ2 */
  2178. RCAR_GP_PIN(4, 19),
  2179. };
  2180. static const unsigned int intc_irq2_mux[] = {
  2181. IRQ2_MARK,
  2182. };
  2183. static const unsigned int intc_irq3_pins[] = {
  2184. /* IRQ3 */
  2185. RCAR_GP_PIN(0, 7),
  2186. };
  2187. static const unsigned int intc_irq3_mux[] = {
  2188. IRQ3_MARK,
  2189. };
  2190. static const unsigned int intc_irq4_pins[] = {
  2191. /* IRQ4 */
  2192. RCAR_GP_PIN(0, 0),
  2193. };
  2194. static const unsigned int intc_irq4_mux[] = {
  2195. IRQ4_MARK,
  2196. };
  2197. static const unsigned int intc_irq5_pins[] = {
  2198. /* IRQ5 */
  2199. RCAR_GP_PIN(4, 1),
  2200. };
  2201. static const unsigned int intc_irq5_mux[] = {
  2202. IRQ5_MARK,
  2203. };
  2204. static const unsigned int intc_irq6_pins[] = {
  2205. /* IRQ6 */
  2206. RCAR_GP_PIN(0, 10),
  2207. };
  2208. static const unsigned int intc_irq6_mux[] = {
  2209. IRQ6_MARK,
  2210. };
  2211. static const unsigned int intc_irq7_pins[] = {
  2212. /* IRQ7 */
  2213. RCAR_GP_PIN(6, 15),
  2214. };
  2215. static const unsigned int intc_irq7_mux[] = {
  2216. IRQ7_MARK,
  2217. };
  2218. static const unsigned int intc_irq8_pins[] = {
  2219. /* IRQ8 */
  2220. RCAR_GP_PIN(5, 0),
  2221. };
  2222. static const unsigned int intc_irq8_mux[] = {
  2223. IRQ8_MARK,
  2224. };
  2225. static const unsigned int intc_irq9_pins[] = {
  2226. /* IRQ9 */
  2227. RCAR_GP_PIN(5, 10),
  2228. };
  2229. static const unsigned int intc_irq9_mux[] = {
  2230. IRQ9_MARK,
  2231. };
  2232. /* - MMCIF ------------------------------------------------------------------ */
  2233. static const unsigned int mmc_data1_pins[] = {
  2234. /* D[0] */
  2235. RCAR_GP_PIN(6, 18),
  2236. };
  2237. static const unsigned int mmc_data1_mux[] = {
  2238. MMC_D0_MARK,
  2239. };
  2240. static const unsigned int mmc_data4_pins[] = {
  2241. /* D[0:3] */
  2242. RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
  2243. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
  2244. };
  2245. static const unsigned int mmc_data4_mux[] = {
  2246. MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
  2247. };
  2248. static const unsigned int mmc_data8_pins[] = {
  2249. /* D[0:7] */
  2250. RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
  2251. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
  2252. RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
  2253. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  2254. };
  2255. static const unsigned int mmc_data8_mux[] = {
  2256. MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
  2257. MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
  2258. };
  2259. static const unsigned int mmc_ctrl_pins[] = {
  2260. /* CLK, CMD */
  2261. RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
  2262. };
  2263. static const unsigned int mmc_ctrl_mux[] = {
  2264. MMC_CLK_MARK, MMC_CMD_MARK,
  2265. };
  2266. /* - MSIOF0 ----------------------------------------------------------------- */
  2267. static const unsigned int msiof0_clk_pins[] = {
  2268. /* SCK */
  2269. RCAR_GP_PIN(4, 4),
  2270. };
  2271. static const unsigned int msiof0_clk_mux[] = {
  2272. MSIOF0_SCK_MARK,
  2273. };
  2274. static const unsigned int msiof0_sync_pins[] = {
  2275. /* SYNC */
  2276. RCAR_GP_PIN(4, 5),
  2277. };
  2278. static const unsigned int msiof0_sync_mux[] = {
  2279. MSIOF0_SYNC_MARK,
  2280. };
  2281. static const unsigned int msiof0_ss1_pins[] = {
  2282. /* SS1 */
  2283. RCAR_GP_PIN(4, 6),
  2284. };
  2285. static const unsigned int msiof0_ss1_mux[] = {
  2286. MSIOF0_SS1_MARK,
  2287. };
  2288. static const unsigned int msiof0_ss2_pins[] = {
  2289. /* SS2 */
  2290. RCAR_GP_PIN(4, 7),
  2291. };
  2292. static const unsigned int msiof0_ss2_mux[] = {
  2293. MSIOF0_SS2_MARK,
  2294. };
  2295. static const unsigned int msiof0_rx_pins[] = {
  2296. /* RXD */
  2297. RCAR_GP_PIN(4, 2),
  2298. };
  2299. static const unsigned int msiof0_rx_mux[] = {
  2300. MSIOF0_RXD_MARK,
  2301. };
  2302. static const unsigned int msiof0_tx_pins[] = {
  2303. /* TXD */
  2304. RCAR_GP_PIN(4, 3),
  2305. };
  2306. static const unsigned int msiof0_tx_mux[] = {
  2307. MSIOF0_TXD_MARK,
  2308. };
  2309. /* - MSIOF1 ----------------------------------------------------------------- */
  2310. static const unsigned int msiof1_clk_pins[] = {
  2311. /* SCK */
  2312. RCAR_GP_PIN(0, 26),
  2313. };
  2314. static const unsigned int msiof1_clk_mux[] = {
  2315. MSIOF1_SCK_MARK,
  2316. };
  2317. static const unsigned int msiof1_sync_pins[] = {
  2318. /* SYNC */
  2319. RCAR_GP_PIN(0, 27),
  2320. };
  2321. static const unsigned int msiof1_sync_mux[] = {
  2322. MSIOF1_SYNC_MARK,
  2323. };
  2324. static const unsigned int msiof1_ss1_pins[] = {
  2325. /* SS1 */
  2326. RCAR_GP_PIN(0, 28),
  2327. };
  2328. static const unsigned int msiof1_ss1_mux[] = {
  2329. MSIOF1_SS1_MARK,
  2330. };
  2331. static const unsigned int msiof1_ss2_pins[] = {
  2332. /* SS2 */
  2333. RCAR_GP_PIN(0, 29),
  2334. };
  2335. static const unsigned int msiof1_ss2_mux[] = {
  2336. MSIOF1_SS2_MARK,
  2337. };
  2338. static const unsigned int msiof1_rx_pins[] = {
  2339. /* RXD */
  2340. RCAR_GP_PIN(0, 24),
  2341. };
  2342. static const unsigned int msiof1_rx_mux[] = {
  2343. MSIOF1_RXD_MARK,
  2344. };
  2345. static const unsigned int msiof1_tx_pins[] = {
  2346. /* TXD */
  2347. RCAR_GP_PIN(0, 25),
  2348. };
  2349. static const unsigned int msiof1_tx_mux[] = {
  2350. MSIOF1_TXD_MARK,
  2351. };
  2352. static const unsigned int msiof1_clk_b_pins[] = {
  2353. /* SCK */
  2354. RCAR_GP_PIN(5, 3),
  2355. };
  2356. static const unsigned int msiof1_clk_b_mux[] = {
  2357. MSIOF1_SCK_B_MARK,
  2358. };
  2359. static const unsigned int msiof1_sync_b_pins[] = {
  2360. /* SYNC */
  2361. RCAR_GP_PIN(5, 4),
  2362. };
  2363. static const unsigned int msiof1_sync_b_mux[] = {
  2364. MSIOF1_SYNC_B_MARK,
  2365. };
  2366. static const unsigned int msiof1_ss1_b_pins[] = {
  2367. /* SS1 */
  2368. RCAR_GP_PIN(5, 5),
  2369. };
  2370. static const unsigned int msiof1_ss1_b_mux[] = {
  2371. MSIOF1_SS1_B_MARK,
  2372. };
  2373. static const unsigned int msiof1_ss2_b_pins[] = {
  2374. /* SS2 */
  2375. RCAR_GP_PIN(5, 6),
  2376. };
  2377. static const unsigned int msiof1_ss2_b_mux[] = {
  2378. MSIOF1_SS2_B_MARK,
  2379. };
  2380. static const unsigned int msiof1_rx_b_pins[] = {
  2381. /* RXD */
  2382. RCAR_GP_PIN(5, 1),
  2383. };
  2384. static const unsigned int msiof1_rx_b_mux[] = {
  2385. MSIOF1_RXD_B_MARK,
  2386. };
  2387. static const unsigned int msiof1_tx_b_pins[] = {
  2388. /* TXD */
  2389. RCAR_GP_PIN(5, 2),
  2390. };
  2391. static const unsigned int msiof1_tx_b_mux[] = {
  2392. MSIOF1_TXD_B_MARK,
  2393. };
  2394. /* - MSIOF2 ----------------------------------------------------------------- */
  2395. static const unsigned int msiof2_clk_pins[] = {
  2396. /* SCK */
  2397. RCAR_GP_PIN(1, 0),
  2398. };
  2399. static const unsigned int msiof2_clk_mux[] = {
  2400. MSIOF2_SCK_MARK,
  2401. };
  2402. static const unsigned int msiof2_sync_pins[] = {
  2403. /* SYNC */
  2404. RCAR_GP_PIN(1, 1),
  2405. };
  2406. static const unsigned int msiof2_sync_mux[] = {
  2407. MSIOF2_SYNC_MARK,
  2408. };
  2409. static const unsigned int msiof2_ss1_pins[] = {
  2410. /* SS1 */
  2411. RCAR_GP_PIN(1, 2),
  2412. };
  2413. static const unsigned int msiof2_ss1_mux[] = {
  2414. MSIOF2_SS1_MARK,
  2415. };
  2416. static const unsigned int msiof2_ss2_pins[] = {
  2417. /* SS2 */
  2418. RCAR_GP_PIN(1, 3),
  2419. };
  2420. static const unsigned int msiof2_ss2_mux[] = {
  2421. MSIOF2_SS2_MARK,
  2422. };
  2423. static const unsigned int msiof2_rx_pins[] = {
  2424. /* RXD */
  2425. RCAR_GP_PIN(0, 30),
  2426. };
  2427. static const unsigned int msiof2_rx_mux[] = {
  2428. MSIOF2_RXD_MARK,
  2429. };
  2430. static const unsigned int msiof2_tx_pins[] = {
  2431. /* TXD */
  2432. RCAR_GP_PIN(0, 31),
  2433. };
  2434. static const unsigned int msiof2_tx_mux[] = {
  2435. MSIOF2_TXD_MARK,
  2436. };
  2437. static const unsigned int msiof2_clk_b_pins[] = {
  2438. /* SCK */
  2439. RCAR_GP_PIN(3, 15),
  2440. };
  2441. static const unsigned int msiof2_clk_b_mux[] = {
  2442. MSIOF2_SCK_B_MARK,
  2443. };
  2444. static const unsigned int msiof2_sync_b_pins[] = {
  2445. /* SYNC */
  2446. RCAR_GP_PIN(3, 16),
  2447. };
  2448. static const unsigned int msiof2_sync_b_mux[] = {
  2449. MSIOF2_SYNC_B_MARK,
  2450. };
  2451. static const unsigned int msiof2_ss1_b_pins[] = {
  2452. /* SS1 */
  2453. RCAR_GP_PIN(3, 17),
  2454. };
  2455. static const unsigned int msiof2_ss1_b_mux[] = {
  2456. MSIOF2_SS1_B_MARK,
  2457. };
  2458. static const unsigned int msiof2_ss2_b_pins[] = {
  2459. /* SS2 */
  2460. RCAR_GP_PIN(3, 18),
  2461. };
  2462. static const unsigned int msiof2_ss2_b_mux[] = {
  2463. MSIOF2_SS2_B_MARK,
  2464. };
  2465. static const unsigned int msiof2_rx_b_pins[] = {
  2466. /* RXD */
  2467. RCAR_GP_PIN(3, 13),
  2468. };
  2469. static const unsigned int msiof2_rx_b_mux[] = {
  2470. MSIOF2_RXD_B_MARK,
  2471. };
  2472. static const unsigned int msiof2_tx_b_pins[] = {
  2473. /* TXD */
  2474. RCAR_GP_PIN(3, 14),
  2475. };
  2476. static const unsigned int msiof2_tx_b_mux[] = {
  2477. MSIOF2_TXD_B_MARK,
  2478. };
  2479. /* - PWM -------------------------------------------------------------------- */
  2480. static const unsigned int pwm0_pins[] = {
  2481. RCAR_GP_PIN(1, 14),
  2482. };
  2483. static const unsigned int pwm0_mux[] = {
  2484. PWM0_MARK,
  2485. };
  2486. static const unsigned int pwm0_b_pins[] = {
  2487. RCAR_GP_PIN(5, 3),
  2488. };
  2489. static const unsigned int pwm0_b_mux[] = {
  2490. PWM0_B_MARK,
  2491. };
  2492. static const unsigned int pwm1_pins[] = {
  2493. RCAR_GP_PIN(4, 5),
  2494. };
  2495. static const unsigned int pwm1_mux[] = {
  2496. PWM1_MARK,
  2497. };
  2498. static const unsigned int pwm1_b_pins[] = {
  2499. RCAR_GP_PIN(5, 10),
  2500. };
  2501. static const unsigned int pwm1_b_mux[] = {
  2502. PWM1_B_MARK,
  2503. };
  2504. static const unsigned int pwm1_c_pins[] = {
  2505. RCAR_GP_PIN(1, 18),
  2506. };
  2507. static const unsigned int pwm1_c_mux[] = {
  2508. PWM1_C_MARK,
  2509. };
  2510. static const unsigned int pwm2_pins[] = {
  2511. RCAR_GP_PIN(4, 10),
  2512. };
  2513. static const unsigned int pwm2_mux[] = {
  2514. PWM2_MARK,
  2515. };
  2516. static const unsigned int pwm2_b_pins[] = {
  2517. RCAR_GP_PIN(5, 17),
  2518. };
  2519. static const unsigned int pwm2_b_mux[] = {
  2520. PWM2_B_MARK,
  2521. };
  2522. static const unsigned int pwm2_c_pins[] = {
  2523. RCAR_GP_PIN(0, 13),
  2524. };
  2525. static const unsigned int pwm2_c_mux[] = {
  2526. PWM2_C_MARK,
  2527. };
  2528. static const unsigned int pwm3_pins[] = {
  2529. RCAR_GP_PIN(4, 13),
  2530. };
  2531. static const unsigned int pwm3_mux[] = {
  2532. PWM3_MARK,
  2533. };
  2534. static const unsigned int pwm3_b_pins[] = {
  2535. RCAR_GP_PIN(0, 16),
  2536. };
  2537. static const unsigned int pwm3_b_mux[] = {
  2538. PWM3_B_MARK,
  2539. };
  2540. static const unsigned int pwm4_pins[] = {
  2541. RCAR_GP_PIN(1, 3),
  2542. };
  2543. static const unsigned int pwm4_mux[] = {
  2544. PWM4_MARK,
  2545. };
  2546. static const unsigned int pwm4_b_pins[] = {
  2547. RCAR_GP_PIN(0, 21),
  2548. };
  2549. static const unsigned int pwm4_b_mux[] = {
  2550. PWM4_B_MARK,
  2551. };
  2552. static const unsigned int pwm5_pins[] = {
  2553. RCAR_GP_PIN(3, 30),
  2554. };
  2555. static const unsigned int pwm5_mux[] = {
  2556. PWM5_MARK,
  2557. };
  2558. static const unsigned int pwm5_b_pins[] = {
  2559. RCAR_GP_PIN(4, 0),
  2560. };
  2561. static const unsigned int pwm5_b_mux[] = {
  2562. PWM5_B_MARK,
  2563. };
  2564. static const unsigned int pwm5_c_pins[] = {
  2565. RCAR_GP_PIN(0, 10),
  2566. };
  2567. static const unsigned int pwm5_c_mux[] = {
  2568. PWM5_C_MARK,
  2569. };
  2570. static const unsigned int pwm6_pins[] = {
  2571. RCAR_GP_PIN(4, 8),
  2572. };
  2573. static const unsigned int pwm6_mux[] = {
  2574. PWM6_MARK,
  2575. };
  2576. static const unsigned int pwm6_b_pins[] = {
  2577. RCAR_GP_PIN(0, 7),
  2578. };
  2579. static const unsigned int pwm6_b_mux[] = {
  2580. PWM6_B_MARK,
  2581. };
  2582. /* - QSPI ------------------------------------------------------------------- */
  2583. static const unsigned int qspi_ctrl_pins[] = {
  2584. /* SPCLK, SSL */
  2585. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
  2586. };
  2587. static const unsigned int qspi_ctrl_mux[] = {
  2588. SPCLK_MARK, SSL_MARK,
  2589. };
  2590. static const unsigned int qspi_data2_pins[] = {
  2591. /* MOSI_IO0, MISO_IO1 */
  2592. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  2593. };
  2594. static const unsigned int qspi_data2_mux[] = {
  2595. MOSI_IO0_MARK, MISO_IO1_MARK,
  2596. };
  2597. static const unsigned int qspi_data4_pins[] = {
  2598. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  2599. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  2600. RCAR_GP_PIN(1, 8),
  2601. };
  2602. static const unsigned int qspi_data4_mux[] = {
  2603. MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
  2604. };
  2605. /* - SCIF0 ------------------------------------------------------------------ */
  2606. static const unsigned int scif0_data_pins[] = {
  2607. /* RX, TX */
  2608. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  2609. };
  2610. static const unsigned int scif0_data_mux[] = {
  2611. SCIF0_RXD_MARK, SCIF0_TXD_MARK,
  2612. };
  2613. static const unsigned int scif0_data_b_pins[] = {
  2614. /* RX, TX */
  2615. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  2616. };
  2617. static const unsigned int scif0_data_b_mux[] = {
  2618. SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
  2619. };
  2620. static const unsigned int scif0_data_c_pins[] = {
  2621. /* RX, TX */
  2622. RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
  2623. };
  2624. static const unsigned int scif0_data_c_mux[] = {
  2625. SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
  2626. };
  2627. static const unsigned int scif0_data_d_pins[] = {
  2628. /* RX, TX */
  2629. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  2630. };
  2631. static const unsigned int scif0_data_d_mux[] = {
  2632. SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
  2633. };
  2634. /* - SCIF1 ------------------------------------------------------------------ */
  2635. static const unsigned int scif1_data_pins[] = {
  2636. /* RX, TX */
  2637. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  2638. };
  2639. static const unsigned int scif1_data_mux[] = {
  2640. SCIF1_RXD_MARK, SCIF1_TXD_MARK,
  2641. };
  2642. static const unsigned int scif1_clk_pins[] = {
  2643. /* SCK */
  2644. RCAR_GP_PIN(4, 13),
  2645. };
  2646. static const unsigned int scif1_clk_mux[] = {
  2647. SCIF1_SCK_MARK,
  2648. };
  2649. static const unsigned int scif1_data_b_pins[] = {
  2650. /* RX, TX */
  2651. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
  2652. };
  2653. static const unsigned int scif1_data_b_mux[] = {
  2654. SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
  2655. };
  2656. static const unsigned int scif1_clk_b_pins[] = {
  2657. /* SCK */
  2658. RCAR_GP_PIN(5, 10),
  2659. };
  2660. static const unsigned int scif1_clk_b_mux[] = {
  2661. SCIF1_SCK_B_MARK,
  2662. };
  2663. static const unsigned int scif1_data_c_pins[] = {
  2664. /* RX, TX */
  2665. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
  2666. };
  2667. static const unsigned int scif1_data_c_mux[] = {
  2668. SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
  2669. };
  2670. static const unsigned int scif1_clk_c_pins[] = {
  2671. /* SCK */
  2672. RCAR_GP_PIN(0, 10),
  2673. };
  2674. static const unsigned int scif1_clk_c_mux[] = {
  2675. SCIF1_SCK_C_MARK,
  2676. };
  2677. /* - SCIF2 ------------------------------------------------------------------ */
  2678. static const unsigned int scif2_data_pins[] = {
  2679. /* RX, TX */
  2680. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
  2681. };
  2682. static const unsigned int scif2_data_mux[] = {
  2683. SCIF2_RXD_MARK, SCIF2_TXD_MARK,
  2684. };
  2685. static const unsigned int scif2_clk_pins[] = {
  2686. /* SCK */
  2687. RCAR_GP_PIN(4, 18),
  2688. };
  2689. static const unsigned int scif2_clk_mux[] = {
  2690. SCIF2_SCK_MARK,
  2691. };
  2692. static const unsigned int scif2_data_b_pins[] = {
  2693. /* RX, TX */
  2694. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  2695. };
  2696. static const unsigned int scif2_data_b_mux[] = {
  2697. SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
  2698. };
  2699. static const unsigned int scif2_clk_b_pins[] = {
  2700. /* SCK */
  2701. RCAR_GP_PIN(5, 17),
  2702. };
  2703. static const unsigned int scif2_clk_b_mux[] = {
  2704. SCIF2_SCK_B_MARK,
  2705. };
  2706. static const unsigned int scif2_data_c_pins[] = {
  2707. /* RX, TX */
  2708. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  2709. };
  2710. static const unsigned int scif2_data_c_mux[] = {
  2711. SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
  2712. };
  2713. static const unsigned int scif2_clk_c_pins[] = {
  2714. /* SCK */
  2715. RCAR_GP_PIN(3, 19),
  2716. };
  2717. static const unsigned int scif2_clk_c_mux[] = {
  2718. SCIF2_SCK_C_MARK,
  2719. };
  2720. /* - SCIF3 ------------------------------------------------------------------ */
  2721. static const unsigned int scif3_data_pins[] = {
  2722. /* RX, TX */
  2723. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  2724. };
  2725. static const unsigned int scif3_data_mux[] = {
  2726. SCIF3_RXD_MARK, SCIF3_TXD_MARK,
  2727. };
  2728. static const unsigned int scif3_clk_pins[] = {
  2729. /* SCK */
  2730. RCAR_GP_PIN(4, 19),
  2731. };
  2732. static const unsigned int scif3_clk_mux[] = {
  2733. SCIF3_SCK_MARK,
  2734. };
  2735. static const unsigned int scif3_data_b_pins[] = {
  2736. /* RX, TX */
  2737. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  2738. };
  2739. static const unsigned int scif3_data_b_mux[] = {
  2740. SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
  2741. };
  2742. static const unsigned int scif3_clk_b_pins[] = {
  2743. /* SCK */
  2744. RCAR_GP_PIN(3, 22),
  2745. };
  2746. static const unsigned int scif3_clk_b_mux[] = {
  2747. SCIF3_SCK_B_MARK,
  2748. };
  2749. /* - SCIF4 ------------------------------------------------------------------ */
  2750. static const unsigned int scif4_data_pins[] = {
  2751. /* RX, TX */
  2752. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  2753. };
  2754. static const unsigned int scif4_data_mux[] = {
  2755. SCIF4_RXD_MARK, SCIF4_TXD_MARK,
  2756. };
  2757. static const unsigned int scif4_data_b_pins[] = {
  2758. /* RX, TX */
  2759. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  2760. };
  2761. static const unsigned int scif4_data_b_mux[] = {
  2762. SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
  2763. };
  2764. static const unsigned int scif4_data_c_pins[] = {
  2765. /* RX, TX */
  2766. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  2767. };
  2768. static const unsigned int scif4_data_c_mux[] = {
  2769. SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
  2770. };
  2771. static const unsigned int scif4_data_d_pins[] = {
  2772. /* RX, TX */
  2773. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
  2774. };
  2775. static const unsigned int scif4_data_d_mux[] = {
  2776. SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
  2777. };
  2778. static const unsigned int scif4_data_e_pins[] = {
  2779. /* RX, TX */
  2780. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
  2781. };
  2782. static const unsigned int scif4_data_e_mux[] = {
  2783. SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
  2784. };
  2785. /* - SCIF5 ------------------------------------------------------------------ */
  2786. static const unsigned int scif5_data_pins[] = {
  2787. /* RX, TX */
  2788. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  2789. };
  2790. static const unsigned int scif5_data_mux[] = {
  2791. SCIF5_RXD_MARK, SCIF5_TXD_MARK,
  2792. };
  2793. static const unsigned int scif5_data_b_pins[] = {
  2794. /* RX, TX */
  2795. RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
  2796. };
  2797. static const unsigned int scif5_data_b_mux[] = {
  2798. SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
  2799. };
  2800. static const unsigned int scif5_data_c_pins[] = {
  2801. /* RX, TX */
  2802. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
  2803. };
  2804. static const unsigned int scif5_data_c_mux[] = {
  2805. SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
  2806. };
  2807. static const unsigned int scif5_data_d_pins[] = {
  2808. /* RX, TX */
  2809. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  2810. };
  2811. static const unsigned int scif5_data_d_mux[] = {
  2812. SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
  2813. };
  2814. /* - SCIFA0 ----------------------------------------------------------------- */
  2815. static const unsigned int scifa0_data_pins[] = {
  2816. /* RXD, TXD */
  2817. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
  2818. };
  2819. static const unsigned int scifa0_data_mux[] = {
  2820. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  2821. };
  2822. static const unsigned int scifa0_data_b_pins[] = {
  2823. /* RXD, TXD */
  2824. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  2825. };
  2826. static const unsigned int scifa0_data_b_mux[] = {
  2827. SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
  2828. };
  2829. static const unsigned int scifa0_data_c_pins[] = {
  2830. /* RXD, TXD */
  2831. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  2832. };
  2833. static const unsigned int scifa0_data_c_mux[] = {
  2834. SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
  2835. };
  2836. static const unsigned int scifa0_data_d_pins[] = {
  2837. /* RXD, TXD */
  2838. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  2839. };
  2840. static const unsigned int scifa0_data_d_mux[] = {
  2841. SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
  2842. };
  2843. /* - SCIFA1 ----------------------------------------------------------------- */
  2844. static const unsigned int scifa1_data_pins[] = {
  2845. /* RXD, TXD */
  2846. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2847. };
  2848. static const unsigned int scifa1_data_mux[] = {
  2849. SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
  2850. };
  2851. static const unsigned int scifa1_clk_pins[] = {
  2852. /* SCK */
  2853. RCAR_GP_PIN(0, 13),
  2854. };
  2855. static const unsigned int scifa1_clk_mux[] = {
  2856. SCIFA1_SCK_MARK,
  2857. };
  2858. static const unsigned int scifa1_data_b_pins[] = {
  2859. /* RXD, TXD */
  2860. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2861. };
  2862. static const unsigned int scifa1_data_b_mux[] = {
  2863. SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
  2864. };
  2865. static const unsigned int scifa1_clk_b_pins[] = {
  2866. /* SCK */
  2867. RCAR_GP_PIN(4, 27),
  2868. };
  2869. static const unsigned int scifa1_clk_b_mux[] = {
  2870. SCIFA1_SCK_B_MARK,
  2871. };
  2872. static const unsigned int scifa1_data_c_pins[] = {
  2873. /* RXD, TXD */
  2874. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2875. };
  2876. static const unsigned int scifa1_data_c_mux[] = {
  2877. SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
  2878. };
  2879. static const unsigned int scifa1_clk_c_pins[] = {
  2880. /* SCK */
  2881. RCAR_GP_PIN(5, 4),
  2882. };
  2883. static const unsigned int scifa1_clk_c_mux[] = {
  2884. SCIFA1_SCK_C_MARK,
  2885. };
  2886. /* - SCIFA2 ----------------------------------------------------------------- */
  2887. static const unsigned int scifa2_data_pins[] = {
  2888. /* RXD, TXD */
  2889. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
  2890. };
  2891. static const unsigned int scifa2_data_mux[] = {
  2892. SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
  2893. };
  2894. static const unsigned int scifa2_clk_pins[] = {
  2895. /* SCK */
  2896. RCAR_GP_PIN(1, 15),
  2897. };
  2898. static const unsigned int scifa2_clk_mux[] = {
  2899. SCIFA2_SCK_MARK,
  2900. };
  2901. static const unsigned int scifa2_data_b_pins[] = {
  2902. /* RXD, TXD */
  2903. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
  2904. };
  2905. static const unsigned int scifa2_data_b_mux[] = {
  2906. SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
  2907. };
  2908. static const unsigned int scifa2_clk_b_pins[] = {
  2909. /* SCK */
  2910. RCAR_GP_PIN(4, 30),
  2911. };
  2912. static const unsigned int scifa2_clk_b_mux[] = {
  2913. SCIFA2_SCK_B_MARK,
  2914. };
  2915. /* - SCIFA3 ----------------------------------------------------------------- */
  2916. static const unsigned int scifa3_data_pins[] = {
  2917. /* RXD, TXD */
  2918. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
  2919. };
  2920. static const unsigned int scifa3_data_mux[] = {
  2921. SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
  2922. };
  2923. static const unsigned int scifa3_clk_pins[] = {
  2924. /* SCK */
  2925. RCAR_GP_PIN(4, 24),
  2926. };
  2927. static const unsigned int scifa3_clk_mux[] = {
  2928. SCIFA3_SCK_MARK,
  2929. };
  2930. static const unsigned int scifa3_data_b_pins[] = {
  2931. /* RXD, TXD */
  2932. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
  2933. };
  2934. static const unsigned int scifa3_data_b_mux[] = {
  2935. SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
  2936. };
  2937. static const unsigned int scifa3_clk_b_pins[] = {
  2938. /* SCK */
  2939. RCAR_GP_PIN(0, 0),
  2940. };
  2941. static const unsigned int scifa3_clk_b_mux[] = {
  2942. SCIFA3_SCK_B_MARK,
  2943. };
  2944. /* - SCIFA4 ----------------------------------------------------------------- */
  2945. static const unsigned int scifa4_data_pins[] = {
  2946. /* RXD, TXD */
  2947. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
  2948. };
  2949. static const unsigned int scifa4_data_mux[] = {
  2950. SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
  2951. };
  2952. static const unsigned int scifa4_data_b_pins[] = {
  2953. /* RXD, TXD */
  2954. RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
  2955. };
  2956. static const unsigned int scifa4_data_b_mux[] = {
  2957. SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
  2958. };
  2959. static const unsigned int scifa4_data_c_pins[] = {
  2960. /* RXD, TXD */
  2961. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  2962. };
  2963. static const unsigned int scifa4_data_c_mux[] = {
  2964. SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
  2965. };
  2966. static const unsigned int scifa4_data_d_pins[] = {
  2967. /* RXD, TXD */
  2968. RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
  2969. };
  2970. static const unsigned int scifa4_data_d_mux[] = {
  2971. SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
  2972. };
  2973. /* - SCIFA5 ----------------------------------------------------------------- */
  2974. static const unsigned int scifa5_data_pins[] = {
  2975. /* RXD, TXD */
  2976. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  2977. };
  2978. static const unsigned int scifa5_data_mux[] = {
  2979. SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
  2980. };
  2981. static const unsigned int scifa5_data_b_pins[] = {
  2982. /* RXD, TXD */
  2983. RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
  2984. };
  2985. static const unsigned int scifa5_data_b_mux[] = {
  2986. SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
  2987. };
  2988. static const unsigned int scifa5_data_c_pins[] = {
  2989. /* RXD, TXD */
  2990. RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
  2991. };
  2992. static const unsigned int scifa5_data_c_mux[] = {
  2993. SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
  2994. };
  2995. static const unsigned int scifa5_data_d_pins[] = {
  2996. /* RXD, TXD */
  2997. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  2998. };
  2999. static const unsigned int scifa5_data_d_mux[] = {
  3000. SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
  3001. };
  3002. /* - SCIFB0 ----------------------------------------------------------------- */
  3003. static const unsigned int scifb0_data_pins[] = {
  3004. /* RXD, TXD */
  3005. RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
  3006. };
  3007. static const unsigned int scifb0_data_mux[] = {
  3008. SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
  3009. };
  3010. static const unsigned int scifb0_clk_pins[] = {
  3011. /* SCK */
  3012. RCAR_GP_PIN(0, 19),
  3013. };
  3014. static const unsigned int scifb0_clk_mux[] = {
  3015. SCIFB0_SCK_MARK,
  3016. };
  3017. static const unsigned int scifb0_ctrl_pins[] = {
  3018. /* RTS, CTS */
  3019. RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
  3020. };
  3021. static const unsigned int scifb0_ctrl_mux[] = {
  3022. SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
  3023. };
  3024. /* - SCIFB1 ----------------------------------------------------------------- */
  3025. static const unsigned int scifb1_data_pins[] = {
  3026. /* RXD, TXD */
  3027. RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
  3028. };
  3029. static const unsigned int scifb1_data_mux[] = {
  3030. SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
  3031. };
  3032. static const unsigned int scifb1_clk_pins[] = {
  3033. /* SCK */
  3034. RCAR_GP_PIN(0, 16),
  3035. };
  3036. static const unsigned int scifb1_clk_mux[] = {
  3037. SCIFB1_SCK_MARK,
  3038. };
  3039. /* - SCIFB2 ----------------------------------------------------------------- */
  3040. static const unsigned int scifb2_data_pins[] = {
  3041. /* RXD, TXD */
  3042. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  3043. };
  3044. static const unsigned int scifb2_data_mux[] = {
  3045. SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
  3046. };
  3047. static const unsigned int scifb2_clk_pins[] = {
  3048. /* SCK */
  3049. RCAR_GP_PIN(1, 15),
  3050. };
  3051. static const unsigned int scifb2_clk_mux[] = {
  3052. SCIFB2_SCK_MARK,
  3053. };
  3054. static const unsigned int scifb2_ctrl_pins[] = {
  3055. /* RTS, CTS */
  3056. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  3057. };
  3058. static const unsigned int scifb2_ctrl_mux[] = {
  3059. SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
  3060. };
  3061. /* - SCIF Clock ------------------------------------------------------------- */
  3062. static const unsigned int scif_clk_pins[] = {
  3063. /* SCIF_CLK */
  3064. RCAR_GP_PIN(1, 23),
  3065. };
  3066. static const unsigned int scif_clk_mux[] = {
  3067. SCIF_CLK_MARK,
  3068. };
  3069. static const unsigned int scif_clk_b_pins[] = {
  3070. /* SCIF_CLK */
  3071. RCAR_GP_PIN(3, 29),
  3072. };
  3073. static const unsigned int scif_clk_b_mux[] = {
  3074. SCIF_CLK_B_MARK,
  3075. };
  3076. /* - SDHI0 ------------------------------------------------------------------ */
  3077. static const unsigned int sdhi0_data1_pins[] = {
  3078. /* D0 */
  3079. RCAR_GP_PIN(6, 2),
  3080. };
  3081. static const unsigned int sdhi0_data1_mux[] = {
  3082. SD0_DATA0_MARK,
  3083. };
  3084. static const unsigned int sdhi0_data4_pins[] = {
  3085. /* D[0:3] */
  3086. RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
  3087. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
  3088. };
  3089. static const unsigned int sdhi0_data4_mux[] = {
  3090. SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
  3091. };
  3092. static const unsigned int sdhi0_ctrl_pins[] = {
  3093. /* CLK, CMD */
  3094. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  3095. };
  3096. static const unsigned int sdhi0_ctrl_mux[] = {
  3097. SD0_CLK_MARK, SD0_CMD_MARK,
  3098. };
  3099. static const unsigned int sdhi0_cd_pins[] = {
  3100. /* CD */
  3101. RCAR_GP_PIN(6, 6),
  3102. };
  3103. static const unsigned int sdhi0_cd_mux[] = {
  3104. SD0_CD_MARK,
  3105. };
  3106. static const unsigned int sdhi0_wp_pins[] = {
  3107. /* WP */
  3108. RCAR_GP_PIN(6, 7),
  3109. };
  3110. static const unsigned int sdhi0_wp_mux[] = {
  3111. SD0_WP_MARK,
  3112. };
  3113. /* - SDHI1 ------------------------------------------------------------------ */
  3114. static const unsigned int sdhi1_data1_pins[] = {
  3115. /* D0 */
  3116. RCAR_GP_PIN(6, 10),
  3117. };
  3118. static const unsigned int sdhi1_data1_mux[] = {
  3119. SD1_DATA0_MARK,
  3120. };
  3121. static const unsigned int sdhi1_data4_pins[] = {
  3122. /* D[0:3] */
  3123. RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
  3124. RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
  3125. };
  3126. static const unsigned int sdhi1_data4_mux[] = {
  3127. SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
  3128. };
  3129. static const unsigned int sdhi1_ctrl_pins[] = {
  3130. /* CLK, CMD */
  3131. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  3132. };
  3133. static const unsigned int sdhi1_ctrl_mux[] = {
  3134. SD1_CLK_MARK, SD1_CMD_MARK,
  3135. };
  3136. static const unsigned int sdhi1_cd_pins[] = {
  3137. /* CD */
  3138. RCAR_GP_PIN(6, 14),
  3139. };
  3140. static const unsigned int sdhi1_cd_mux[] = {
  3141. SD1_CD_MARK,
  3142. };
  3143. static const unsigned int sdhi1_wp_pins[] = {
  3144. /* WP */
  3145. RCAR_GP_PIN(6, 15),
  3146. };
  3147. static const unsigned int sdhi1_wp_mux[] = {
  3148. SD1_WP_MARK,
  3149. };
  3150. /* - SDHI2 ------------------------------------------------------------------ */
  3151. static const unsigned int sdhi2_data1_pins[] = {
  3152. /* D0 */
  3153. RCAR_GP_PIN(6, 18),
  3154. };
  3155. static const unsigned int sdhi2_data1_mux[] = {
  3156. SD2_DATA0_MARK,
  3157. };
  3158. static const unsigned int sdhi2_data4_pins[] = {
  3159. /* D[0:3] */
  3160. RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
  3161. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
  3162. };
  3163. static const unsigned int sdhi2_data4_mux[] = {
  3164. SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
  3165. };
  3166. static const unsigned int sdhi2_ctrl_pins[] = {
  3167. /* CLK, CMD */
  3168. RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
  3169. };
  3170. static const unsigned int sdhi2_ctrl_mux[] = {
  3171. SD2_CLK_MARK, SD2_CMD_MARK,
  3172. };
  3173. static const unsigned int sdhi2_cd_pins[] = {
  3174. /* CD */
  3175. RCAR_GP_PIN(6, 22),
  3176. };
  3177. static const unsigned int sdhi2_cd_mux[] = {
  3178. SD2_CD_MARK,
  3179. };
  3180. static const unsigned int sdhi2_wp_pins[] = {
  3181. /* WP */
  3182. RCAR_GP_PIN(6, 23),
  3183. };
  3184. static const unsigned int sdhi2_wp_mux[] = {
  3185. SD2_WP_MARK,
  3186. };
  3187. /* - SSI -------------------------------------------------------------------- */
  3188. static const unsigned int ssi0_data_pins[] = {
  3189. /* SDATA0 */
  3190. RCAR_GP_PIN(5, 3),
  3191. };
  3192. static const unsigned int ssi0_data_mux[] = {
  3193. SSI_SDATA0_MARK,
  3194. };
  3195. static const unsigned int ssi0129_ctrl_pins[] = {
  3196. /* SCK0129, WS0129 */
  3197. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  3198. };
  3199. static const unsigned int ssi0129_ctrl_mux[] = {
  3200. SSI_SCK0129_MARK, SSI_WS0129_MARK,
  3201. };
  3202. static const unsigned int ssi1_data_pins[] = {
  3203. /* SDATA1 */
  3204. RCAR_GP_PIN(5, 13),
  3205. };
  3206. static const unsigned int ssi1_data_mux[] = {
  3207. SSI_SDATA1_MARK,
  3208. };
  3209. static const unsigned int ssi1_ctrl_pins[] = {
  3210. /* SCK1, WS1 */
  3211. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
  3212. };
  3213. static const unsigned int ssi1_ctrl_mux[] = {
  3214. SSI_SCK1_MARK, SSI_WS1_MARK,
  3215. };
  3216. static const unsigned int ssi1_data_b_pins[] = {
  3217. /* SDATA1 */
  3218. RCAR_GP_PIN(4, 13),
  3219. };
  3220. static const unsigned int ssi1_data_b_mux[] = {
  3221. SSI_SDATA1_B_MARK,
  3222. };
  3223. static const unsigned int ssi1_ctrl_b_pins[] = {
  3224. /* SCK1, WS1 */
  3225. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3226. };
  3227. static const unsigned int ssi1_ctrl_b_mux[] = {
  3228. SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
  3229. };
  3230. static const unsigned int ssi2_data_pins[] = {
  3231. /* SDATA2 */
  3232. RCAR_GP_PIN(5, 16),
  3233. };
  3234. static const unsigned int ssi2_data_mux[] = {
  3235. SSI_SDATA2_MARK,
  3236. };
  3237. static const unsigned int ssi2_ctrl_pins[] = {
  3238. /* SCK2, WS2 */
  3239. RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
  3240. };
  3241. static const unsigned int ssi2_ctrl_mux[] = {
  3242. SSI_SCK2_MARK, SSI_WS2_MARK,
  3243. };
  3244. static const unsigned int ssi2_data_b_pins[] = {
  3245. /* SDATA2 */
  3246. RCAR_GP_PIN(4, 16),
  3247. };
  3248. static const unsigned int ssi2_data_b_mux[] = {
  3249. SSI_SDATA2_B_MARK,
  3250. };
  3251. static const unsigned int ssi2_ctrl_b_pins[] = {
  3252. /* SCK2, WS2 */
  3253. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  3254. };
  3255. static const unsigned int ssi2_ctrl_b_mux[] = {
  3256. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  3257. };
  3258. static const unsigned int ssi3_data_pins[] = {
  3259. /* SDATA3 */
  3260. RCAR_GP_PIN(5, 6),
  3261. };
  3262. static const unsigned int ssi3_data_mux[] = {
  3263. SSI_SDATA3_MARK
  3264. };
  3265. static const unsigned int ssi34_ctrl_pins[] = {
  3266. /* SCK34, WS34 */
  3267. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
  3268. };
  3269. static const unsigned int ssi34_ctrl_mux[] = {
  3270. SSI_SCK34_MARK, SSI_WS34_MARK,
  3271. };
  3272. static const unsigned int ssi4_data_pins[] = {
  3273. /* SDATA4 */
  3274. RCAR_GP_PIN(5, 9),
  3275. };
  3276. static const unsigned int ssi4_data_mux[] = {
  3277. SSI_SDATA4_MARK,
  3278. };
  3279. static const unsigned int ssi4_ctrl_pins[] = {
  3280. /* SCK4, WS4 */
  3281. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  3282. };
  3283. static const unsigned int ssi4_ctrl_mux[] = {
  3284. SSI_SCK4_MARK, SSI_WS4_MARK,
  3285. };
  3286. static const unsigned int ssi4_data_b_pins[] = {
  3287. /* SDATA4 */
  3288. RCAR_GP_PIN(4, 22),
  3289. };
  3290. static const unsigned int ssi4_data_b_mux[] = {
  3291. SSI_SDATA4_B_MARK,
  3292. };
  3293. static const unsigned int ssi4_ctrl_b_pins[] = {
  3294. /* SCK4, WS4 */
  3295. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  3296. };
  3297. static const unsigned int ssi4_ctrl_b_mux[] = {
  3298. SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
  3299. };
  3300. static const unsigned int ssi5_data_pins[] = {
  3301. /* SDATA5 */
  3302. RCAR_GP_PIN(4, 26),
  3303. };
  3304. static const unsigned int ssi5_data_mux[] = {
  3305. SSI_SDATA5_MARK,
  3306. };
  3307. static const unsigned int ssi5_ctrl_pins[] = {
  3308. /* SCK5, WS5 */
  3309. RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
  3310. };
  3311. static const unsigned int ssi5_ctrl_mux[] = {
  3312. SSI_SCK5_MARK, SSI_WS5_MARK,
  3313. };
  3314. static const unsigned int ssi5_data_b_pins[] = {
  3315. /* SDATA5 */
  3316. RCAR_GP_PIN(3, 21),
  3317. };
  3318. static const unsigned int ssi5_data_b_mux[] = {
  3319. SSI_SDATA5_B_MARK,
  3320. };
  3321. static const unsigned int ssi5_ctrl_b_pins[] = {
  3322. /* SCK5, WS5 */
  3323. RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  3324. };
  3325. static const unsigned int ssi5_ctrl_b_mux[] = {
  3326. SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
  3327. };
  3328. static const unsigned int ssi6_data_pins[] = {
  3329. /* SDATA6 */
  3330. RCAR_GP_PIN(4, 29),
  3331. };
  3332. static const unsigned int ssi6_data_mux[] = {
  3333. SSI_SDATA6_MARK,
  3334. };
  3335. static const unsigned int ssi6_ctrl_pins[] = {
  3336. /* SCK6, WS6 */
  3337. RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
  3338. };
  3339. static const unsigned int ssi6_ctrl_mux[] = {
  3340. SSI_SCK6_MARK, SSI_WS6_MARK,
  3341. };
  3342. static const unsigned int ssi6_data_b_pins[] = {
  3343. /* SDATA6 */
  3344. RCAR_GP_PIN(3, 24),
  3345. };
  3346. static const unsigned int ssi6_data_b_mux[] = {
  3347. SSI_SDATA6_B_MARK,
  3348. };
  3349. static const unsigned int ssi6_ctrl_b_pins[] = {
  3350. /* SCK6, WS6 */
  3351. RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
  3352. };
  3353. static const unsigned int ssi6_ctrl_b_mux[] = {
  3354. SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
  3355. };
  3356. static const unsigned int ssi7_data_pins[] = {
  3357. /* SDATA7 */
  3358. RCAR_GP_PIN(5, 0),
  3359. };
  3360. static const unsigned int ssi7_data_mux[] = {
  3361. SSI_SDATA7_MARK,
  3362. };
  3363. static const unsigned int ssi78_ctrl_pins[] = {
  3364. /* SCK78, WS78 */
  3365. RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
  3366. };
  3367. static const unsigned int ssi78_ctrl_mux[] = {
  3368. SSI_SCK78_MARK, SSI_WS78_MARK,
  3369. };
  3370. static const unsigned int ssi7_data_b_pins[] = {
  3371. /* SDATA7 */
  3372. RCAR_GP_PIN(3, 27),
  3373. };
  3374. static const unsigned int ssi7_data_b_mux[] = {
  3375. SSI_SDATA7_B_MARK,
  3376. };
  3377. static const unsigned int ssi78_ctrl_b_pins[] = {
  3378. /* SCK78, WS78 */
  3379. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  3380. };
  3381. static const unsigned int ssi78_ctrl_b_mux[] = {
  3382. SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
  3383. };
  3384. static const unsigned int ssi8_data_pins[] = {
  3385. /* SDATA8 */
  3386. RCAR_GP_PIN(5, 10),
  3387. };
  3388. static const unsigned int ssi8_data_mux[] = {
  3389. SSI_SDATA8_MARK,
  3390. };
  3391. static const unsigned int ssi8_data_b_pins[] = {
  3392. /* SDATA8 */
  3393. RCAR_GP_PIN(3, 28),
  3394. };
  3395. static const unsigned int ssi8_data_b_mux[] = {
  3396. SSI_SDATA8_B_MARK,
  3397. };
  3398. static const unsigned int ssi9_data_pins[] = {
  3399. /* SDATA9 */
  3400. RCAR_GP_PIN(5, 19),
  3401. };
  3402. static const unsigned int ssi9_data_mux[] = {
  3403. SSI_SDATA9_MARK,
  3404. };
  3405. static const unsigned int ssi9_ctrl_pins[] = {
  3406. /* SCK9, WS9 */
  3407. RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
  3408. };
  3409. static const unsigned int ssi9_ctrl_mux[] = {
  3410. SSI_SCK9_MARK, SSI_WS9_MARK,
  3411. };
  3412. static const unsigned int ssi9_data_b_pins[] = {
  3413. /* SDATA9 */
  3414. RCAR_GP_PIN(4, 19),
  3415. };
  3416. static const unsigned int ssi9_data_b_mux[] = {
  3417. SSI_SDATA9_B_MARK,
  3418. };
  3419. static const unsigned int ssi9_ctrl_b_pins[] = {
  3420. /* SCK9, WS9 */
  3421. RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
  3422. };
  3423. static const unsigned int ssi9_ctrl_b_mux[] = {
  3424. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  3425. };
  3426. /* - TPU -------------------------------------------------------------------- */
  3427. static const unsigned int tpu_to0_pins[] = {
  3428. RCAR_GP_PIN(3, 31),
  3429. };
  3430. static const unsigned int tpu_to0_mux[] = {
  3431. TPUTO0_MARK,
  3432. };
  3433. static const unsigned int tpu_to0_b_pins[] = {
  3434. RCAR_GP_PIN(3, 30),
  3435. };
  3436. static const unsigned int tpu_to0_b_mux[] = {
  3437. TPUTO0_B_MARK,
  3438. };
  3439. static const unsigned int tpu_to0_c_pins[] = {
  3440. RCAR_GP_PIN(1, 18),
  3441. };
  3442. static const unsigned int tpu_to0_c_mux[] = {
  3443. TPUTO0_C_MARK,
  3444. };
  3445. static const unsigned int tpu_to1_pins[] = {
  3446. RCAR_GP_PIN(4, 9),
  3447. };
  3448. static const unsigned int tpu_to1_mux[] = {
  3449. TPUTO1_MARK,
  3450. };
  3451. static const unsigned int tpu_to1_b_pins[] = {
  3452. RCAR_GP_PIN(4, 0),
  3453. };
  3454. static const unsigned int tpu_to1_b_mux[] = {
  3455. TPUTO1_B_MARK,
  3456. };
  3457. static const unsigned int tpu_to1_c_pins[] = {
  3458. RCAR_GP_PIN(4, 4),
  3459. };
  3460. static const unsigned int tpu_to1_c_mux[] = {
  3461. TPUTO1_C_MARK,
  3462. };
  3463. static const unsigned int tpu_to2_pins[] = {
  3464. RCAR_GP_PIN(1, 3),
  3465. };
  3466. static const unsigned int tpu_to2_mux[] = {
  3467. TPUTO2_MARK,
  3468. };
  3469. static const unsigned int tpu_to2_b_pins[] = {
  3470. RCAR_GP_PIN(1, 0),
  3471. };
  3472. static const unsigned int tpu_to2_b_mux[] = {
  3473. TPUTO2_B_MARK,
  3474. };
  3475. static const unsigned int tpu_to2_c_pins[] = {
  3476. RCAR_GP_PIN(0, 22),
  3477. };
  3478. static const unsigned int tpu_to2_c_mux[] = {
  3479. TPUTO2_C_MARK,
  3480. };
  3481. static const unsigned int tpu_to3_pins[] = {
  3482. RCAR_GP_PIN(1, 14),
  3483. };
  3484. static const unsigned int tpu_to3_mux[] = {
  3485. TPUTO3_MARK,
  3486. };
  3487. static const unsigned int tpu_to3_b_pins[] = {
  3488. RCAR_GP_PIN(1, 13),
  3489. };
  3490. static const unsigned int tpu_to3_b_mux[] = {
  3491. TPUTO3_B_MARK,
  3492. };
  3493. static const unsigned int tpu_to3_c_pins[] = {
  3494. RCAR_GP_PIN(0, 21),
  3495. };
  3496. static const unsigned int tpu_to3_c_mux[] = {
  3497. TPUTO3_C_MARK,
  3498. };
  3499. /* - USB0 ------------------------------------------------------------------- */
  3500. static const unsigned int usb0_pins[] = {
  3501. RCAR_GP_PIN(5, 24), /* PWEN */
  3502. RCAR_GP_PIN(5, 25), /* OVC */
  3503. };
  3504. static const unsigned int usb0_mux[] = {
  3505. USB0_PWEN_MARK,
  3506. USB0_OVC_MARK,
  3507. };
  3508. /* - USB1 ------------------------------------------------------------------- */
  3509. static const unsigned int usb1_pins[] = {
  3510. RCAR_GP_PIN(5, 26), /* PWEN */
  3511. RCAR_GP_PIN(5, 27), /* OVC */
  3512. };
  3513. static const unsigned int usb1_mux[] = {
  3514. USB1_PWEN_MARK,
  3515. USB1_OVC_MARK,
  3516. };
  3517. /* - VIN0 ------------------------------------------------------------------- */
  3518. static const union vin_data vin0_data_pins = {
  3519. .data24 = {
  3520. /* B */
  3521. RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
  3522. RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  3523. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
  3524. RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
  3525. /* G */
  3526. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  3527. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  3528. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
  3529. RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  3530. /* R */
  3531. RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
  3532. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  3533. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  3534. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  3535. },
  3536. };
  3537. static const union vin_data vin0_data_mux = {
  3538. .data24 = {
  3539. /* B */
  3540. VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
  3541. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  3542. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  3543. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  3544. /* G */
  3545. VI0_G0_MARK, VI0_G1_MARK,
  3546. VI0_G2_MARK, VI0_G3_MARK,
  3547. VI0_G4_MARK, VI0_G5_MARK,
  3548. VI0_G6_MARK, VI0_G7_MARK,
  3549. /* R */
  3550. VI0_R0_MARK, VI0_R1_MARK,
  3551. VI0_R2_MARK, VI0_R3_MARK,
  3552. VI0_R4_MARK, VI0_R5_MARK,
  3553. VI0_R6_MARK, VI0_R7_MARK,
  3554. },
  3555. };
  3556. static const unsigned int vin0_data18_pins[] = {
  3557. /* B */
  3558. RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  3559. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
  3560. RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
  3561. /* G */
  3562. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  3563. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
  3564. RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  3565. /* R */
  3566. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  3567. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  3568. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  3569. };
  3570. static const unsigned int vin0_data18_mux[] = {
  3571. /* B */
  3572. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  3573. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  3574. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  3575. /* G */
  3576. VI0_G2_MARK, VI0_G3_MARK,
  3577. VI0_G4_MARK, VI0_G5_MARK,
  3578. VI0_G6_MARK, VI0_G7_MARK,
  3579. /* R */
  3580. VI0_R2_MARK, VI0_R3_MARK,
  3581. VI0_R4_MARK, VI0_R5_MARK,
  3582. VI0_R6_MARK, VI0_R7_MARK,
  3583. };
  3584. static const unsigned int vin0_sync_pins[] = {
  3585. RCAR_GP_PIN(3, 11), /* HSYNC */
  3586. RCAR_GP_PIN(3, 12), /* VSYNC */
  3587. };
  3588. static const unsigned int vin0_sync_mux[] = {
  3589. VI0_HSYNC_N_MARK,
  3590. VI0_VSYNC_N_MARK,
  3591. };
  3592. static const unsigned int vin0_field_pins[] = {
  3593. RCAR_GP_PIN(3, 10),
  3594. };
  3595. static const unsigned int vin0_field_mux[] = {
  3596. VI0_FIELD_MARK,
  3597. };
  3598. static const unsigned int vin0_clkenb_pins[] = {
  3599. RCAR_GP_PIN(3, 9),
  3600. };
  3601. static const unsigned int vin0_clkenb_mux[] = {
  3602. VI0_CLKENB_MARK,
  3603. };
  3604. static const unsigned int vin0_clk_pins[] = {
  3605. RCAR_GP_PIN(3, 0),
  3606. };
  3607. static const unsigned int vin0_clk_mux[] = {
  3608. VI0_CLK_MARK,
  3609. };
  3610. /* - VIN1 ------------------------------------------------------------------- */
  3611. static const union vin_data12 vin1_data_pins = {
  3612. .data12 = {
  3613. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
  3614. RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
  3615. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
  3616. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  3617. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
  3618. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  3619. },
  3620. };
  3621. static const union vin_data12 vin1_data_mux = {
  3622. .data12 = {
  3623. VI1_DATA0_MARK, VI1_DATA1_MARK,
  3624. VI1_DATA2_MARK, VI1_DATA3_MARK,
  3625. VI1_DATA4_MARK, VI1_DATA5_MARK,
  3626. VI1_DATA6_MARK, VI1_DATA7_MARK,
  3627. VI1_DATA8_MARK, VI1_DATA9_MARK,
  3628. VI1_DATA10_MARK, VI1_DATA11_MARK,
  3629. },
  3630. };
  3631. static const unsigned int vin1_sync_pins[] = {
  3632. RCAR_GP_PIN(5, 22), /* HSYNC */
  3633. RCAR_GP_PIN(5, 23), /* VSYNC */
  3634. };
  3635. static const unsigned int vin1_sync_mux[] = {
  3636. VI1_HSYNC_N_MARK,
  3637. VI1_VSYNC_N_MARK,
  3638. };
  3639. static const unsigned int vin1_field_pins[] = {
  3640. RCAR_GP_PIN(5, 21),
  3641. };
  3642. static const unsigned int vin1_field_mux[] = {
  3643. VI1_FIELD_MARK,
  3644. };
  3645. static const unsigned int vin1_clkenb_pins[] = {
  3646. RCAR_GP_PIN(5, 20),
  3647. };
  3648. static const unsigned int vin1_clkenb_mux[] = {
  3649. VI1_CLKENB_MARK,
  3650. };
  3651. static const unsigned int vin1_clk_pins[] = {
  3652. RCAR_GP_PIN(5, 11),
  3653. };
  3654. static const unsigned int vin1_clk_mux[] = {
  3655. VI1_CLK_MARK,
  3656. };
  3657. static const struct sh_pfc_pin_group pinmux_groups[] = {
  3658. SH_PFC_PIN_GROUP(audio_clka),
  3659. SH_PFC_PIN_GROUP(audio_clka_b),
  3660. SH_PFC_PIN_GROUP(audio_clka_c),
  3661. SH_PFC_PIN_GROUP(audio_clka_d),
  3662. SH_PFC_PIN_GROUP(audio_clkb),
  3663. SH_PFC_PIN_GROUP(audio_clkb_b),
  3664. SH_PFC_PIN_GROUP(audio_clkb_c),
  3665. SH_PFC_PIN_GROUP(audio_clkc),
  3666. SH_PFC_PIN_GROUP(audio_clkc_b),
  3667. SH_PFC_PIN_GROUP(audio_clkc_c),
  3668. SH_PFC_PIN_GROUP(audio_clkout),
  3669. SH_PFC_PIN_GROUP(audio_clkout_b),
  3670. SH_PFC_PIN_GROUP(audio_clkout_c),
  3671. SH_PFC_PIN_GROUP(avb_link),
  3672. SH_PFC_PIN_GROUP(avb_magic),
  3673. SH_PFC_PIN_GROUP(avb_phy_int),
  3674. SH_PFC_PIN_GROUP(avb_mdio),
  3675. SH_PFC_PIN_GROUP(avb_mii),
  3676. SH_PFC_PIN_GROUP(avb_gmii),
  3677. SH_PFC_PIN_GROUP(can0_data),
  3678. SH_PFC_PIN_GROUP(can0_data_b),
  3679. SH_PFC_PIN_GROUP(can0_data_c),
  3680. SH_PFC_PIN_GROUP(can0_data_d),
  3681. SH_PFC_PIN_GROUP(can1_data),
  3682. SH_PFC_PIN_GROUP(can1_data_b),
  3683. SH_PFC_PIN_GROUP(can1_data_c),
  3684. SH_PFC_PIN_GROUP(can1_data_d),
  3685. SH_PFC_PIN_GROUP(can_clk),
  3686. SH_PFC_PIN_GROUP(can_clk_b),
  3687. SH_PFC_PIN_GROUP(can_clk_c),
  3688. SH_PFC_PIN_GROUP(can_clk_d),
  3689. SH_PFC_PIN_GROUP(du0_rgb666),
  3690. SH_PFC_PIN_GROUP(du0_rgb888),
  3691. SH_PFC_PIN_GROUP(du0_clk0_out),
  3692. SH_PFC_PIN_GROUP(du0_clk1_out),
  3693. SH_PFC_PIN_GROUP(du0_clk_in),
  3694. SH_PFC_PIN_GROUP(du0_sync),
  3695. SH_PFC_PIN_GROUP(du0_oddf),
  3696. SH_PFC_PIN_GROUP(du0_cde),
  3697. SH_PFC_PIN_GROUP(du0_disp),
  3698. SH_PFC_PIN_GROUP(du1_rgb666),
  3699. SH_PFC_PIN_GROUP(du1_rgb888),
  3700. SH_PFC_PIN_GROUP(du1_clk0_out),
  3701. SH_PFC_PIN_GROUP(du1_clk1_out),
  3702. SH_PFC_PIN_GROUP(du1_clk_in),
  3703. SH_PFC_PIN_GROUP(du1_sync),
  3704. SH_PFC_PIN_GROUP(du1_oddf),
  3705. SH_PFC_PIN_GROUP(du1_cde),
  3706. SH_PFC_PIN_GROUP(du1_disp),
  3707. SH_PFC_PIN_GROUP(eth_link),
  3708. SH_PFC_PIN_GROUP(eth_magic),
  3709. SH_PFC_PIN_GROUP(eth_mdio),
  3710. SH_PFC_PIN_GROUP(eth_rmii),
  3711. SH_PFC_PIN_GROUP(eth_link_b),
  3712. SH_PFC_PIN_GROUP(eth_magic_b),
  3713. SH_PFC_PIN_GROUP(eth_mdio_b),
  3714. SH_PFC_PIN_GROUP(eth_rmii_b),
  3715. SH_PFC_PIN_GROUP(hscif0_data),
  3716. SH_PFC_PIN_GROUP(hscif0_clk),
  3717. SH_PFC_PIN_GROUP(hscif0_ctrl),
  3718. SH_PFC_PIN_GROUP(hscif0_data_b),
  3719. SH_PFC_PIN_GROUP(hscif0_clk_b),
  3720. SH_PFC_PIN_GROUP(hscif1_data),
  3721. SH_PFC_PIN_GROUP(hscif1_clk),
  3722. SH_PFC_PIN_GROUP(hscif1_ctrl),
  3723. SH_PFC_PIN_GROUP(hscif1_data_b),
  3724. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3725. SH_PFC_PIN_GROUP(hscif2_data),
  3726. SH_PFC_PIN_GROUP(hscif2_clk),
  3727. SH_PFC_PIN_GROUP(hscif2_ctrl),
  3728. SH_PFC_PIN_GROUP(i2c0),
  3729. SH_PFC_PIN_GROUP(i2c0_b),
  3730. SH_PFC_PIN_GROUP(i2c0_c),
  3731. SH_PFC_PIN_GROUP(i2c0_d),
  3732. SH_PFC_PIN_GROUP(i2c0_e),
  3733. SH_PFC_PIN_GROUP(i2c1),
  3734. SH_PFC_PIN_GROUP(i2c1_b),
  3735. SH_PFC_PIN_GROUP(i2c1_c),
  3736. SH_PFC_PIN_GROUP(i2c1_d),
  3737. SH_PFC_PIN_GROUP(i2c1_e),
  3738. SH_PFC_PIN_GROUP(i2c2),
  3739. SH_PFC_PIN_GROUP(i2c2_b),
  3740. SH_PFC_PIN_GROUP(i2c2_c),
  3741. SH_PFC_PIN_GROUP(i2c2_d),
  3742. SH_PFC_PIN_GROUP(i2c2_e),
  3743. SH_PFC_PIN_GROUP(i2c3),
  3744. SH_PFC_PIN_GROUP(i2c3_b),
  3745. SH_PFC_PIN_GROUP(i2c3_c),
  3746. SH_PFC_PIN_GROUP(i2c3_d),
  3747. SH_PFC_PIN_GROUP(i2c3_e),
  3748. SH_PFC_PIN_GROUP(i2c4),
  3749. SH_PFC_PIN_GROUP(i2c4_b),
  3750. SH_PFC_PIN_GROUP(i2c4_c),
  3751. SH_PFC_PIN_GROUP(i2c4_d),
  3752. SH_PFC_PIN_GROUP(i2c4_e),
  3753. SH_PFC_PIN_GROUP(i2c5),
  3754. SH_PFC_PIN_GROUP(i2c5_b),
  3755. SH_PFC_PIN_GROUP(i2c5_c),
  3756. SH_PFC_PIN_GROUP(i2c5_d),
  3757. SH_PFC_PIN_GROUP(intc_irq0),
  3758. SH_PFC_PIN_GROUP(intc_irq1),
  3759. SH_PFC_PIN_GROUP(intc_irq2),
  3760. SH_PFC_PIN_GROUP(intc_irq3),
  3761. SH_PFC_PIN_GROUP(intc_irq4),
  3762. SH_PFC_PIN_GROUP(intc_irq5),
  3763. SH_PFC_PIN_GROUP(intc_irq6),
  3764. SH_PFC_PIN_GROUP(intc_irq7),
  3765. SH_PFC_PIN_GROUP(intc_irq8),
  3766. SH_PFC_PIN_GROUP(intc_irq9),
  3767. SH_PFC_PIN_GROUP(mmc_data1),
  3768. SH_PFC_PIN_GROUP(mmc_data4),
  3769. SH_PFC_PIN_GROUP(mmc_data8),
  3770. SH_PFC_PIN_GROUP(mmc_ctrl),
  3771. SH_PFC_PIN_GROUP(msiof0_clk),
  3772. SH_PFC_PIN_GROUP(msiof0_sync),
  3773. SH_PFC_PIN_GROUP(msiof0_ss1),
  3774. SH_PFC_PIN_GROUP(msiof0_ss2),
  3775. SH_PFC_PIN_GROUP(msiof0_rx),
  3776. SH_PFC_PIN_GROUP(msiof0_tx),
  3777. SH_PFC_PIN_GROUP(msiof1_clk),
  3778. SH_PFC_PIN_GROUP(msiof1_sync),
  3779. SH_PFC_PIN_GROUP(msiof1_ss1),
  3780. SH_PFC_PIN_GROUP(msiof1_ss2),
  3781. SH_PFC_PIN_GROUP(msiof1_rx),
  3782. SH_PFC_PIN_GROUP(msiof1_tx),
  3783. SH_PFC_PIN_GROUP(msiof1_clk_b),
  3784. SH_PFC_PIN_GROUP(msiof1_sync_b),
  3785. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  3786. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  3787. SH_PFC_PIN_GROUP(msiof1_rx_b),
  3788. SH_PFC_PIN_GROUP(msiof1_tx_b),
  3789. SH_PFC_PIN_GROUP(msiof2_clk),
  3790. SH_PFC_PIN_GROUP(msiof2_sync),
  3791. SH_PFC_PIN_GROUP(msiof2_ss1),
  3792. SH_PFC_PIN_GROUP(msiof2_ss2),
  3793. SH_PFC_PIN_GROUP(msiof2_rx),
  3794. SH_PFC_PIN_GROUP(msiof2_tx),
  3795. SH_PFC_PIN_GROUP(msiof2_clk_b),
  3796. SH_PFC_PIN_GROUP(msiof2_sync_b),
  3797. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  3798. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  3799. SH_PFC_PIN_GROUP(msiof2_rx_b),
  3800. SH_PFC_PIN_GROUP(msiof2_tx_b),
  3801. SH_PFC_PIN_GROUP(pwm0),
  3802. SH_PFC_PIN_GROUP(pwm0_b),
  3803. SH_PFC_PIN_GROUP(pwm1),
  3804. SH_PFC_PIN_GROUP(pwm1_b),
  3805. SH_PFC_PIN_GROUP(pwm1_c),
  3806. SH_PFC_PIN_GROUP(pwm2),
  3807. SH_PFC_PIN_GROUP(pwm2_b),
  3808. SH_PFC_PIN_GROUP(pwm2_c),
  3809. SH_PFC_PIN_GROUP(pwm3),
  3810. SH_PFC_PIN_GROUP(pwm3_b),
  3811. SH_PFC_PIN_GROUP(pwm4),
  3812. SH_PFC_PIN_GROUP(pwm4_b),
  3813. SH_PFC_PIN_GROUP(pwm5),
  3814. SH_PFC_PIN_GROUP(pwm5_b),
  3815. SH_PFC_PIN_GROUP(pwm5_c),
  3816. SH_PFC_PIN_GROUP(pwm6),
  3817. SH_PFC_PIN_GROUP(pwm6_b),
  3818. SH_PFC_PIN_GROUP(qspi_ctrl),
  3819. SH_PFC_PIN_GROUP(qspi_data2),
  3820. SH_PFC_PIN_GROUP(qspi_data4),
  3821. SH_PFC_PIN_GROUP(scif0_data),
  3822. SH_PFC_PIN_GROUP(scif0_data_b),
  3823. SH_PFC_PIN_GROUP(scif0_data_c),
  3824. SH_PFC_PIN_GROUP(scif0_data_d),
  3825. SH_PFC_PIN_GROUP(scif1_data),
  3826. SH_PFC_PIN_GROUP(scif1_clk),
  3827. SH_PFC_PIN_GROUP(scif1_data_b),
  3828. SH_PFC_PIN_GROUP(scif1_clk_b),
  3829. SH_PFC_PIN_GROUP(scif1_data_c),
  3830. SH_PFC_PIN_GROUP(scif1_clk_c),
  3831. SH_PFC_PIN_GROUP(scif2_data),
  3832. SH_PFC_PIN_GROUP(scif2_clk),
  3833. SH_PFC_PIN_GROUP(scif2_data_b),
  3834. SH_PFC_PIN_GROUP(scif2_clk_b),
  3835. SH_PFC_PIN_GROUP(scif2_data_c),
  3836. SH_PFC_PIN_GROUP(scif2_clk_c),
  3837. SH_PFC_PIN_GROUP(scif3_data),
  3838. SH_PFC_PIN_GROUP(scif3_clk),
  3839. SH_PFC_PIN_GROUP(scif3_data_b),
  3840. SH_PFC_PIN_GROUP(scif3_clk_b),
  3841. SH_PFC_PIN_GROUP(scif4_data),
  3842. SH_PFC_PIN_GROUP(scif4_data_b),
  3843. SH_PFC_PIN_GROUP(scif4_data_c),
  3844. SH_PFC_PIN_GROUP(scif4_data_d),
  3845. SH_PFC_PIN_GROUP(scif4_data_e),
  3846. SH_PFC_PIN_GROUP(scif5_data),
  3847. SH_PFC_PIN_GROUP(scif5_data_b),
  3848. SH_PFC_PIN_GROUP(scif5_data_c),
  3849. SH_PFC_PIN_GROUP(scif5_data_d),
  3850. SH_PFC_PIN_GROUP(scifa0_data),
  3851. SH_PFC_PIN_GROUP(scifa0_data_b),
  3852. SH_PFC_PIN_GROUP(scifa0_data_c),
  3853. SH_PFC_PIN_GROUP(scifa0_data_d),
  3854. SH_PFC_PIN_GROUP(scifa1_data),
  3855. SH_PFC_PIN_GROUP(scifa1_clk),
  3856. SH_PFC_PIN_GROUP(scifa1_data_b),
  3857. SH_PFC_PIN_GROUP(scifa1_clk_b),
  3858. SH_PFC_PIN_GROUP(scifa1_data_c),
  3859. SH_PFC_PIN_GROUP(scifa1_clk_c),
  3860. SH_PFC_PIN_GROUP(scifa2_data),
  3861. SH_PFC_PIN_GROUP(scifa2_clk),
  3862. SH_PFC_PIN_GROUP(scifa2_data_b),
  3863. SH_PFC_PIN_GROUP(scifa2_clk_b),
  3864. SH_PFC_PIN_GROUP(scifa3_data),
  3865. SH_PFC_PIN_GROUP(scifa3_clk),
  3866. SH_PFC_PIN_GROUP(scifa3_data_b),
  3867. SH_PFC_PIN_GROUP(scifa3_clk_b),
  3868. SH_PFC_PIN_GROUP(scifa4_data),
  3869. SH_PFC_PIN_GROUP(scifa4_data_b),
  3870. SH_PFC_PIN_GROUP(scifa4_data_c),
  3871. SH_PFC_PIN_GROUP(scifa4_data_d),
  3872. SH_PFC_PIN_GROUP(scifa5_data),
  3873. SH_PFC_PIN_GROUP(scifa5_data_b),
  3874. SH_PFC_PIN_GROUP(scifa5_data_c),
  3875. SH_PFC_PIN_GROUP(scifa5_data_d),
  3876. SH_PFC_PIN_GROUP(scifb0_data),
  3877. SH_PFC_PIN_GROUP(scifb0_clk),
  3878. SH_PFC_PIN_GROUP(scifb0_ctrl),
  3879. SH_PFC_PIN_GROUP(scifb1_data),
  3880. SH_PFC_PIN_GROUP(scifb1_clk),
  3881. SH_PFC_PIN_GROUP(scifb2_data),
  3882. SH_PFC_PIN_GROUP(scifb2_clk),
  3883. SH_PFC_PIN_GROUP(scifb2_ctrl),
  3884. SH_PFC_PIN_GROUP(scif_clk),
  3885. SH_PFC_PIN_GROUP(scif_clk_b),
  3886. SH_PFC_PIN_GROUP(sdhi0_data1),
  3887. SH_PFC_PIN_GROUP(sdhi0_data4),
  3888. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  3889. SH_PFC_PIN_GROUP(sdhi0_cd),
  3890. SH_PFC_PIN_GROUP(sdhi0_wp),
  3891. SH_PFC_PIN_GROUP(sdhi1_data1),
  3892. SH_PFC_PIN_GROUP(sdhi1_data4),
  3893. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  3894. SH_PFC_PIN_GROUP(sdhi1_cd),
  3895. SH_PFC_PIN_GROUP(sdhi1_wp),
  3896. SH_PFC_PIN_GROUP(sdhi2_data1),
  3897. SH_PFC_PIN_GROUP(sdhi2_data4),
  3898. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  3899. SH_PFC_PIN_GROUP(sdhi2_cd),
  3900. SH_PFC_PIN_GROUP(sdhi2_wp),
  3901. SH_PFC_PIN_GROUP(ssi0_data),
  3902. SH_PFC_PIN_GROUP(ssi0129_ctrl),
  3903. SH_PFC_PIN_GROUP(ssi1_data),
  3904. SH_PFC_PIN_GROUP(ssi1_ctrl),
  3905. SH_PFC_PIN_GROUP(ssi1_data_b),
  3906. SH_PFC_PIN_GROUP(ssi1_ctrl_b),
  3907. SH_PFC_PIN_GROUP(ssi2_data),
  3908. SH_PFC_PIN_GROUP(ssi2_ctrl),
  3909. SH_PFC_PIN_GROUP(ssi2_data_b),
  3910. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  3911. SH_PFC_PIN_GROUP(ssi3_data),
  3912. SH_PFC_PIN_GROUP(ssi34_ctrl),
  3913. SH_PFC_PIN_GROUP(ssi4_data),
  3914. SH_PFC_PIN_GROUP(ssi4_ctrl),
  3915. SH_PFC_PIN_GROUP(ssi4_data_b),
  3916. SH_PFC_PIN_GROUP(ssi4_ctrl_b),
  3917. SH_PFC_PIN_GROUP(ssi5_data),
  3918. SH_PFC_PIN_GROUP(ssi5_ctrl),
  3919. SH_PFC_PIN_GROUP(ssi5_data_b),
  3920. SH_PFC_PIN_GROUP(ssi5_ctrl_b),
  3921. SH_PFC_PIN_GROUP(ssi6_data),
  3922. SH_PFC_PIN_GROUP(ssi6_ctrl),
  3923. SH_PFC_PIN_GROUP(ssi6_data_b),
  3924. SH_PFC_PIN_GROUP(ssi6_ctrl_b),
  3925. SH_PFC_PIN_GROUP(ssi7_data),
  3926. SH_PFC_PIN_GROUP(ssi78_ctrl),
  3927. SH_PFC_PIN_GROUP(ssi7_data_b),
  3928. SH_PFC_PIN_GROUP(ssi78_ctrl_b),
  3929. SH_PFC_PIN_GROUP(ssi8_data),
  3930. SH_PFC_PIN_GROUP(ssi8_data_b),
  3931. SH_PFC_PIN_GROUP(ssi9_data),
  3932. SH_PFC_PIN_GROUP(ssi9_ctrl),
  3933. SH_PFC_PIN_GROUP(ssi9_data_b),
  3934. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  3935. SH_PFC_PIN_GROUP(tpu_to0),
  3936. SH_PFC_PIN_GROUP(tpu_to0_b),
  3937. SH_PFC_PIN_GROUP(tpu_to0_c),
  3938. SH_PFC_PIN_GROUP(tpu_to1),
  3939. SH_PFC_PIN_GROUP(tpu_to1_b),
  3940. SH_PFC_PIN_GROUP(tpu_to1_c),
  3941. SH_PFC_PIN_GROUP(tpu_to2),
  3942. SH_PFC_PIN_GROUP(tpu_to2_b),
  3943. SH_PFC_PIN_GROUP(tpu_to2_c),
  3944. SH_PFC_PIN_GROUP(tpu_to3),
  3945. SH_PFC_PIN_GROUP(tpu_to3_b),
  3946. SH_PFC_PIN_GROUP(tpu_to3_c),
  3947. SH_PFC_PIN_GROUP(usb0),
  3948. SH_PFC_PIN_GROUP(usb1),
  3949. VIN_DATA_PIN_GROUP(vin0_data, 24),
  3950. VIN_DATA_PIN_GROUP(vin0_data, 20),
  3951. SH_PFC_PIN_GROUP(vin0_data18),
  3952. VIN_DATA_PIN_GROUP(vin0_data, 16),
  3953. VIN_DATA_PIN_GROUP(vin0_data, 12),
  3954. VIN_DATA_PIN_GROUP(vin0_data, 10),
  3955. VIN_DATA_PIN_GROUP(vin0_data, 8),
  3956. SH_PFC_PIN_GROUP(vin0_sync),
  3957. SH_PFC_PIN_GROUP(vin0_field),
  3958. SH_PFC_PIN_GROUP(vin0_clkenb),
  3959. SH_PFC_PIN_GROUP(vin0_clk),
  3960. VIN_DATA_PIN_GROUP(vin1_data, 12),
  3961. VIN_DATA_PIN_GROUP(vin1_data, 10),
  3962. VIN_DATA_PIN_GROUP(vin1_data, 8),
  3963. SH_PFC_PIN_GROUP(vin1_sync),
  3964. SH_PFC_PIN_GROUP(vin1_field),
  3965. SH_PFC_PIN_GROUP(vin1_clkenb),
  3966. SH_PFC_PIN_GROUP(vin1_clk),
  3967. };
  3968. static const char * const audio_clk_groups[] = {
  3969. "audio_clka",
  3970. "audio_clka_b",
  3971. "audio_clka_c",
  3972. "audio_clka_d",
  3973. "audio_clkb",
  3974. "audio_clkb_b",
  3975. "audio_clkb_c",
  3976. "audio_clkc",
  3977. "audio_clkc_b",
  3978. "audio_clkc_c",
  3979. "audio_clkout",
  3980. "audio_clkout_b",
  3981. "audio_clkout_c",
  3982. };
  3983. static const char * const avb_groups[] = {
  3984. "avb_link",
  3985. "avb_magic",
  3986. "avb_phy_int",
  3987. "avb_mdio",
  3988. "avb_mii",
  3989. "avb_gmii",
  3990. };
  3991. static const char * const can0_groups[] = {
  3992. "can0_data",
  3993. "can0_data_b",
  3994. "can0_data_c",
  3995. "can0_data_d",
  3996. /*
  3997. * Retained for backwards compatibility, use can_clk_groups in new
  3998. * designs.
  3999. */
  4000. "can_clk",
  4001. "can_clk_b",
  4002. "can_clk_c",
  4003. "can_clk_d",
  4004. };
  4005. static const char * const can1_groups[] = {
  4006. "can1_data",
  4007. "can1_data_b",
  4008. "can1_data_c",
  4009. "can1_data_d",
  4010. /*
  4011. * Retained for backwards compatibility, use can_clk_groups in new
  4012. * designs.
  4013. */
  4014. "can_clk",
  4015. "can_clk_b",
  4016. "can_clk_c",
  4017. "can_clk_d",
  4018. };
  4019. /*
  4020. * can_clk_groups allows for independent configuration, use can_clk function
  4021. * in new designs.
  4022. */
  4023. static const char * const can_clk_groups[] = {
  4024. "can_clk",
  4025. "can_clk_b",
  4026. "can_clk_c",
  4027. "can_clk_d",
  4028. };
  4029. static const char * const du0_groups[] = {
  4030. "du0_rgb666",
  4031. "du0_rgb888",
  4032. "du0_clk0_out",
  4033. "du0_clk1_out",
  4034. "du0_clk_in",
  4035. "du0_sync",
  4036. "du0_oddf",
  4037. "du0_cde",
  4038. "du0_disp",
  4039. };
  4040. static const char * const du1_groups[] = {
  4041. "du1_rgb666",
  4042. "du1_rgb888",
  4043. "du1_clk0_out",
  4044. "du1_clk1_out",
  4045. "du1_clk_in",
  4046. "du1_sync",
  4047. "du1_oddf",
  4048. "du1_cde",
  4049. "du1_disp",
  4050. };
  4051. static const char * const eth_groups[] = {
  4052. "eth_link",
  4053. "eth_magic",
  4054. "eth_mdio",
  4055. "eth_rmii",
  4056. "eth_link_b",
  4057. "eth_magic_b",
  4058. "eth_mdio_b",
  4059. "eth_rmii_b",
  4060. };
  4061. static const char * const hscif0_groups[] = {
  4062. "hscif0_data",
  4063. "hscif0_clk",
  4064. "hscif0_ctrl",
  4065. "hscif0_data_b",
  4066. "hscif0_clk_b",
  4067. };
  4068. static const char * const hscif1_groups[] = {
  4069. "hscif1_data",
  4070. "hscif1_clk",
  4071. "hscif1_ctrl",
  4072. "hscif1_data_b",
  4073. "hscif1_ctrl_b",
  4074. };
  4075. static const char * const hscif2_groups[] = {
  4076. "hscif2_data",
  4077. "hscif2_clk",
  4078. "hscif2_ctrl",
  4079. };
  4080. static const char * const i2c0_groups[] = {
  4081. "i2c0",
  4082. "i2c0_b",
  4083. "i2c0_c",
  4084. "i2c0_d",
  4085. "i2c0_e",
  4086. };
  4087. static const char * const i2c1_groups[] = {
  4088. "i2c1",
  4089. "i2c1_b",
  4090. "i2c1_c",
  4091. "i2c1_d",
  4092. "i2c1_e",
  4093. };
  4094. static const char * const i2c2_groups[] = {
  4095. "i2c2",
  4096. "i2c2_b",
  4097. "i2c2_c",
  4098. "i2c2_d",
  4099. "i2c2_e",
  4100. };
  4101. static const char * const i2c3_groups[] = {
  4102. "i2c3",
  4103. "i2c3_b",
  4104. "i2c3_c",
  4105. "i2c3_d",
  4106. "i2c3_e",
  4107. };
  4108. static const char * const i2c4_groups[] = {
  4109. "i2c4",
  4110. "i2c4_b",
  4111. "i2c4_c",
  4112. "i2c4_d",
  4113. "i2c4_e",
  4114. };
  4115. static const char * const i2c5_groups[] = {
  4116. "i2c5",
  4117. "i2c5_b",
  4118. "i2c5_c",
  4119. "i2c5_d",
  4120. };
  4121. static const char * const intc_groups[] = {
  4122. "intc_irq0",
  4123. "intc_irq1",
  4124. "intc_irq2",
  4125. "intc_irq3",
  4126. "intc_irq4",
  4127. "intc_irq5",
  4128. "intc_irq6",
  4129. "intc_irq7",
  4130. "intc_irq8",
  4131. "intc_irq9",
  4132. };
  4133. static const char * const mmc_groups[] = {
  4134. "mmc_data1",
  4135. "mmc_data4",
  4136. "mmc_data8",
  4137. "mmc_ctrl",
  4138. };
  4139. static const char * const msiof0_groups[] = {
  4140. "msiof0_clk",
  4141. "msiof0_sync",
  4142. "msiof0_ss1",
  4143. "msiof0_ss2",
  4144. "msiof0_rx",
  4145. "msiof0_tx",
  4146. };
  4147. static const char * const msiof1_groups[] = {
  4148. "msiof1_clk",
  4149. "msiof1_sync",
  4150. "msiof1_ss1",
  4151. "msiof1_ss2",
  4152. "msiof1_rx",
  4153. "msiof1_tx",
  4154. "msiof1_clk_b",
  4155. "msiof1_sync_b",
  4156. "msiof1_ss1_b",
  4157. "msiof1_ss2_b",
  4158. "msiof1_rx_b",
  4159. "msiof1_tx_b",
  4160. };
  4161. static const char * const msiof2_groups[] = {
  4162. "msiof2_clk",
  4163. "msiof2_sync",
  4164. "msiof2_ss1",
  4165. "msiof2_ss2",
  4166. "msiof2_rx",
  4167. "msiof2_tx",
  4168. "msiof2_clk_b",
  4169. "msiof2_sync_b",
  4170. "msiof2_ss1_b",
  4171. "msiof2_ss2_b",
  4172. "msiof2_rx_b",
  4173. "msiof2_tx_b",
  4174. };
  4175. static const char * const pwm0_groups[] = {
  4176. "pwm0",
  4177. "pwm0_b",
  4178. };
  4179. static const char * const pwm1_groups[] = {
  4180. "pwm1",
  4181. "pwm1_b",
  4182. "pwm1_c",
  4183. };
  4184. static const char * const pwm2_groups[] = {
  4185. "pwm2",
  4186. "pwm2_b",
  4187. "pwm2_c",
  4188. };
  4189. static const char * const pwm3_groups[] = {
  4190. "pwm3",
  4191. "pwm3_b",
  4192. };
  4193. static const char * const pwm4_groups[] = {
  4194. "pwm4",
  4195. "pwm4_b",
  4196. };
  4197. static const char * const pwm5_groups[] = {
  4198. "pwm5",
  4199. "pwm5_b",
  4200. "pwm5_c",
  4201. };
  4202. static const char * const pwm6_groups[] = {
  4203. "pwm6",
  4204. "pwm6_b",
  4205. };
  4206. static const char * const qspi_groups[] = {
  4207. "qspi_ctrl",
  4208. "qspi_data2",
  4209. "qspi_data4",
  4210. };
  4211. static const char * const scif0_groups[] = {
  4212. "scif0_data",
  4213. "scif0_data_b",
  4214. "scif0_data_c",
  4215. "scif0_data_d",
  4216. };
  4217. static const char * const scif1_groups[] = {
  4218. "scif1_data",
  4219. "scif1_clk",
  4220. "scif1_data_b",
  4221. "scif1_clk_b",
  4222. "scif1_data_c",
  4223. "scif1_clk_c",
  4224. };
  4225. static const char * const scif2_groups[] = {
  4226. "scif2_data",
  4227. "scif2_clk",
  4228. "scif2_data_b",
  4229. "scif2_clk_b",
  4230. "scif2_data_c",
  4231. "scif2_clk_c",
  4232. };
  4233. static const char * const scif3_groups[] = {
  4234. "scif3_data",
  4235. "scif3_clk",
  4236. "scif3_data_b",
  4237. "scif3_clk_b",
  4238. };
  4239. static const char * const scif4_groups[] = {
  4240. "scif4_data",
  4241. "scif4_data_b",
  4242. "scif4_data_c",
  4243. "scif4_data_d",
  4244. "scif4_data_e",
  4245. };
  4246. static const char * const scif5_groups[] = {
  4247. "scif5_data",
  4248. "scif5_data_b",
  4249. "scif5_data_c",
  4250. "scif5_data_d",
  4251. };
  4252. static const char * const scifa0_groups[] = {
  4253. "scifa0_data",
  4254. "scifa0_data_b",
  4255. "scifa0_data_c",
  4256. "scifa0_data_d",
  4257. };
  4258. static const char * const scifa1_groups[] = {
  4259. "scifa1_data",
  4260. "scifa1_clk",
  4261. "scifa1_data_b",
  4262. "scifa1_clk_b",
  4263. "scifa1_data_c",
  4264. "scifa1_clk_c",
  4265. };
  4266. static const char * const scifa2_groups[] = {
  4267. "scifa2_data",
  4268. "scifa2_clk",
  4269. "scifa2_data_b",
  4270. "scifa2_clk_b",
  4271. };
  4272. static const char * const scifa3_groups[] = {
  4273. "scifa3_data",
  4274. "scifa3_clk",
  4275. "scifa3_data_b",
  4276. "scifa3_clk_b",
  4277. };
  4278. static const char * const scifa4_groups[] = {
  4279. "scifa4_data",
  4280. "scifa4_data_b",
  4281. "scifa4_data_c",
  4282. "scifa4_data_d",
  4283. };
  4284. static const char * const scifa5_groups[] = {
  4285. "scifa5_data",
  4286. "scifa5_data_b",
  4287. "scifa5_data_c",
  4288. "scifa5_data_d",
  4289. };
  4290. static const char * const scifb0_groups[] = {
  4291. "scifb0_data",
  4292. "scifb0_clk",
  4293. "scifb0_ctrl",
  4294. };
  4295. static const char * const scifb1_groups[] = {
  4296. "scifb1_data",
  4297. "scifb1_clk",
  4298. };
  4299. static const char * const scifb2_groups[] = {
  4300. "scifb2_data",
  4301. "scifb2_clk",
  4302. "scifb2_ctrl",
  4303. };
  4304. static const char * const scif_clk_groups[] = {
  4305. "scif_clk",
  4306. "scif_clk_b",
  4307. };
  4308. static const char * const sdhi0_groups[] = {
  4309. "sdhi0_data1",
  4310. "sdhi0_data4",
  4311. "sdhi0_ctrl",
  4312. "sdhi0_cd",
  4313. "sdhi0_wp",
  4314. };
  4315. static const char * const sdhi1_groups[] = {
  4316. "sdhi1_data1",
  4317. "sdhi1_data4",
  4318. "sdhi1_ctrl",
  4319. "sdhi1_cd",
  4320. "sdhi1_wp",
  4321. };
  4322. static const char * const sdhi2_groups[] = {
  4323. "sdhi2_data1",
  4324. "sdhi2_data4",
  4325. "sdhi2_ctrl",
  4326. "sdhi2_cd",
  4327. "sdhi2_wp",
  4328. };
  4329. static const char * const ssi_groups[] = {
  4330. "ssi0_data",
  4331. "ssi0129_ctrl",
  4332. "ssi1_data",
  4333. "ssi1_ctrl",
  4334. "ssi1_data_b",
  4335. "ssi1_ctrl_b",
  4336. "ssi2_data",
  4337. "ssi2_ctrl",
  4338. "ssi2_data_b",
  4339. "ssi2_ctrl_b",
  4340. "ssi3_data",
  4341. "ssi34_ctrl",
  4342. "ssi4_data",
  4343. "ssi4_ctrl",
  4344. "ssi4_data_b",
  4345. "ssi4_ctrl_b",
  4346. "ssi5_data",
  4347. "ssi5_ctrl",
  4348. "ssi5_data_b",
  4349. "ssi5_ctrl_b",
  4350. "ssi6_data",
  4351. "ssi6_ctrl",
  4352. "ssi6_data_b",
  4353. "ssi6_ctrl_b",
  4354. "ssi7_data",
  4355. "ssi78_ctrl",
  4356. "ssi7_data_b",
  4357. "ssi78_ctrl_b",
  4358. "ssi8_data",
  4359. "ssi8_data_b",
  4360. "ssi9_data",
  4361. "ssi9_ctrl",
  4362. "ssi9_data_b",
  4363. "ssi9_ctrl_b",
  4364. };
  4365. static const char * const tpu_groups[] = {
  4366. "tpu_to0",
  4367. "tpu_to0_b",
  4368. "tpu_to0_c",
  4369. "tpu_to1",
  4370. "tpu_to1_b",
  4371. "tpu_to1_c",
  4372. "tpu_to2",
  4373. "tpu_to2_b",
  4374. "tpu_to2_c",
  4375. "tpu_to3",
  4376. "tpu_to3_b",
  4377. "tpu_to3_c",
  4378. };
  4379. static const char * const usb0_groups[] = {
  4380. "usb0",
  4381. };
  4382. static const char * const usb1_groups[] = {
  4383. "usb1",
  4384. };
  4385. static const char * const vin0_groups[] = {
  4386. "vin0_data24",
  4387. "vin0_data20",
  4388. "vin0_data18",
  4389. "vin0_data16",
  4390. "vin0_data12",
  4391. "vin0_data10",
  4392. "vin0_data8",
  4393. "vin0_sync",
  4394. "vin0_field",
  4395. "vin0_clkenb",
  4396. "vin0_clk",
  4397. };
  4398. static const char * const vin1_groups[] = {
  4399. "vin1_data12",
  4400. "vin1_data10",
  4401. "vin1_data8",
  4402. "vin1_sync",
  4403. "vin1_field",
  4404. "vin1_clkenb",
  4405. "vin1_clk",
  4406. };
  4407. static const struct sh_pfc_function pinmux_functions[] = {
  4408. SH_PFC_FUNCTION(audio_clk),
  4409. SH_PFC_FUNCTION(avb),
  4410. SH_PFC_FUNCTION(can0),
  4411. SH_PFC_FUNCTION(can1),
  4412. SH_PFC_FUNCTION(can_clk),
  4413. SH_PFC_FUNCTION(du0),
  4414. SH_PFC_FUNCTION(du1),
  4415. SH_PFC_FUNCTION(eth),
  4416. SH_PFC_FUNCTION(hscif0),
  4417. SH_PFC_FUNCTION(hscif1),
  4418. SH_PFC_FUNCTION(hscif2),
  4419. SH_PFC_FUNCTION(i2c0),
  4420. SH_PFC_FUNCTION(i2c1),
  4421. SH_PFC_FUNCTION(i2c2),
  4422. SH_PFC_FUNCTION(i2c3),
  4423. SH_PFC_FUNCTION(i2c4),
  4424. SH_PFC_FUNCTION(i2c5),
  4425. SH_PFC_FUNCTION(intc),
  4426. SH_PFC_FUNCTION(mmc),
  4427. SH_PFC_FUNCTION(msiof0),
  4428. SH_PFC_FUNCTION(msiof1),
  4429. SH_PFC_FUNCTION(msiof2),
  4430. SH_PFC_FUNCTION(pwm0),
  4431. SH_PFC_FUNCTION(pwm1),
  4432. SH_PFC_FUNCTION(pwm2),
  4433. SH_PFC_FUNCTION(pwm3),
  4434. SH_PFC_FUNCTION(pwm4),
  4435. SH_PFC_FUNCTION(pwm5),
  4436. SH_PFC_FUNCTION(pwm6),
  4437. SH_PFC_FUNCTION(qspi),
  4438. SH_PFC_FUNCTION(scif0),
  4439. SH_PFC_FUNCTION(scif1),
  4440. SH_PFC_FUNCTION(scif2),
  4441. SH_PFC_FUNCTION(scif3),
  4442. SH_PFC_FUNCTION(scif4),
  4443. SH_PFC_FUNCTION(scif5),
  4444. SH_PFC_FUNCTION(scifa0),
  4445. SH_PFC_FUNCTION(scifa1),
  4446. SH_PFC_FUNCTION(scifa2),
  4447. SH_PFC_FUNCTION(scifa3),
  4448. SH_PFC_FUNCTION(scifa4),
  4449. SH_PFC_FUNCTION(scifa5),
  4450. SH_PFC_FUNCTION(scifb0),
  4451. SH_PFC_FUNCTION(scifb1),
  4452. SH_PFC_FUNCTION(scifb2),
  4453. SH_PFC_FUNCTION(scif_clk),
  4454. SH_PFC_FUNCTION(sdhi0),
  4455. SH_PFC_FUNCTION(sdhi1),
  4456. SH_PFC_FUNCTION(sdhi2),
  4457. SH_PFC_FUNCTION(ssi),
  4458. SH_PFC_FUNCTION(tpu),
  4459. SH_PFC_FUNCTION(usb0),
  4460. SH_PFC_FUNCTION(usb1),
  4461. SH_PFC_FUNCTION(vin0),
  4462. SH_PFC_FUNCTION(vin1),
  4463. };
  4464. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4465. { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
  4466. GP_0_31_FN, FN_IP2_17_16,
  4467. GP_0_30_FN, FN_IP2_15_14,
  4468. GP_0_29_FN, FN_IP2_13_12,
  4469. GP_0_28_FN, FN_IP2_11_10,
  4470. GP_0_27_FN, FN_IP2_9_8,
  4471. GP_0_26_FN, FN_IP2_7_6,
  4472. GP_0_25_FN, FN_IP2_5_4,
  4473. GP_0_24_FN, FN_IP2_3_2,
  4474. GP_0_23_FN, FN_IP2_1_0,
  4475. GP_0_22_FN, FN_IP1_31_30,
  4476. GP_0_21_FN, FN_IP1_29_28,
  4477. GP_0_20_FN, FN_IP1_27,
  4478. GP_0_19_FN, FN_IP1_26,
  4479. GP_0_18_FN, FN_A2,
  4480. GP_0_17_FN, FN_IP1_24,
  4481. GP_0_16_FN, FN_IP1_23_22,
  4482. GP_0_15_FN, FN_IP1_21_20,
  4483. GP_0_14_FN, FN_IP1_19_18,
  4484. GP_0_13_FN, FN_IP1_17_15,
  4485. GP_0_12_FN, FN_IP1_14_13,
  4486. GP_0_11_FN, FN_IP1_12_11,
  4487. GP_0_10_FN, FN_IP1_10_8,
  4488. GP_0_9_FN, FN_IP1_7_6,
  4489. GP_0_8_FN, FN_IP1_5_4,
  4490. GP_0_7_FN, FN_IP1_3_2,
  4491. GP_0_6_FN, FN_IP1_1_0,
  4492. GP_0_5_FN, FN_IP0_31_30,
  4493. GP_0_4_FN, FN_IP0_29_28,
  4494. GP_0_3_FN, FN_IP0_27_26,
  4495. GP_0_2_FN, FN_IP0_25,
  4496. GP_0_1_FN, FN_IP0_24,
  4497. GP_0_0_FN, FN_IP0_23_22, ))
  4498. },
  4499. { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
  4500. 0, 0,
  4501. 0, 0,
  4502. 0, 0,
  4503. 0, 0,
  4504. 0, 0,
  4505. 0, 0,
  4506. GP_1_25_FN, FN_DACK0,
  4507. GP_1_24_FN, FN_IP7_31,
  4508. GP_1_23_FN, FN_IP4_1_0,
  4509. GP_1_22_FN, FN_WE1_N,
  4510. GP_1_21_FN, FN_WE0_N,
  4511. GP_1_20_FN, FN_IP3_31,
  4512. GP_1_19_FN, FN_IP3_30,
  4513. GP_1_18_FN, FN_IP3_29_27,
  4514. GP_1_17_FN, FN_IP3_26_24,
  4515. GP_1_16_FN, FN_IP3_23_21,
  4516. GP_1_15_FN, FN_IP3_20_18,
  4517. GP_1_14_FN, FN_IP3_17_15,
  4518. GP_1_13_FN, FN_IP3_14_13,
  4519. GP_1_12_FN, FN_IP3_12,
  4520. GP_1_11_FN, FN_IP3_11,
  4521. GP_1_10_FN, FN_IP3_10,
  4522. GP_1_9_FN, FN_IP3_9_8,
  4523. GP_1_8_FN, FN_IP3_7_6,
  4524. GP_1_7_FN, FN_IP3_5_4,
  4525. GP_1_6_FN, FN_IP3_3_2,
  4526. GP_1_5_FN, FN_IP3_1_0,
  4527. GP_1_4_FN, FN_IP2_31_30,
  4528. GP_1_3_FN, FN_IP2_29_27,
  4529. GP_1_2_FN, FN_IP2_26_24,
  4530. GP_1_1_FN, FN_IP2_23_21,
  4531. GP_1_0_FN, FN_IP2_20_18, ))
  4532. },
  4533. { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
  4534. GP_2_31_FN, FN_IP6_7_6,
  4535. GP_2_30_FN, FN_IP6_5_4,
  4536. GP_2_29_FN, FN_IP6_3_2,
  4537. GP_2_28_FN, FN_IP6_1_0,
  4538. GP_2_27_FN, FN_IP5_31_30,
  4539. GP_2_26_FN, FN_IP5_29_28,
  4540. GP_2_25_FN, FN_IP5_27_26,
  4541. GP_2_24_FN, FN_IP5_25_24,
  4542. GP_2_23_FN, FN_IP5_23_22,
  4543. GP_2_22_FN, FN_IP5_21_20,
  4544. GP_2_21_FN, FN_IP5_19_18,
  4545. GP_2_20_FN, FN_IP5_17_16,
  4546. GP_2_19_FN, FN_IP5_15_14,
  4547. GP_2_18_FN, FN_IP5_13_12,
  4548. GP_2_17_FN, FN_IP5_11_9,
  4549. GP_2_16_FN, FN_IP5_8_6,
  4550. GP_2_15_FN, FN_IP5_5_4,
  4551. GP_2_14_FN, FN_IP5_3_2,
  4552. GP_2_13_FN, FN_IP5_1_0,
  4553. GP_2_12_FN, FN_IP4_31_30,
  4554. GP_2_11_FN, FN_IP4_29_28,
  4555. GP_2_10_FN, FN_IP4_27_26,
  4556. GP_2_9_FN, FN_IP4_25_23,
  4557. GP_2_8_FN, FN_IP4_22_20,
  4558. GP_2_7_FN, FN_IP4_19_18,
  4559. GP_2_6_FN, FN_IP4_17_16,
  4560. GP_2_5_FN, FN_IP4_15_14,
  4561. GP_2_4_FN, FN_IP4_13_12,
  4562. GP_2_3_FN, FN_IP4_11_10,
  4563. GP_2_2_FN, FN_IP4_9_8,
  4564. GP_2_1_FN, FN_IP4_7_5,
  4565. GP_2_0_FN, FN_IP4_4_2 ))
  4566. },
  4567. { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
  4568. GP_3_31_FN, FN_IP8_22_20,
  4569. GP_3_30_FN, FN_IP8_19_17,
  4570. GP_3_29_FN, FN_IP8_16_15,
  4571. GP_3_28_FN, FN_IP8_14_12,
  4572. GP_3_27_FN, FN_IP8_11_9,
  4573. GP_3_26_FN, FN_IP8_8_6,
  4574. GP_3_25_FN, FN_IP8_5_3,
  4575. GP_3_24_FN, FN_IP8_2_0,
  4576. GP_3_23_FN, FN_IP7_29_27,
  4577. GP_3_22_FN, FN_IP7_26_24,
  4578. GP_3_21_FN, FN_IP7_23_21,
  4579. GP_3_20_FN, FN_IP7_20_18,
  4580. GP_3_19_FN, FN_IP7_17_15,
  4581. GP_3_18_FN, FN_IP7_14_12,
  4582. GP_3_17_FN, FN_IP7_11_9,
  4583. GP_3_16_FN, FN_IP7_8_6,
  4584. GP_3_15_FN, FN_IP7_5_3,
  4585. GP_3_14_FN, FN_IP7_2_0,
  4586. GP_3_13_FN, FN_IP6_31_29,
  4587. GP_3_12_FN, FN_IP6_28_26,
  4588. GP_3_11_FN, FN_IP6_25_23,
  4589. GP_3_10_FN, FN_IP6_22_20,
  4590. GP_3_9_FN, FN_IP6_19_17,
  4591. GP_3_8_FN, FN_IP6_16,
  4592. GP_3_7_FN, FN_IP6_15,
  4593. GP_3_6_FN, FN_IP6_14,
  4594. GP_3_5_FN, FN_IP6_13,
  4595. GP_3_4_FN, FN_IP6_12,
  4596. GP_3_3_FN, FN_IP6_11,
  4597. GP_3_2_FN, FN_IP6_10,
  4598. GP_3_1_FN, FN_IP6_9,
  4599. GP_3_0_FN, FN_IP6_8 ))
  4600. },
  4601. { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
  4602. GP_4_31_FN, FN_IP11_17_16,
  4603. GP_4_30_FN, FN_IP11_15_14,
  4604. GP_4_29_FN, FN_IP11_13_11,
  4605. GP_4_28_FN, FN_IP11_10_8,
  4606. GP_4_27_FN, FN_IP11_7_6,
  4607. GP_4_26_FN, FN_IP11_5_3,
  4608. GP_4_25_FN, FN_IP11_2_0,
  4609. GP_4_24_FN, FN_IP10_31_30,
  4610. GP_4_23_FN, FN_IP10_29_27,
  4611. GP_4_22_FN, FN_IP10_26_24,
  4612. GP_4_21_FN, FN_IP10_23_21,
  4613. GP_4_20_FN, FN_IP10_20_18,
  4614. GP_4_19_FN, FN_IP10_17_15,
  4615. GP_4_18_FN, FN_IP10_14_12,
  4616. GP_4_17_FN, FN_IP10_11_9,
  4617. GP_4_16_FN, FN_IP10_8_6,
  4618. GP_4_15_FN, FN_IP10_5_3,
  4619. GP_4_14_FN, FN_IP10_2_0,
  4620. GP_4_13_FN, FN_IP9_30_28,
  4621. GP_4_12_FN, FN_IP9_27_25,
  4622. GP_4_11_FN, FN_IP9_24_22,
  4623. GP_4_10_FN, FN_IP9_21_19,
  4624. GP_4_9_FN, FN_IP9_18_17,
  4625. GP_4_8_FN, FN_IP9_16_15,
  4626. GP_4_7_FN, FN_IP9_14_12,
  4627. GP_4_6_FN, FN_IP9_11_9,
  4628. GP_4_5_FN, FN_IP9_8_6,
  4629. GP_4_4_FN, FN_IP9_5_3,
  4630. GP_4_3_FN, FN_IP9_2_0,
  4631. GP_4_2_FN, FN_IP8_31_29,
  4632. GP_4_1_FN, FN_IP8_28_26,
  4633. GP_4_0_FN, FN_IP8_25_23 ))
  4634. },
  4635. { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
  4636. 0, 0,
  4637. 0, 0,
  4638. 0, 0,
  4639. 0, 0,
  4640. GP_5_27_FN, FN_USB1_OVC,
  4641. GP_5_26_FN, FN_USB1_PWEN,
  4642. GP_5_25_FN, FN_USB0_OVC,
  4643. GP_5_24_FN, FN_USB0_PWEN,
  4644. GP_5_23_FN, FN_IP13_26_24,
  4645. GP_5_22_FN, FN_IP13_23_21,
  4646. GP_5_21_FN, FN_IP13_20_18,
  4647. GP_5_20_FN, FN_IP13_17_15,
  4648. GP_5_19_FN, FN_IP13_14_12,
  4649. GP_5_18_FN, FN_IP13_11_9,
  4650. GP_5_17_FN, FN_IP13_8_6,
  4651. GP_5_16_FN, FN_IP13_5_3,
  4652. GP_5_15_FN, FN_IP13_2_0,
  4653. GP_5_14_FN, FN_IP12_29_27,
  4654. GP_5_13_FN, FN_IP12_26_24,
  4655. GP_5_12_FN, FN_IP12_23_21,
  4656. GP_5_11_FN, FN_IP12_20_18,
  4657. GP_5_10_FN, FN_IP12_17_15,
  4658. GP_5_9_FN, FN_IP12_14_13,
  4659. GP_5_8_FN, FN_IP12_12_11,
  4660. GP_5_7_FN, FN_IP12_10_9,
  4661. GP_5_6_FN, FN_IP12_8_6,
  4662. GP_5_5_FN, FN_IP12_5_3,
  4663. GP_5_4_FN, FN_IP12_2_0,
  4664. GP_5_3_FN, FN_IP11_29_27,
  4665. GP_5_2_FN, FN_IP11_26_24,
  4666. GP_5_1_FN, FN_IP11_23_21,
  4667. GP_5_0_FN, FN_IP11_20_18 ))
  4668. },
  4669. { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
  4670. 0, 0,
  4671. 0, 0,
  4672. 0, 0,
  4673. 0, 0,
  4674. 0, 0,
  4675. 0, 0,
  4676. GP_6_25_FN, FN_IP0_21_20,
  4677. GP_6_24_FN, FN_IP0_19_18,
  4678. GP_6_23_FN, FN_IP0_17,
  4679. GP_6_22_FN, FN_IP0_16,
  4680. GP_6_21_FN, FN_IP0_15,
  4681. GP_6_20_FN, FN_IP0_14,
  4682. GP_6_19_FN, FN_IP0_13,
  4683. GP_6_18_FN, FN_IP0_12,
  4684. GP_6_17_FN, FN_IP0_11,
  4685. GP_6_16_FN, FN_IP0_10,
  4686. GP_6_15_FN, FN_IP0_9_8,
  4687. GP_6_14_FN, FN_IP0_0,
  4688. GP_6_13_FN, FN_SD1_DATA3,
  4689. GP_6_12_FN, FN_SD1_DATA2,
  4690. GP_6_11_FN, FN_SD1_DATA1,
  4691. GP_6_10_FN, FN_SD1_DATA0,
  4692. GP_6_9_FN, FN_SD1_CMD,
  4693. GP_6_8_FN, FN_SD1_CLK,
  4694. GP_6_7_FN, FN_SD0_WP,
  4695. GP_6_6_FN, FN_SD0_CD,
  4696. GP_6_5_FN, FN_SD0_DATA3,
  4697. GP_6_4_FN, FN_SD0_DATA2,
  4698. GP_6_3_FN, FN_SD0_DATA1,
  4699. GP_6_2_FN, FN_SD0_DATA0,
  4700. GP_6_1_FN, FN_SD0_CMD,
  4701. GP_6_0_FN, FN_SD0_CLK ))
  4702. },
  4703. { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
  4704. GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
  4705. 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
  4706. GROUP(
  4707. /* IP0_31_30 [2] */
  4708. FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
  4709. /* IP0_29_28 [2] */
  4710. FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
  4711. /* IP0_27_26 [2] */
  4712. FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
  4713. /* IP0_25 [1] */
  4714. FN_D2, FN_SCIFA3_TXD_B,
  4715. /* IP0_24 [1] */
  4716. FN_D1, FN_SCIFA3_RXD_B,
  4717. /* IP0_23_22 [2] */
  4718. FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
  4719. /* IP0_21_20 [2] */
  4720. FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
  4721. /* IP0_19_18 [2] */
  4722. FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
  4723. /* IP0_17 [1] */
  4724. FN_MMC_D5, FN_SD2_WP,
  4725. /* IP0_16 [1] */
  4726. FN_MMC_D4, FN_SD2_CD,
  4727. /* IP0_15 [1] */
  4728. FN_MMC_D3, FN_SD2_DATA3,
  4729. /* IP0_14 [1] */
  4730. FN_MMC_D2, FN_SD2_DATA2,
  4731. /* IP0_13 [1] */
  4732. FN_MMC_D1, FN_SD2_DATA1,
  4733. /* IP0_12 [1] */
  4734. FN_MMC_D0, FN_SD2_DATA0,
  4735. /* IP0_11 [1] */
  4736. FN_MMC_CMD, FN_SD2_CMD,
  4737. /* IP0_10 [1] */
  4738. FN_MMC_CLK, FN_SD2_CLK,
  4739. /* IP0_9_8 [2] */
  4740. FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
  4741. /* IP0_7 [1] */
  4742. 0, 0,
  4743. /* IP0_6 [1] */
  4744. 0, 0,
  4745. /* IP0_5 [1] */
  4746. 0, 0,
  4747. /* IP0_4 [1] */
  4748. 0, 0,
  4749. /* IP0_3 [1] */
  4750. 0, 0,
  4751. /* IP0_2 [1] */
  4752. 0, 0,
  4753. /* IP0_1 [1] */
  4754. 0, 0,
  4755. /* IP0_0 [1] */
  4756. FN_SD1_CD, FN_CAN0_RX, ))
  4757. },
  4758. { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
  4759. GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
  4760. 3, 2, 2, 2, 2),
  4761. GROUP(
  4762. /* IP1_31_30 [2] */
  4763. FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
  4764. /* IP1_29_28 [2] */
  4765. FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
  4766. /* IP1_27 [1] */
  4767. FN_A4, FN_SCIFB0_TXD,
  4768. /* IP1_26 [1] */
  4769. FN_A3, FN_SCIFB0_SCK,
  4770. /* IP1_25 [1] */
  4771. 0, 0,
  4772. /* IP1_24 [1] */
  4773. FN_A1, FN_SCIFB1_TXD,
  4774. /* IP1_23_22 [2] */
  4775. FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
  4776. /* IP1_21_20 [2] */
  4777. FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
  4778. /* IP1_19_18 [2] */
  4779. FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
  4780. /* IP1_17_15 [3] */
  4781. FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
  4782. 0, 0, 0,
  4783. /* IP1_14_13 [2] */
  4784. FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
  4785. /* IP1_12_11 [2] */
  4786. FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
  4787. /* IP1_10_8 [3] */
  4788. FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
  4789. 0, 0, 0,
  4790. /* IP1_7_6 [2] */
  4791. FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
  4792. /* IP1_5_4 [2] */
  4793. FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
  4794. /* IP1_3_2 [2] */
  4795. FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
  4796. /* IP1_1_0 [2] */
  4797. FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
  4798. },
  4799. { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
  4800. GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
  4801. GROUP(
  4802. /* IP2_31_30 [2] */
  4803. FN_A20, FN_SPCLK, 0, 0,
  4804. /* IP2_29_27 [3] */
  4805. FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
  4806. 0, 0, 0, 0,
  4807. /* IP2_26_24 [3] */
  4808. FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
  4809. 0, 0, 0, 0,
  4810. /* IP2_23_21 [3] */
  4811. FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
  4812. 0, 0, 0, 0,
  4813. /* IP2_20_18 [3] */
  4814. FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
  4815. 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
  4816. /* IP2_17_16 [2] */
  4817. FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
  4818. /* IP2_15_14 [2] */
  4819. FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
  4820. /* IP2_13_12 [2] */
  4821. FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
  4822. /* IP2_11_10 [2] */
  4823. FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
  4824. /* IP2_9_8 [2] */
  4825. FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
  4826. /* IP2_7_6 [2] */
  4827. FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
  4828. /* IP2_5_4 [2] */
  4829. FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
  4830. /* IP2_3_2 [2] */
  4831. FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
  4832. /* IP2_1_0 [2] */
  4833. FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
  4834. },
  4835. { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
  4836. GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
  4837. 2, 2, 2, 2),
  4838. GROUP(
  4839. /* IP3_31 [1] */
  4840. FN_RD_WR_N, FN_ATAG1_N,
  4841. /* IP3_30 [1] */
  4842. FN_RD_N, FN_ATACS11_N,
  4843. /* IP3_29_27 [3] */
  4844. FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
  4845. 0, 0, 0,
  4846. /* IP3_26_24 [3] */
  4847. FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
  4848. 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
  4849. /* IP3_23_21 [3] */
  4850. FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
  4851. 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
  4852. /* IP3_20_18 [3] */
  4853. FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
  4854. 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
  4855. /* IP3_17_15 [3] */
  4856. FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
  4857. 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
  4858. /* IP3_14_13 [2] */
  4859. FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
  4860. /* IP3_12 [1] */
  4861. FN_EX_CS0_N, FN_VI1_DATA10,
  4862. /* IP3_11 [1] */
  4863. FN_CS1_N_A26, FN_VI1_DATA9,
  4864. /* IP3_10 [1] */
  4865. FN_CS0_N, FN_VI1_DATA8,
  4866. /* IP3_9_8 [2] */
  4867. FN_A25, FN_SSL, FN_ATARD1_N, 0,
  4868. /* IP3_7_6 [2] */
  4869. FN_A24, FN_IO3, FN_EX_WAIT2, 0,
  4870. /* IP3_5_4 [2] */
  4871. FN_A23, FN_IO2, 0, FN_ATAWR1_N,
  4872. /* IP3_3_2 [2] */
  4873. FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
  4874. /* IP3_1_0 [2] */
  4875. FN_A21, FN_MOSI_IO0, 0, 0, ))
  4876. },
  4877. { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
  4878. GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
  4879. GROUP(
  4880. /* IP4_31_30 [2] */
  4881. FN_DU0_DG4, FN_LCDOUT12, 0, 0,
  4882. /* IP4_29_28 [2] */
  4883. FN_DU0_DG3, FN_LCDOUT11, 0, 0,
  4884. /* IP4_27_26 [2] */
  4885. FN_DU0_DG2, FN_LCDOUT10, 0, 0,
  4886. /* IP4_25_23 [3] */
  4887. FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
  4888. 0, 0, 0, 0,
  4889. /* IP4_22_20 [3] */
  4890. FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
  4891. 0, 0, 0, 0,
  4892. /* IP4_19_18 [2] */
  4893. FN_DU0_DR7, FN_LCDOUT23, 0, 0,
  4894. /* IP4_17_16 [2] */
  4895. FN_DU0_DR6, FN_LCDOUT22, 0, 0,
  4896. /* IP4_15_14 [2] */
  4897. FN_DU0_DR5, FN_LCDOUT21, 0, 0,
  4898. /* IP4_13_12 [2] */
  4899. FN_DU0_DR4, FN_LCDOUT20, 0, 0,
  4900. /* IP4_11_10 [2] */
  4901. FN_DU0_DR3, FN_LCDOUT19, 0, 0,
  4902. /* IP4_9_8 [2] */
  4903. FN_DU0_DR2, FN_LCDOUT18, 0, 0,
  4904. /* IP4_7_5 [3] */
  4905. FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
  4906. 0, 0, 0, 0,
  4907. /* IP4_4_2 [3] */
  4908. FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
  4909. 0, 0, 0, 0,
  4910. /* IP4_1_0 [2] */
  4911. FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
  4912. },
  4913. { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
  4914. GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
  4915. 2, 2, 2),
  4916. GROUP(
  4917. /* IP5_31_30 [2] */
  4918. FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
  4919. /* IP5_29_28 [2] */
  4920. FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
  4921. /* IP5_27_26 [2] */
  4922. FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
  4923. /* IP5_25_24 [2] */
  4924. FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
  4925. /* IP5_23_22 [2] */
  4926. FN_DU0_DB7, FN_LCDOUT7, 0, 0,
  4927. /* IP5_21_20 [2] */
  4928. FN_DU0_DB6, FN_LCDOUT6, 0, 0,
  4929. /* IP5_19_18 [2] */
  4930. FN_DU0_DB5, FN_LCDOUT5, 0, 0,
  4931. /* IP5_17_16 [2] */
  4932. FN_DU0_DB4, FN_LCDOUT4, 0, 0,
  4933. /* IP5_15_14 [2] */
  4934. FN_DU0_DB3, FN_LCDOUT3, 0, 0,
  4935. /* IP5_13_12 [2] */
  4936. FN_DU0_DB2, FN_LCDOUT2, 0, 0,
  4937. /* IP5_11_9 [3] */
  4938. FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
  4939. FN_CAN0_TX_C, 0, 0, 0,
  4940. /* IP5_8_6 [3] */
  4941. FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
  4942. FN_CAN0_RX_C, 0, 0, 0,
  4943. /* IP5_5_4 [2] */
  4944. FN_DU0_DG7, FN_LCDOUT15, 0, 0,
  4945. /* IP5_3_2 [2] */
  4946. FN_DU0_DG6, FN_LCDOUT14, 0, 0,
  4947. /* IP5_1_0 [2] */
  4948. FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
  4949. },
  4950. { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
  4951. GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
  4952. 1, 1, 2, 2, 2, 2),
  4953. GROUP(
  4954. /* IP6_31_29 [3] */
  4955. FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
  4956. FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
  4957. /* IP6_28_26 [3] */
  4958. FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
  4959. FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
  4960. /* IP6_25_23 [3] */
  4961. FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
  4962. FN_AVB_COL, 0, 0, 0,
  4963. /* IP6_22_20 [3] */
  4964. FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
  4965. FN_AVB_RX_ER, 0, 0, 0,
  4966. /* IP6_19_17 [3] */
  4967. FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
  4968. FN_AVB_RXD7, 0, 0, 0,
  4969. /* IP6_16 [1] */
  4970. FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
  4971. /* IP6_15 [1] */
  4972. FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
  4973. /* IP6_14 [1] */
  4974. FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
  4975. /* IP6_13 [1] */
  4976. FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
  4977. /* IP6_12 [1] */
  4978. FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
  4979. /* IP6_11 [1] */
  4980. FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
  4981. /* IP6_10 [1] */
  4982. FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
  4983. /* IP6_9 [1] */
  4984. FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
  4985. /* IP6_8 [1] */
  4986. FN_VI0_CLK, FN_AVB_RX_CLK,
  4987. /* IP6_7_6 [2] */
  4988. FN_DU0_CDE, FN_QPOLB, 0, 0,
  4989. /* IP6_5_4 [2] */
  4990. FN_DU0_DISP, FN_QPOLA, 0, 0,
  4991. /* IP6_3_2 [2] */
  4992. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
  4993. 0,
  4994. /* IP6_1_0 [2] */
  4995. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
  4996. },
  4997. { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
  4998. GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  4999. GROUP(
  5000. /* IP7_31 [1] */
  5001. FN_DREQ0_N, FN_SCIFB1_RXD,
  5002. /* IP7_30 [1] */
  5003. 0, 0,
  5004. /* IP7_29_27 [3] */
  5005. FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
  5006. FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
  5007. /* IP7_26_24 [3] */
  5008. FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
  5009. FN_SSI_SCK6_B, 0, 0, 0,
  5010. /* IP7_23_21 [3] */
  5011. FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
  5012. FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
  5013. /* IP7_20_18 [3] */
  5014. FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
  5015. FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
  5016. /* IP7_17_15 [3] */
  5017. FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
  5018. FN_SSI_SCK5_B, 0, 0, 0,
  5019. /* IP7_14_12 [3] */
  5020. FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
  5021. FN_AVB_TXD4, FN_ADICHS2, 0, 0,
  5022. /* IP7_11_9 [3] */
  5023. FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
  5024. FN_AVB_TXD3, FN_ADICHS1, 0, 0,
  5025. /* IP7_8_6 [3] */
  5026. FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
  5027. FN_AVB_TXD2, FN_ADICHS0, 0, 0,
  5028. /* IP7_5_3 [3] */
  5029. FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
  5030. FN_AVB_TXD1, FN_ADICLK, 0, 0,
  5031. /* IP7_2_0 [3] */
  5032. FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
  5033. FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
  5034. },
  5035. { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
  5036. GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
  5037. GROUP(
  5038. /* IP8_31_29 [3] */
  5039. FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
  5040. 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
  5041. /* IP8_28_26 [3] */
  5042. FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
  5043. 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
  5044. /* IP8_25_23 [3] */
  5045. FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
  5046. 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
  5047. /* IP8_22_20 [3] */
  5048. FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
  5049. FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
  5050. /* IP8_19_17 [3] */
  5051. FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
  5052. FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
  5053. /* IP8_16_15 [2] */
  5054. FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
  5055. /* IP8_14_12 [3] */
  5056. FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
  5057. FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
  5058. /* IP8_11_9 [3] */
  5059. FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
  5060. FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
  5061. /* IP8_8_6 [3] */
  5062. FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
  5063. FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
  5064. /* IP8_5_3 [3] */
  5065. FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
  5066. FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
  5067. /* IP8_2_0 [3] */
  5068. FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
  5069. FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
  5070. },
  5071. { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
  5072. GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
  5073. GROUP(
  5074. /* IP9_31 [1] */
  5075. 0, 0,
  5076. /* IP9_30_28 [3] */
  5077. FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
  5078. FN_SSI_SDATA1_B, 0, 0, 0,
  5079. /* IP9_27_25 [3] */
  5080. FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
  5081. FN_SSI_WS1_B, 0, 0, 0,
  5082. /* IP9_24_22 [3] */
  5083. FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
  5084. FN_SSI_SCK1_B, 0, 0, 0,
  5085. /* IP9_21_19 [3] */
  5086. FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
  5087. FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
  5088. /* IP9_18_17 [2] */
  5089. FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
  5090. /* IP9_16_15 [2] */
  5091. FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
  5092. /* IP9_14_12 [3] */
  5093. FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
  5094. 0, FN_FMIN_B, 0, 0,
  5095. /* IP9_11_9 [3] */
  5096. FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
  5097. 0, FN_FMCLK_B, 0, 0,
  5098. /* IP9_8_6 [3] */
  5099. FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
  5100. 0, FN_BPFCLK_B, 0, 0,
  5101. /* IP9_5_3 [3] */
  5102. FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
  5103. 0, FN_TPUTO1_C, 0, 0,
  5104. /* IP9_2_0 [3] */
  5105. FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
  5106. 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
  5107. },
  5108. { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
  5109. GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  5110. GROUP(
  5111. /* IP10_31_30 [2] */
  5112. FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
  5113. /* IP10_29_27 [3] */
  5114. FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
  5115. 0, 0, 0, 0,
  5116. /* IP10_26_24 [3] */
  5117. FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
  5118. FN_SSI_SDATA4_B, 0, 0, 0,
  5119. /* IP10_23_21 [3] */
  5120. FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
  5121. FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
  5122. /* IP10_20_18 [3] */
  5123. FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
  5124. FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
  5125. /* IP10_17_15 [3] */
  5126. FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
  5127. FN_SSI_SDATA9_B, 0, 0, 0,
  5128. /* IP10_14_12 [3] */
  5129. FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
  5130. 0, 0, 0, 0,
  5131. /* IP10_11_9 [3] */
  5132. FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
  5133. 0, 0, 0, 0,
  5134. /* IP10_8_6 [3] */
  5135. FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
  5136. 0, 0, 0, 0,
  5137. /* IP10_5_3 [3] */
  5138. FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
  5139. 0, 0, 0, 0,
  5140. /* IP10_2_0 [3] */
  5141. FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
  5142. 0, 0, 0, 0, ))
  5143. },
  5144. { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
  5145. GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
  5146. GROUP(
  5147. /* IP11_31_30 [2] */
  5148. 0, 0, 0, 0,
  5149. /* IP11_29_27 [3] */
  5150. FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
  5151. 0, 0, 0, 0,
  5152. /* IP11_26_24 [3] */
  5153. FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
  5154. 0, 0, 0, 0,
  5155. /* IP11_23_21 [3] */
  5156. FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
  5157. 0, 0, 0, 0,
  5158. /* IP11_20_18 [3] */
  5159. FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
  5160. FN_CAN_CLK_D, 0, 0, 0,
  5161. /* IP11_17_16 [2] */
  5162. FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
  5163. /* IP11_15_14 [2] */
  5164. FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
  5165. /* IP11_13_11 [3] */
  5166. FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
  5167. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
  5168. /* IP11_10_8 [3] */
  5169. FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
  5170. FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
  5171. /* IP11_7_6 [2] */
  5172. FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
  5173. /* IP11_5_3 [3] */
  5174. FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
  5175. 0, 0, 0, 0,
  5176. /* IP11_2_0 [3] */
  5177. FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
  5178. 0, 0, 0, 0, ))
  5179. },
  5180. { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
  5181. GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
  5182. GROUP(
  5183. /* IP12_31_30 [2] */
  5184. 0, 0, 0, 0,
  5185. /* IP12_29_27 [3] */
  5186. FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
  5187. FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
  5188. /* IP12_26_24 [3] */
  5189. FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
  5190. FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
  5191. /* IP12_23_21 [3] */
  5192. FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
  5193. FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
  5194. /* IP12_20_18 [3] */
  5195. FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
  5196. FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
  5197. /* IP12_17_15 [3] */
  5198. FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
  5199. FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
  5200. /* IP12_14_13 [2] */
  5201. FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
  5202. /* IP12_12_11 [2] */
  5203. FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
  5204. /* IP12_10_9 [2] */
  5205. FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
  5206. /* IP12_8_6 [3] */
  5207. FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
  5208. FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
  5209. /* IP12_5_3 [3] */
  5210. FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
  5211. FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
  5212. /* IP12_2_0 [3] */
  5213. FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
  5214. 0, FN_DREQ1_N_B, 0, 0, ))
  5215. },
  5216. { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
  5217. GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  5218. GROUP(
  5219. /* IP13_31 [1] */
  5220. 0, 0,
  5221. /* IP13_30 [1] */
  5222. 0, 0,
  5223. /* IP13_29 [1] */
  5224. 0, 0,
  5225. /* IP13_28 [1] */
  5226. 0, 0,
  5227. /* IP13_27 [1] */
  5228. 0, 0,
  5229. /* IP13_26_24 [3] */
  5230. FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
  5231. FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
  5232. /* IP13_23_21 [3] */
  5233. FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
  5234. FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
  5235. /* IP13_20_18 [3] */
  5236. FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
  5237. FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
  5238. /* IP13_17_15 [3] */
  5239. FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
  5240. FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
  5241. /* IP13_14_12 [3] */
  5242. FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
  5243. FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
  5244. /* IP13_11_9 [3] */
  5245. FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
  5246. FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
  5247. /* IP13_8_6 [3] */
  5248. FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
  5249. 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
  5250. /* IP13_5_3 [2] */
  5251. FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
  5252. FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
  5253. /* IP13_2_0 [3] */
  5254. FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
  5255. 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
  5256. },
  5257. { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
  5258. GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
  5259. GROUP(
  5260. /* SEL_ADG [2] */
  5261. FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
  5262. /* RESERVED [1] */
  5263. 0, 0,
  5264. /* SEL_CAN [2] */
  5265. FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
  5266. /* SEL_DARC [3] */
  5267. FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
  5268. FN_SEL_DARC_4, 0, 0, 0,
  5269. /* RESERVED [4] */
  5270. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5271. /* SEL_ETH [1] */
  5272. FN_SEL_ETH_0, FN_SEL_ETH_1,
  5273. /* RESERVED [1] */
  5274. 0, 0,
  5275. /* SEL_IC200 [3] */
  5276. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
  5277. FN_SEL_I2C00_4, 0, 0, 0,
  5278. /* SEL_I2C01 [3] */
  5279. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
  5280. FN_SEL_I2C01_4, 0, 0, 0,
  5281. /* SEL_I2C02 [3] */
  5282. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  5283. FN_SEL_I2C02_4, 0, 0, 0,
  5284. /* SEL_I2C03 [3] */
  5285. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  5286. FN_SEL_I2C03_4, 0, 0, 0,
  5287. /* SEL_I2C04 [3] */
  5288. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
  5289. FN_SEL_I2C04_4, 0, 0, 0,
  5290. /* SEL_I2C05 [2] */
  5291. FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
  5292. /* RESERVED [1] */
  5293. 0, 0, ))
  5294. },
  5295. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
  5296. GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
  5297. 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
  5298. GROUP(
  5299. /* SEL_IEB [2] */
  5300. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
  5301. /* SEL_IIC0 [2] */
  5302. FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
  5303. /* SEL_LBS [1] */
  5304. FN_SEL_LBS_0, FN_SEL_LBS_1,
  5305. /* SEL_MSI1 [1] */
  5306. FN_SEL_MSI1_0, FN_SEL_MSI1_1,
  5307. /* SEL_MSI2 [1] */
  5308. FN_SEL_MSI2_0, FN_SEL_MSI2_1,
  5309. /* SEL_RAD [1] */
  5310. FN_SEL_RAD_0, FN_SEL_RAD_1,
  5311. /* SEL_RCN [1] */
  5312. FN_SEL_RCN_0, FN_SEL_RCN_1,
  5313. /* SEL_RSP [1] */
  5314. FN_SEL_RSP_0, FN_SEL_RSP_1,
  5315. /* SEL_SCIFA0 [2] */
  5316. FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
  5317. FN_SEL_SCIFA0_3,
  5318. /* SEL_SCIFA1 [2] */
  5319. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
  5320. /* SEL_SCIFA2 [1] */
  5321. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
  5322. /* SEL_SCIFA3 [1] */
  5323. FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
  5324. /* SEL_SCIFA4 [2] */
  5325. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
  5326. FN_SEL_SCIFA4_3,
  5327. /* SEL_SCIFA5 [2] */
  5328. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
  5329. FN_SEL_SCIFA5_3,
  5330. /* RESERVED [1] */
  5331. 0, 0,
  5332. /* SEL_TMU [1] */
  5333. FN_SEL_TMU_0, FN_SEL_TMU_1,
  5334. /* SEL_TSIF0 [2] */
  5335. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  5336. /* SEL_CAN0 [2] */
  5337. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  5338. /* SEL_CAN1 [2] */
  5339. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  5340. /* SEL_HSCIF0 [1] */
  5341. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
  5342. /* SEL_HSCIF1 [1] */
  5343. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  5344. /* RESERVED [2] */
  5345. 0, 0, 0, 0, ))
  5346. },
  5347. { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
  5348. GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
  5349. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
  5350. GROUP(
  5351. /* SEL_SCIF0 [2] */
  5352. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  5353. /* SEL_SCIF1 [2] */
  5354. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
  5355. /* SEL_SCIF2 [2] */
  5356. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
  5357. /* SEL_SCIF3 [1] */
  5358. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
  5359. /* SEL_SCIF4 [3] */
  5360. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  5361. FN_SEL_SCIF4_4, 0, 0, 0,
  5362. /* SEL_SCIF5 [2] */
  5363. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
  5364. /* SEL_SSI1 [1] */
  5365. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  5366. /* SEL_SSI2 [1] */
  5367. FN_SEL_SSI2_0, FN_SEL_SSI2_1,
  5368. /* SEL_SSI4 [1] */
  5369. FN_SEL_SSI4_0, FN_SEL_SSI4_1,
  5370. /* SEL_SSI5 [1] */
  5371. FN_SEL_SSI5_0, FN_SEL_SSI5_1,
  5372. /* SEL_SSI6 [1] */
  5373. FN_SEL_SSI6_0, FN_SEL_SSI6_1,
  5374. /* SEL_SSI7 [1] */
  5375. FN_SEL_SSI7_0, FN_SEL_SSI7_1,
  5376. /* SEL_SSI8 [1] */
  5377. FN_SEL_SSI8_0, FN_SEL_SSI8_1,
  5378. /* SEL_SSI9 [1] */
  5379. FN_SEL_SSI9_0, FN_SEL_SSI9_1,
  5380. /* RESERVED [1] */
  5381. 0, 0,
  5382. /* RESERVED [1] */
  5383. 0, 0,
  5384. /* RESERVED [1] */
  5385. 0, 0,
  5386. /* RESERVED [1] */
  5387. 0, 0,
  5388. /* RESERVED [1] */
  5389. 0, 0,
  5390. /* RESERVED [1] */
  5391. 0, 0,
  5392. /* RESERVED [1] */
  5393. 0, 0,
  5394. /* RESERVED [1] */
  5395. 0, 0,
  5396. /* RESERVED [1] */
  5397. 0, 0,
  5398. /* RESERVED [1] */
  5399. 0, 0,
  5400. /* RESERVED [1] */
  5401. 0, 0,
  5402. /* RESERVED [1] */
  5403. 0, 0, ))
  5404. },
  5405. { },
  5406. };
  5407. static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
  5408. {
  5409. *pocctrl = 0xe606006c;
  5410. switch (pin & 0x1f) {
  5411. case 6: return 23;
  5412. case 7: return 16;
  5413. case 14: return 15;
  5414. case 15: return 8;
  5415. case 0 ... 5:
  5416. case 8 ... 13:
  5417. return 22 - (pin & 0x1f);
  5418. case 16 ... 23:
  5419. return 47 - (pin & 0x1f);
  5420. }
  5421. return -EINVAL;
  5422. }
  5423. static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
  5424. {
  5425. /* Initialize TDSEL on old revisions */
  5426. if ((rmobile_get_cpu_rev_integer() == 1) &&
  5427. (rmobile_get_cpu_rev_fraction() == 0))
  5428. sh_pfc_write(pfc, 0xe6060068, 0x55555500);
  5429. return 0;
  5430. }
  5431. static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
  5432. .init = r8a7794_pinmux_soc_init,
  5433. .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
  5434. };
  5435. #ifdef CONFIG_PINCTRL_PFC_R8A7745
  5436. const struct sh_pfc_soc_info r8a7745_pinmux_info = {
  5437. .name = "r8a77450_pfc",
  5438. .ops = &r8a7794_pinmux_ops,
  5439. .unlock_reg = 0xe6060000, /* PMMR */
  5440. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5441. .pins = pinmux_pins,
  5442. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5443. .groups = pinmux_groups,
  5444. .nr_groups = ARRAY_SIZE(pinmux_groups),
  5445. .functions = pinmux_functions,
  5446. .nr_functions = ARRAY_SIZE(pinmux_functions),
  5447. .cfg_regs = pinmux_config_regs,
  5448. .pinmux_data = pinmux_data,
  5449. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5450. };
  5451. #endif
  5452. #ifdef CONFIG_PINCTRL_PFC_R8A7794
  5453. const struct sh_pfc_soc_info r8a7794_pinmux_info = {
  5454. .name = "r8a77940_pfc",
  5455. .ops = &r8a7794_pinmux_ops,
  5456. .unlock_reg = 0xe6060000, /* PMMR */
  5457. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5458. .pins = pinmux_pins,
  5459. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5460. .groups = pinmux_groups,
  5461. .nr_groups = ARRAY_SIZE(pinmux_groups),
  5462. .functions = pinmux_functions,
  5463. .nr_functions = ARRAY_SIZE(pinmux_functions),
  5464. .cfg_regs = pinmux_config_regs,
  5465. .pinmux_data = pinmux_data,
  5466. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5467. };
  5468. #endif