pinctrl-single.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
  4. * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dm/device_compat.h>
  9. #include <dm/devres.h>
  10. #include <dm/pinctrl.h>
  11. #include <linux/libfdt.h>
  12. #include <linux/list.h>
  13. #include <asm/io.h>
  14. #include <sort.h>
  15. /**
  16. * struct single_pdata - platform data
  17. * @base: first configuration register
  18. * @offset: index of last configuration register
  19. * @mask: configuration-value mask bits
  20. * @width: configuration register bit width
  21. * @bits_per_mux: true if one register controls more than one pin
  22. */
  23. struct single_pdata {
  24. fdt_addr_t base;
  25. int offset;
  26. u32 mask;
  27. u32 width;
  28. bool bits_per_mux;
  29. };
  30. /**
  31. * struct single_func - pinctrl function
  32. * @node: list node
  33. * @name: pinctrl function name
  34. * @npins: number of entries in pins array
  35. * @pins: pins array
  36. */
  37. struct single_func {
  38. struct list_head node;
  39. const char *name;
  40. unsigned int npins;
  41. unsigned int *pins;
  42. };
  43. /**
  44. * struct single_priv - private data
  45. * @bits_per_pin: number of bits per pin
  46. * @npins: number of selectable pins
  47. * @pin_name: temporary buffer to store the pin name
  48. */
  49. struct single_priv {
  50. #if (IS_ENABLED(CONFIG_SANDBOX))
  51. u32 *sandbox_regs;
  52. #endif
  53. unsigned int bits_per_pin;
  54. unsigned int npins;
  55. char pin_name[PINNAME_SIZE];
  56. struct list_head functions;
  57. };
  58. /**
  59. * struct single_fdt_pin_cfg - pin configuration
  60. *
  61. * This structure is used for the pin configuration parameters in case
  62. * the register controls only one pin.
  63. *
  64. * @reg: configuration register offset
  65. * @val: configuration register value
  66. */
  67. struct single_fdt_pin_cfg {
  68. fdt32_t reg;
  69. fdt32_t val;
  70. };
  71. /**
  72. * struct single_fdt_bits_cfg - pin configuration
  73. *
  74. * This structure is used for the pin configuration parameters in case
  75. * the register controls more than one pin.
  76. *
  77. * @reg: configuration register offset
  78. * @val: configuration register value
  79. * @mask: configuration register mask
  80. */
  81. struct single_fdt_bits_cfg {
  82. fdt32_t reg;
  83. fdt32_t val;
  84. fdt32_t mask;
  85. };
  86. #if (!IS_ENABLED(CONFIG_SANDBOX))
  87. static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
  88. {
  89. struct single_pdata *pdata = dev_get_plat(dev);
  90. switch (pdata->width) {
  91. case 8:
  92. return readb(reg);
  93. case 16:
  94. return readw(reg);
  95. default: /* 32 bits */
  96. return readl(reg);
  97. }
  98. return readb(reg);
  99. }
  100. static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
  101. {
  102. struct single_pdata *pdata = dev_get_plat(dev);
  103. switch (pdata->width) {
  104. case 8:
  105. writeb(val, reg);
  106. break;
  107. case 16:
  108. writew(val, reg);
  109. break;
  110. default: /* 32 bits */
  111. writel(val, reg);
  112. }
  113. }
  114. #else /* CONFIG_SANDBOX */
  115. static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
  116. {
  117. struct single_priv *priv = dev_get_priv(dev);
  118. return priv->sandbox_regs[reg];
  119. }
  120. static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
  121. {
  122. struct single_priv *priv = dev_get_priv(dev);
  123. priv->sandbox_regs[reg] = val;
  124. }
  125. #endif /* CONFIG_SANDBOX */
  126. /**
  127. * single_get_pin_by_offset() - get a pin based on the register offset
  128. * @dev: single driver instance
  129. * @offset: register offset from the base
  130. */
  131. static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset)
  132. {
  133. struct single_pdata *pdata = dev_get_plat(dev);
  134. struct single_priv *priv = dev_get_priv(dev);
  135. if (offset > pdata->offset) {
  136. dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n",
  137. offset, pdata->offset);
  138. return -EINVAL;
  139. }
  140. if (pdata->bits_per_mux)
  141. return (offset * BITS_PER_BYTE) / priv->bits_per_pin;
  142. return offset / (pdata->width / BITS_PER_BYTE);
  143. }
  144. static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin)
  145. {
  146. struct single_pdata *pdata = dev_get_plat(dev);
  147. struct single_priv *priv = dev_get_priv(dev);
  148. unsigned int mux_bytes;
  149. if (pin >= priv->npins)
  150. return -EINVAL;
  151. mux_bytes = pdata->width / BITS_PER_BYTE;
  152. if (pdata->bits_per_mux) {
  153. int byte_num;
  154. byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE;
  155. return (byte_num / mux_bytes) * mux_bytes;
  156. }
  157. return pin * mux_bytes;
  158. }
  159. static const char *single_get_pin_function(struct udevice *dev,
  160. unsigned int pin)
  161. {
  162. struct single_priv *priv = dev_get_priv(dev);
  163. struct single_func *func;
  164. int i;
  165. list_for_each_entry(func, &priv->functions, node) {
  166. for (i = 0; i < func->npins; i++) {
  167. if (pin == func->pins[i])
  168. return func->name;
  169. if (pin < func->pins[i])
  170. break;
  171. }
  172. }
  173. return NULL;
  174. }
  175. static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
  176. char *buf, int size)
  177. {
  178. struct single_pdata *pdata = dev_get_plat(dev);
  179. struct single_priv *priv = dev_get_priv(dev);
  180. fdt_addr_t reg;
  181. const char *fname;
  182. unsigned int val;
  183. int offset, pin_shift = 0;
  184. offset = single_get_offset_by_pin(dev, pin);
  185. if (offset < 0)
  186. return offset;
  187. reg = pdata->base + offset;
  188. val = single_read(dev, reg);
  189. if (pdata->bits_per_mux)
  190. pin_shift = pin % (pdata->width / priv->bits_per_pin) *
  191. priv->bits_per_pin;
  192. val &= (pdata->mask << pin_shift);
  193. fname = single_get_pin_function(dev, pin);
  194. snprintf(buf, size, "%pa 0x%08x %s", &reg, val,
  195. fname ? fname : "UNCLAIMED");
  196. return 0;
  197. }
  198. static struct single_func *single_allocate_function(struct udevice *dev,
  199. unsigned int group_pins)
  200. {
  201. struct single_func *func;
  202. func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL);
  203. if (!func)
  204. return ERR_PTR(-ENOMEM);
  205. func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins,
  206. GFP_KERNEL);
  207. if (!func->pins)
  208. return ERR_PTR(-ENOMEM);
  209. return func;
  210. }
  211. static int single_pin_compare(const void *s1, const void *s2)
  212. {
  213. int pin1 = *(const unsigned int *)s1;
  214. int pin2 = *(const unsigned int *)s2;
  215. return pin1 - pin2;
  216. }
  217. /**
  218. * single_configure_pins() - Configure pins based on FDT data
  219. *
  220. * @dev: Pointer to single pin configuration device which is the parent of
  221. * the pins node holding the pin configuration data.
  222. * @pins: Pointer to the first element of an array of register/value pairs
  223. * of type 'struct single_fdt_pin_cfg'. Each such pair describes the
  224. * the pin to be configured and the value to be used for configuration.
  225. * This pointer points to a 'pinctrl-single,pins' property in the
  226. * device-tree.
  227. * @size: Size of the 'pins' array in bytes.
  228. * The number of register/value pairs in the 'pins' array therefore
  229. * equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
  230. * @fname: Function name.
  231. */
  232. static int single_configure_pins(struct udevice *dev,
  233. const struct single_fdt_pin_cfg *pins,
  234. int size, const char *fname)
  235. {
  236. struct single_pdata *pdata = dev_get_plat(dev);
  237. struct single_priv *priv = dev_get_priv(dev);
  238. int n, pin, count = size / sizeof(struct single_fdt_pin_cfg);
  239. struct single_func *func;
  240. phys_addr_t reg;
  241. u32 offset, val;
  242. /* If function mask is null, needn't enable it. */
  243. if (!pdata->mask)
  244. return 0;
  245. func = single_allocate_function(dev, count);
  246. if (IS_ERR(func))
  247. return PTR_ERR(func);
  248. func->name = fname;
  249. func->npins = 0;
  250. for (n = 0; n < count; n++, pins++) {
  251. offset = fdt32_to_cpu(pins->reg);
  252. if (offset > pdata->offset) {
  253. dev_err(dev, " invalid register offset 0x%x\n",
  254. offset);
  255. continue;
  256. }
  257. reg = pdata->base + offset;
  258. val = fdt32_to_cpu(pins->val) & pdata->mask;
  259. pin = single_get_pin_by_offset(dev, offset);
  260. if (pin < 0) {
  261. dev_err(dev, " failed to get pin by offset %x\n",
  262. offset);
  263. continue;
  264. }
  265. single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val,
  266. reg);
  267. dev_dbg(dev, " reg/val %pa/0x%08x\n", &reg, val);
  268. func->pins[func->npins] = pin;
  269. func->npins++;
  270. }
  271. qsort(func->pins, func->npins, sizeof(func->pins[0]),
  272. single_pin_compare);
  273. list_add(&func->node, &priv->functions);
  274. return 0;
  275. }
  276. static int single_configure_bits(struct udevice *dev,
  277. const struct single_fdt_bits_cfg *pins,
  278. int size, const char *fname)
  279. {
  280. struct single_pdata *pdata = dev_get_plat(dev);
  281. struct single_priv *priv = dev_get_priv(dev);
  282. int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
  283. int npins_in_reg, pin_num_from_lsb;
  284. struct single_func *func;
  285. phys_addr_t reg;
  286. u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
  287. /* If function mask is null, needn't enable it. */
  288. if (!pdata->mask)
  289. return 0;
  290. npins_in_reg = pdata->width / priv->bits_per_pin;
  291. func = single_allocate_function(dev, count * npins_in_reg);
  292. if (IS_ERR(func))
  293. return PTR_ERR(func);
  294. func->name = fname;
  295. func->npins = 0;
  296. for (n = 0; n < count; n++, pins++) {
  297. offset = fdt32_to_cpu(pins->reg);
  298. if (offset > pdata->offset) {
  299. dev_dbg(dev, " invalid register offset 0x%x\n",
  300. offset);
  301. continue;
  302. }
  303. reg = pdata->base + offset;
  304. pin = single_get_pin_by_offset(dev, offset);
  305. if (pin < 0) {
  306. dev_err(dev, " failed to get pin by offset 0x%pa\n",
  307. &reg);
  308. continue;
  309. }
  310. mask = fdt32_to_cpu(pins->mask);
  311. val = fdt32_to_cpu(pins->val) & mask;
  312. single_write(dev, (single_read(dev, reg) & ~mask) | val, reg);
  313. dev_dbg(dev, " reg/val %pa/0x%08x\n", &reg, val);
  314. while (mask) {
  315. bit_pos = __ffs(mask);
  316. pin_num_from_lsb = bit_pos / priv->bits_per_pin;
  317. mask_pos = pdata->mask << bit_pos;
  318. val_pos = val & mask_pos;
  319. submask = mask & mask_pos;
  320. if ((mask & mask_pos) == 0) {
  321. dev_err(dev, "Invalid mask at 0x%x\n", offset);
  322. break;
  323. }
  324. mask &= ~mask_pos;
  325. if (submask != mask_pos) {
  326. dev_warn(dev,
  327. "Invalid submask 0x%x at 0x%x\n",
  328. submask, offset);
  329. continue;
  330. }
  331. func->pins[func->npins] = pin + pin_num_from_lsb;
  332. func->npins++;
  333. }
  334. }
  335. qsort(func->pins, func->npins, sizeof(func->pins[0]),
  336. single_pin_compare);
  337. list_add(&func->node, &priv->functions);
  338. return 0;
  339. }
  340. static int single_set_state(struct udevice *dev,
  341. struct udevice *config)
  342. {
  343. const struct single_fdt_pin_cfg *prop;
  344. const struct single_fdt_bits_cfg *prop_bits;
  345. int len;
  346. prop = dev_read_prop(config, "pinctrl-single,pins", &len);
  347. if (prop) {
  348. dev_dbg(dev, "configuring pins for %s\n", config->name);
  349. if (len % sizeof(struct single_fdt_pin_cfg)) {
  350. dev_dbg(dev, " invalid pin configuration in fdt\n");
  351. return -FDT_ERR_BADSTRUCTURE;
  352. }
  353. single_configure_pins(dev, prop, len, config->name);
  354. return 0;
  355. }
  356. /* pinctrl-single,pins not found so check for pinctrl-single,bits */
  357. prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len);
  358. if (prop_bits) {
  359. dev_dbg(dev, "configuring pins for %s\n", config->name);
  360. if (len % sizeof(struct single_fdt_bits_cfg)) {
  361. dev_dbg(dev, " invalid bits configuration in fdt\n");
  362. return -FDT_ERR_BADSTRUCTURE;
  363. }
  364. single_configure_bits(dev, prop_bits, len, config->name);
  365. return 0;
  366. }
  367. /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
  368. return len;
  369. }
  370. static const char *single_get_pin_name(struct udevice *dev,
  371. unsigned int selector)
  372. {
  373. struct single_priv *priv = dev_get_priv(dev);
  374. if (selector >= priv->npins)
  375. snprintf(priv->pin_name, PINNAME_SIZE, "Error");
  376. else
  377. snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector);
  378. return priv->pin_name;
  379. }
  380. static int single_get_pins_count(struct udevice *dev)
  381. {
  382. struct single_priv *priv = dev_get_priv(dev);
  383. return priv->npins;
  384. }
  385. static int single_probe(struct udevice *dev)
  386. {
  387. struct single_pdata *pdata = dev_get_plat(dev);
  388. struct single_priv *priv = dev_get_priv(dev);
  389. u32 size;
  390. INIT_LIST_HEAD(&priv->functions);
  391. size = pdata->offset + pdata->width / BITS_PER_BYTE;
  392. #if (CONFIG_IS_ENABLED(SANDBOX))
  393. priv->sandbox_regs =
  394. devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs),
  395. GFP_KERNEL);
  396. if (!priv->sandbox_regs)
  397. return -ENOMEM;
  398. #endif
  399. /* looks like a possible divide by 0, but data->width avoids this */
  400. priv->npins = size / (pdata->width / BITS_PER_BYTE);
  401. if (pdata->bits_per_mux) {
  402. if (!pdata->mask) {
  403. dev_err(dev, "function mask needs to be non-zero\n");
  404. return -EINVAL;
  405. }
  406. priv->bits_per_pin = fls(pdata->mask);
  407. priv->npins *= (pdata->width / priv->bits_per_pin);
  408. }
  409. dev_dbg(dev, "%d pins\n", priv->npins);
  410. return 0;
  411. }
  412. static int single_of_to_plat(struct udevice *dev)
  413. {
  414. fdt_addr_t addr;
  415. fdt_size_t size;
  416. struct single_pdata *pdata = dev_get_plat(dev);
  417. int ret;
  418. ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width);
  419. if (ret) {
  420. dev_err(dev, "missing register width\n");
  421. return ret;
  422. }
  423. switch (pdata->width) {
  424. case 8:
  425. case 16:
  426. case 32:
  427. break;
  428. default:
  429. dev_err(dev, "wrong register width\n");
  430. return -EINVAL;
  431. }
  432. addr = dev_read_addr_size_index(dev, 0, &size);
  433. if (addr == FDT_ADDR_T_NONE) {
  434. dev_err(dev, "failed to get base register address\n");
  435. return -EINVAL;
  436. }
  437. pdata->offset = size - pdata->width / BITS_PER_BYTE;
  438. pdata->base = addr;
  439. ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask);
  440. if (ret) {
  441. pdata->mask = 0;
  442. dev_warn(dev, "missing function register mask\n");
  443. }
  444. pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
  445. return 0;
  446. }
  447. const struct pinctrl_ops single_pinctrl_ops = {
  448. .get_pins_count = single_get_pins_count,
  449. .get_pin_name = single_get_pin_name,
  450. .set_state = single_set_state,
  451. .get_pin_muxing = single_get_pin_muxing,
  452. };
  453. static const struct udevice_id single_pinctrl_match[] = {
  454. { .compatible = "pinctrl-single" },
  455. { /* sentinel */ }
  456. };
  457. U_BOOT_DRIVER(single_pinctrl) = {
  458. .name = "single-pinctrl",
  459. .id = UCLASS_PINCTRL,
  460. .of_match = single_pinctrl_match,
  461. .ops = &single_pinctrl_ops,
  462. .plat_auto = sizeof(struct single_pdata),
  463. .priv_auto = sizeof(struct single_priv),
  464. .of_to_plat = single_of_to_plat,
  465. .probe = single_probe,
  466. };