pinctrl-qe-io.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #include <common.h>
  9. #include <linux/errno.h>
  10. #include <asm/io.h>
  11. #include <asm/immap_83xx.h>
  12. #if defined(CONFIG_PINCTRL)
  13. #include <dm.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/pinctrl.h>
  16. #include <linux/ioport.h>
  17. /**
  18. * struct qe_io_plat
  19. *
  20. * @base: Base register address
  21. * @num_par_io_ports number of io ports
  22. */
  23. struct qe_io_plat {
  24. qepio83xx_t *base;
  25. u32 num_io_ports;
  26. };
  27. #endif
  28. #define NUM_OF_PINS 32
  29. /** qe_cfg_iopin configure one io pin setting
  30. *
  31. * @par_io: pointer to parallel I/O base
  32. * @port: io pin port
  33. * @pin: io pin number which get configured
  34. * @dir: direction of io pin 2 bits valid
  35. * 00 = pin disabled
  36. * 01 = output
  37. * 10 = input
  38. * 11 = pin is I/O
  39. * @open_drain: is pin open drain
  40. * @assign: pin assignment registers select the function of the pin
  41. */
  42. static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
  43. int open_drain, int assign)
  44. {
  45. u32 dbit_mask;
  46. u32 dbit_dir;
  47. u32 dbit_asgn;
  48. u32 bit_mask;
  49. u32 tmp_val;
  50. int offset;
  51. offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
  52. /* Calculate pin location and 2bit mask and dir */
  53. dbit_mask = (u32)(0x3 << offset);
  54. dbit_dir = (u32)(dir << offset);
  55. /* Setup the direction */
  56. tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
  57. in_be32(&par_io->ioport[port].dir2) :
  58. in_be32(&par_io->ioport[port].dir1);
  59. if (pin > (NUM_OF_PINS / 2) - 1) {
  60. out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
  61. out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
  62. } else {
  63. out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
  64. out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
  65. }
  66. /* Calculate pin location for 1bit mask */
  67. bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
  68. /* Setup the open drain */
  69. tmp_val = in_be32(&par_io->ioport[port].podr);
  70. if (open_drain)
  71. out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
  72. else
  73. out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
  74. /* Setup the assignment */
  75. tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
  76. in_be32(&par_io->ioport[port].ppar2) :
  77. in_be32(&par_io->ioport[port].ppar1);
  78. dbit_asgn = (u32)(assign << offset);
  79. /* Clear and set 2 bits mask */
  80. if (pin > (NUM_OF_PINS / 2) - 1) {
  81. out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
  82. out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
  83. } else {
  84. out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
  85. out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
  86. }
  87. }
  88. #if !defined(CONFIG_PINCTRL)
  89. /** qe_config_iopin configure one io pin setting
  90. *
  91. * @port: io pin port
  92. * @pin: io pin number which get configured
  93. * @dir: direction of io pin 2 bits valid
  94. * 00 = pin disabled
  95. * 01 = output
  96. * 10 = input
  97. * 11 = pin is I/O
  98. * @open_drain: is pin open drain
  99. * @assign: pin assignment registers select the function of the pin
  100. */
  101. void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
  102. {
  103. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  104. qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
  105. qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
  106. }
  107. #else
  108. static int qe_io_of_to_plat(struct udevice *dev)
  109. {
  110. struct qe_io_plat *plat = dev_get_plat(dev);
  111. fdt_addr_t addr;
  112. addr = dev_read_addr(dev);
  113. if (addr == FDT_ADDR_T_NONE)
  114. return -EINVAL;
  115. plat->base = (qepio83xx_t *)addr;
  116. if (dev_read_u32(dev, "num-ports", &plat->num_io_ports))
  117. return -EINVAL;
  118. return 0;
  119. }
  120. /**
  121. * par_io_of_config_node config
  122. * @dev: pointer to pinctrl device
  123. * @pio: ofnode of pinconfig property
  124. */
  125. static int par_io_of_config_node(struct udevice *dev, ofnode pio)
  126. {
  127. struct qe_io_plat *plat = dev_get_plat(dev);
  128. qepio83xx_t *par_io = plat->base;
  129. const unsigned int *pio_map;
  130. int pio_map_len;
  131. pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len);
  132. if (!pio_map)
  133. return -ENOENT;
  134. pio_map_len /= sizeof(unsigned int);
  135. if ((pio_map_len % 6) != 0) {
  136. dev_err(dev, "%s: pio-map format wrong!\n", __func__);
  137. return -EINVAL;
  138. }
  139. while (pio_map_len > 0) {
  140. /*
  141. * column pio_map[5] from linux (has_irq) not
  142. * supported in u-boot yet.
  143. */
  144. qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1],
  145. (int)pio_map[2], (int)pio_map[3],
  146. (int)pio_map[4]);
  147. pio_map += 6;
  148. pio_map_len -= 6;
  149. }
  150. return 0;
  151. }
  152. int par_io_of_config(struct udevice *dev)
  153. {
  154. u32 phandle;
  155. ofnode pio;
  156. int err;
  157. err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle);
  158. if (err) {
  159. dev_err(dev, "%s: pio-handle not available\n", __func__);
  160. return err;
  161. }
  162. pio = ofnode_get_by_phandle(phandle);
  163. if (!ofnode_valid(pio)) {
  164. dev_err(dev, "%s: unable to find node\n", __func__);
  165. return -EINVAL;
  166. }
  167. /* To Do: find pinctrl device and pass it */
  168. return par_io_of_config_node(NULL, pio);
  169. }
  170. /*
  171. * This is not nice!
  172. * pinsettings should work with "pinctrl-" properties.
  173. * Unfortunately on mpc83xx powerpc linux device trees
  174. * devices handle this with "pio-handle" properties ...
  175. *
  176. * Even worser, old board code inits all par_io
  177. * pins in one step, if U-Boot uses the device
  178. * or not. So init all par_io definitions here too
  179. * as linux does this also.
  180. */
  181. static void config_qe_ioports(struct udevice *dev)
  182. {
  183. ofnode ofn;
  184. for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn);
  185. ofn = dev_read_next_subnode(ofn)) {
  186. /*
  187. * ignore errors here, as may the subnode
  188. * has no pio-handle
  189. */
  190. par_io_of_config_node(dev, ofn);
  191. }
  192. }
  193. static int par_io_pinctrl_probe(struct udevice *dev)
  194. {
  195. config_qe_ioports(dev);
  196. return 0;
  197. }
  198. static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  199. {
  200. return 0;
  201. }
  202. const struct pinctrl_ops par_io_pinctrl_ops = {
  203. .set_state = par_io_pinctrl_set_state,
  204. };
  205. static const struct udevice_id par_io_pinctrl_match[] = {
  206. { .compatible = "fsl,mpc8360-par_io"},
  207. { /* sentinel */ }
  208. };
  209. U_BOOT_DRIVER(par_io_pinctrl) = {
  210. .name = "par-io-pinctrl",
  211. .id = UCLASS_PINCTRL,
  212. .of_match = of_match_ptr(par_io_pinctrl_match),
  213. .probe = par_io_pinctrl_probe,
  214. .of_to_plat = qe_io_of_to_plat,
  215. .plat_auto = sizeof(struct qe_io_plat),
  216. .ops = &par_io_pinctrl_ops,
  217. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  218. .flags = DM_FLAG_PRE_RELOC,
  219. #endif
  220. };
  221. #endif