pinctrl-at91.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO pinctrl driver
  4. *
  5. * Copyright (C) 2016 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/global_data.h>
  12. #include <dm/pinctrl.h>
  13. #include <asm/hardware.h>
  14. #include <linux/bitops.h>
  15. #include <linux/io.h>
  16. #include <linux/err.h>
  17. #include <mach/at91_pio.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define MAX_GPIO_BANKS 5
  20. #define MAX_NB_GPIO_PER_BANK 32
  21. #define MAX_PINMUX_ENTRIES 200
  22. struct at91_pinctrl_priv {
  23. struct at91_port *reg_base[MAX_GPIO_BANKS];
  24. u32 nbanks;
  25. };
  26. #define PULL_UP BIT(0)
  27. #define MULTI_DRIVE BIT(1)
  28. #define DEGLITCH BIT(2)
  29. #define PULL_DOWN BIT(3)
  30. #define DIS_SCHMIT BIT(4)
  31. #define DRIVE_STRENGTH_SHIFT 5
  32. #define DRIVE_STRENGTH_MASK 0x3
  33. #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
  34. #define OUTPUT BIT(7)
  35. #define OUTPUT_VAL_SHIFT 8
  36. #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
  37. #define SLEWRATE_SHIFT 9
  38. #define SLEWRATE_MASK 0x1
  39. #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
  40. #define DEBOUNCE BIT(16)
  41. #define DEBOUNCE_VAL_SHIFT 17
  42. #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
  43. /**
  44. * These defines will translated the dt binding settings to our internal
  45. * settings. They are not necessarily the same value as the register setting.
  46. * The actual drive strength current of low, medium and high must be looked up
  47. * from the corresponding device datasheet. This value is different for pins
  48. * that are even in the same banks. It is also dependent on VCC.
  49. * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
  50. * strength when there is no dt config for it.
  51. */
  52. enum drive_strength_bit {
  53. DRIVE_STRENGTH_BIT_DEF,
  54. DRIVE_STRENGTH_BIT_LOW,
  55. DRIVE_STRENGTH_BIT_MED,
  56. DRIVE_STRENGTH_BIT_HI,
  57. };
  58. #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
  59. DRIVE_STRENGTH_SHIFT)
  60. enum slewrate_bit {
  61. SLEWRATE_BIT_DIS,
  62. SLEWRATE_BIT_ENA,
  63. };
  64. #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
  65. enum at91_mux {
  66. AT91_MUX_GPIO = 0,
  67. AT91_MUX_PERIPH_A = 1,
  68. AT91_MUX_PERIPH_B = 2,
  69. AT91_MUX_PERIPH_C = 3,
  70. AT91_MUX_PERIPH_D = 4,
  71. };
  72. /**
  73. * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
  74. * on new IP with support for periph C and D the way to mux in
  75. * periph A and B has changed
  76. * So provide the right callbacks
  77. * if not present means the IP does not support it
  78. * @mux_A_periph: assign the corresponding pin to the peripheral A function.
  79. * @mux_B_periph: assign the corresponding pin to the peripheral B function.
  80. * @mux_C_periph: assign the corresponding pin to the peripheral C function.
  81. * @mux_D_periph: assign the corresponding pin to the peripheral D function.
  82. * @set_deglitch: enable/disable the deglitch feature.
  83. * @set_debounce: enable/disable the debounce feature.
  84. * @set_pulldown: enable/disable the pulldown feature.
  85. * @disable_schmitt_trig: disable schmitt trigger
  86. */
  87. struct at91_pinctrl_mux_ops {
  88. void (*mux_A_periph)(struct at91_port *pio, u32 mask);
  89. void (*mux_B_periph)(struct at91_port *pio, u32 mask);
  90. void (*mux_C_periph)(struct at91_port *pio, u32 mask);
  91. void (*mux_D_periph)(struct at91_port *pio, u32 mask);
  92. void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
  93. void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
  94. u32 div);
  95. void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
  96. void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
  97. void (*set_drivestrength)(struct at91_port *pio, u32 pin,
  98. u32 strength);
  99. void (*set_slewrate)(struct at91_port *pio, u32 pin, u32 slewrate);
  100. };
  101. static u32 two_bit_pin_value_shift_amount(u32 pin)
  102. {
  103. /* return the shift value for a pin for "two bit" per pin registers,
  104. * i.e. drive strength */
  105. return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
  106. ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
  107. }
  108. static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
  109. {
  110. writel(mask, &pio->idr);
  111. }
  112. static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
  113. {
  114. if (on)
  115. writel(mask, &pio->mux.pio3.ppddr);
  116. writel(mask, (on ? &pio->puer : &pio->pudr));
  117. }
  118. static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
  119. bool is_on, bool val)
  120. {
  121. writel(mask, (val ? &pio->sodr : &pio->codr));
  122. writel(mask, (is_on ? &pio->oer : &pio->odr));
  123. }
  124. static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
  125. {
  126. writel(mask, (on ? &pio->mder : &pio->mddr));
  127. }
  128. static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
  129. {
  130. writel(mask, &pio->mux.pio2.asr);
  131. }
  132. static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
  133. {
  134. writel(mask, &pio->mux.pio2.bsr);
  135. }
  136. static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
  137. {
  138. writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
  139. writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
  140. }
  141. static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
  142. {
  143. writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
  144. writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
  145. }
  146. static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
  147. {
  148. writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
  149. writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
  150. }
  151. static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
  152. {
  153. writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
  154. writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
  155. }
  156. static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
  157. {
  158. writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
  159. }
  160. static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
  161. u32 mask, bool is_on)
  162. {
  163. if (is_on)
  164. writel(mask, &pio->mux.pio3.ifscdr);
  165. at91_mux_set_deglitch(pio, mask, is_on);
  166. }
  167. static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
  168. bool is_on, u32 div)
  169. {
  170. if (is_on) {
  171. writel(mask, &pio->mux.pio3.ifscer);
  172. writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
  173. writel(mask, &pio->ifer);
  174. } else {
  175. writel(mask, &pio->mux.pio3.ifscdr);
  176. }
  177. }
  178. static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
  179. u32 mask, bool is_on)
  180. {
  181. if (is_on)
  182. writel(mask, &pio->pudr);
  183. writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
  184. }
  185. static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
  186. u32 mask)
  187. {
  188. writel(readl(&pio->schmitt) | mask, &pio->schmitt);
  189. }
  190. static void set_drive_strength(void *reg, u32 pin, u32 strength)
  191. {
  192. u32 shift = two_bit_pin_value_shift_amount(pin);
  193. clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
  194. }
  195. static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
  196. u32 pin, u32 setting)
  197. {
  198. void *reg;
  199. reg = &pio->driver12;
  200. if (pin >= MAX_NB_GPIO_PER_BANK / 2)
  201. reg = &pio->driver2;
  202. /* do nothing if setting is zero */
  203. if (!setting)
  204. return;
  205. /* strength is 1 to 1 with setting for SAMA5 */
  206. set_drive_strength(reg, pin, setting);
  207. }
  208. static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
  209. u32 pin, u32 setting)
  210. {
  211. void *reg;
  212. reg = &pio->driver1;
  213. if (pin >= MAX_NB_GPIO_PER_BANK / 2)
  214. reg = &pio->driver12;
  215. /* do nothing if setting is zero */
  216. if (!setting)
  217. return;
  218. /* strength is inverse on SAM9x5s with our defines
  219. * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
  220. setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
  221. set_drive_strength(reg, pin, setting);
  222. }
  223. static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
  224. u32 setting)
  225. {
  226. void *reg = &pio->driver12;
  227. u32 tmp;
  228. if (setting <= DRIVE_STRENGTH_BIT_DEF ||
  229. setting == DRIVE_STRENGTH_BIT_MED ||
  230. setting > DRIVE_STRENGTH_BIT_HI)
  231. return;
  232. tmp = readl(reg);
  233. /* Strength is 0: low, 1: hi */
  234. if (setting == DRIVE_STRENGTH_BIT_LOW)
  235. tmp &= ~BIT(pin);
  236. else
  237. tmp |= BIT(pin);
  238. writel(tmp, reg);
  239. }
  240. static void at91_mux_sam9x60_set_slewrate(struct at91_port *pio, u32 pin,
  241. u32 setting)
  242. {
  243. void *reg = &pio->reserved12[3];
  244. u32 tmp;
  245. if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
  246. return;
  247. tmp = readl(reg);
  248. if (setting == SLEWRATE_BIT_DIS)
  249. tmp &= ~BIT(pin);
  250. else
  251. tmp |= BIT(pin);
  252. writel(tmp, reg);
  253. }
  254. static struct at91_pinctrl_mux_ops at91rm9200_ops = {
  255. .mux_A_periph = at91_mux_set_A_periph,
  256. .mux_B_periph = at91_mux_set_B_periph,
  257. .set_deglitch = at91_mux_set_deglitch,
  258. };
  259. static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
  260. .mux_A_periph = at91_mux_pio3_set_A_periph,
  261. .mux_B_periph = at91_mux_pio3_set_B_periph,
  262. .mux_C_periph = at91_mux_pio3_set_C_periph,
  263. .mux_D_periph = at91_mux_pio3_set_D_periph,
  264. .set_deglitch = at91_mux_pio3_set_deglitch,
  265. .set_debounce = at91_mux_pio3_set_debounce,
  266. .set_pulldown = at91_mux_pio3_set_pulldown,
  267. .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
  268. .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
  269. };
  270. static struct at91_pinctrl_mux_ops sama5d3_ops = {
  271. .mux_A_periph = at91_mux_pio3_set_A_periph,
  272. .mux_B_periph = at91_mux_pio3_set_B_periph,
  273. .mux_C_periph = at91_mux_pio3_set_C_periph,
  274. .mux_D_periph = at91_mux_pio3_set_D_periph,
  275. .set_deglitch = at91_mux_pio3_set_deglitch,
  276. .set_debounce = at91_mux_pio3_set_debounce,
  277. .set_pulldown = at91_mux_pio3_set_pulldown,
  278. .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
  279. .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
  280. };
  281. static struct at91_pinctrl_mux_ops sam9x60_ops = {
  282. .mux_A_periph = at91_mux_pio3_set_A_periph,
  283. .mux_B_periph = at91_mux_pio3_set_B_periph,
  284. .mux_C_periph = at91_mux_pio3_set_C_periph,
  285. .mux_D_periph = at91_mux_pio3_set_D_periph,
  286. .set_deglitch = at91_mux_pio3_set_deglitch,
  287. .set_debounce = at91_mux_pio3_set_debounce,
  288. .set_pulldown = at91_mux_pio3_set_pulldown,
  289. .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
  290. .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
  291. .set_slewrate = at91_mux_sam9x60_set_slewrate,
  292. };
  293. static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
  294. {
  295. writel(mask, &pio->pdr);
  296. }
  297. static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
  298. {
  299. writel(mask, &pio->per);
  300. writel(mask, (input ? &pio->odr : &pio->oer));
  301. }
  302. static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
  303. struct at91_port *pio, u32 mask, enum at91_mux mux)
  304. {
  305. at91_mux_disable_interrupt(pio, mask);
  306. switch (mux) {
  307. case AT91_MUX_GPIO:
  308. at91_mux_gpio_enable(pio, mask, 1);
  309. break;
  310. case AT91_MUX_PERIPH_A:
  311. ops->mux_A_periph(pio, mask);
  312. break;
  313. case AT91_MUX_PERIPH_B:
  314. ops->mux_B_periph(pio, mask);
  315. break;
  316. case AT91_MUX_PERIPH_C:
  317. if (!ops->mux_C_periph)
  318. return -EINVAL;
  319. ops->mux_C_periph(pio, mask);
  320. break;
  321. case AT91_MUX_PERIPH_D:
  322. if (!ops->mux_D_periph)
  323. return -EINVAL;
  324. ops->mux_D_periph(pio, mask);
  325. break;
  326. }
  327. if (mux)
  328. at91_mux_gpio_disable(pio, mask);
  329. return 0;
  330. }
  331. static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
  332. struct at91_port *pio, u32 pin, u32 config)
  333. {
  334. u32 mask = BIT(pin);
  335. if ((config & PULL_UP) && (config & PULL_DOWN))
  336. return -EINVAL;
  337. at91_mux_set_output(pio, mask, config & OUTPUT,
  338. (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
  339. at91_mux_set_pullup(pio, mask, config & PULL_UP);
  340. at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
  341. if (ops->set_deglitch)
  342. ops->set_deglitch(pio, mask, config & DEGLITCH);
  343. if (ops->set_debounce)
  344. ops->set_debounce(pio, mask, config & DEBOUNCE,
  345. (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
  346. if (ops->set_pulldown)
  347. ops->set_pulldown(pio, mask, config & PULL_DOWN);
  348. if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
  349. ops->disable_schmitt_trig(pio, mask);
  350. if (ops->set_drivestrength)
  351. ops->set_drivestrength(pio, pin,
  352. (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
  353. if (ops->set_slewrate)
  354. ops->set_slewrate(pio, pin,
  355. (config & SLEWRATE) >> SLEWRATE_SHIFT);
  356. return 0;
  357. }
  358. static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
  359. {
  360. struct at91_pinctrl_priv *priv = dev_get_priv(dev);
  361. if (bank >= priv->nbanks) {
  362. debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
  363. return -EINVAL;
  364. }
  365. if (pin >= MAX_NB_GPIO_PER_BANK) {
  366. debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
  367. return -EINVAL;
  368. }
  369. return 0;
  370. }
  371. static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  372. {
  373. struct at91_pinctrl_priv *priv = dev_get_priv(dev);
  374. const void *blob = gd->fdt_blob;
  375. int node = dev_of_offset(config);
  376. u32 cells[MAX_PINMUX_ENTRIES];
  377. const u32 *list = cells;
  378. u32 bank, pin;
  379. u32 conf, mask, count, i;
  380. int size;
  381. int ret;
  382. enum at91_mux mux;
  383. struct at91_port *pio;
  384. struct at91_pinctrl_mux_ops *ops =
  385. (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
  386. /*
  387. * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
  388. * do sanity check and calculate pins number
  389. */
  390. size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
  391. cells, ARRAY_SIZE(cells));
  392. /* we do not check return since it's safe node passed down */
  393. count = size >> 2;
  394. if (!count)
  395. return -EINVAL;
  396. for (i = 0; i < count; i++) {
  397. bank = *list++;
  398. pin = *list++;
  399. mux = *list++;
  400. conf = *list++;
  401. ret = at91_pin_check_config(dev, bank, pin);
  402. if (ret)
  403. return ret;
  404. pio = priv->reg_base[bank];
  405. mask = BIT(pin);
  406. ret = at91_pmx_set(ops, pio, mask, mux);
  407. if (ret)
  408. return ret;
  409. ret = at91_pinconf_set(ops, pio, pin, conf);
  410. if (ret)
  411. return ret;
  412. }
  413. return 0;
  414. }
  415. const struct pinctrl_ops at91_pinctrl_ops = {
  416. .set_state = at91_pinctrl_set_state,
  417. };
  418. static int at91_pinctrl_probe(struct udevice *dev)
  419. {
  420. struct at91_pinctrl_priv *priv = dev_get_priv(dev);
  421. fdt_addr_t addr_base;
  422. int index;
  423. for (index = 0; index < MAX_GPIO_BANKS; index++) {
  424. addr_base = devfdt_get_addr_index(dev, index);
  425. if (addr_base == FDT_ADDR_T_NONE)
  426. break;
  427. priv->reg_base[index] = (struct at91_port *)addr_base;
  428. }
  429. priv->nbanks = index;
  430. return 0;
  431. }
  432. static const struct udevice_id at91_pinctrl_match[] = {
  433. { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
  434. { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
  435. { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
  436. { .compatible = "microchip,sam9x60-pinctrl", .data = (ulong)&sam9x60_ops },
  437. {}
  438. };
  439. U_BOOT_DRIVER(atmel_sama5d3_pinctrl) = {
  440. .name = "atmel_sama5d3_pinctrl",
  441. .id = UCLASS_PINCTRL,
  442. .of_match = at91_pinctrl_match,
  443. .probe = at91_pinctrl_probe,
  444. .priv_auto = sizeof(struct at91_pinctrl_priv),
  445. .ops = &at91_pinctrl_ops,
  446. };
  447. DM_DRIVER_ALIAS(atmel_sama5d3_pinctrl, atmel_at91rm9200_pinctrl)