pinctrl-at91-pio4.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO4 pinctrl driver
  4. *
  5. * Copyright (C) 2016 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <asm/global_data.h>
  11. #include <dm/pinctrl.h>
  12. #include <linux/bitops.h>
  13. #include <linux/io.h>
  14. #include <linux/err.h>
  15. #include <mach/atmel_pio4.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /*
  18. * Warning:
  19. * In order to not introduce confusion between Atmel PIO groups and pinctrl
  20. * framework groups, Atmel PIO groups will be called banks.
  21. */
  22. struct atmel_pio4_plat {
  23. struct atmel_pio4_port *reg_base;
  24. unsigned int slew_rate_support;
  25. };
  26. static const struct pinconf_param conf_params[] = {
  27. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  28. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
  29. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
  30. { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
  31. { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
  32. { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
  33. { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
  34. { "atmel,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
  35. { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
  36. };
  37. static u32 atmel_pinctrl_get_pinconf(struct udevice *config,
  38. struct atmel_pio4_plat *plat)
  39. {
  40. const struct pinconf_param *params;
  41. u32 param, arg, conf = 0;
  42. u32 i;
  43. u32 val;
  44. for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
  45. params = &conf_params[i];
  46. if (!dev_read_prop(config, params->property, NULL))
  47. continue;
  48. param = params->param;
  49. arg = params->default_value;
  50. /* Keep slew rate enabled by default. */
  51. if (plat->slew_rate_support)
  52. conf |= ATMEL_PIO_SR;
  53. switch (param) {
  54. case PIN_CONFIG_BIAS_DISABLE:
  55. conf &= (~ATMEL_PIO_PUEN_MASK);
  56. conf &= (~ATMEL_PIO_PDEN_MASK);
  57. break;
  58. case PIN_CONFIG_BIAS_PULL_UP:
  59. conf |= ATMEL_PIO_PUEN_MASK;
  60. break;
  61. case PIN_CONFIG_BIAS_PULL_DOWN:
  62. conf |= ATMEL_PIO_PDEN_MASK;
  63. break;
  64. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  65. if (arg == 0)
  66. conf &= (~ATMEL_PIO_OPD_MASK);
  67. else
  68. conf |= ATMEL_PIO_OPD_MASK;
  69. break;
  70. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  71. if (arg == 0)
  72. conf |= ATMEL_PIO_SCHMITT_MASK;
  73. else
  74. conf &= (~ATMEL_PIO_SCHMITT_MASK);
  75. break;
  76. case PIN_CONFIG_INPUT_DEBOUNCE:
  77. if (arg == 0) {
  78. conf &= (~ATMEL_PIO_IFEN_MASK);
  79. conf &= (~ATMEL_PIO_IFSCEN_MASK);
  80. } else {
  81. conf |= ATMEL_PIO_IFEN_MASK;
  82. conf |= ATMEL_PIO_IFSCEN_MASK;
  83. }
  84. break;
  85. case PIN_CONFIG_DRIVE_STRENGTH:
  86. dev_read_u32(config, params->property, &val);
  87. conf &= (~ATMEL_PIO_DRVSTR_MASK);
  88. conf |= (val << ATMEL_PIO_DRVSTR_OFFSET)
  89. & ATMEL_PIO_DRVSTR_MASK;
  90. break;
  91. case PIN_CONFIG_SLEW_RATE:
  92. if (!plat->slew_rate_support)
  93. break;
  94. dev_read_u32(config, params->property, &val);
  95. /* And disable it if requested. */
  96. if (val == 0)
  97. conf &= ~ATMEL_PIO_SR;
  98. break;
  99. default:
  100. printf("%s: Unsupported configuration parameter: %u\n",
  101. __func__, param);
  102. break;
  103. }
  104. }
  105. return conf;
  106. }
  107. static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
  108. u32 bank)
  109. {
  110. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  111. struct atmel_pio4_port *bank_base =
  112. (struct atmel_pio4_port *)((u32)plat->reg_base +
  113. ATMEL_PIO_BANK_OFFSET * bank);
  114. return bank_base;
  115. }
  116. #define MAX_PINMUX_ENTRIES 40
  117. static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  118. {
  119. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  120. struct atmel_pio4_port *bank_base;
  121. const void *blob = gd->fdt_blob;
  122. int node = dev_of_offset(config);
  123. u32 offset, func, bank, line;
  124. u32 cells[MAX_PINMUX_ENTRIES];
  125. u32 i, conf;
  126. int count;
  127. conf = atmel_pinctrl_get_pinconf(config, plat);
  128. count = fdtdec_get_int_array_count(blob, node, "pinmux",
  129. cells, ARRAY_SIZE(cells));
  130. if (count < 0) {
  131. printf("%s: bad pinmux array %d\n", __func__, count);
  132. return -EINVAL;
  133. }
  134. if (count > MAX_PINMUX_ENTRIES) {
  135. printf("%s: unsupported pinmux array count %d\n",
  136. __func__, count);
  137. return -EINVAL;
  138. }
  139. for (i = 0 ; i < count; i++) {
  140. offset = ATMEL_GET_PIN_NO(cells[i]);
  141. func = ATMEL_GET_PIN_FUNC(cells[i]);
  142. bank = ATMEL_PIO_BANK(offset);
  143. line = ATMEL_PIO_LINE(offset);
  144. bank_base = atmel_pio4_bank_base(dev, bank);
  145. writel(BIT(line), &bank_base->mskr);
  146. conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
  147. conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK);
  148. writel(conf, &bank_base->cfgr);
  149. }
  150. return 0;
  151. }
  152. const struct pinctrl_ops atmel_pinctrl_ops = {
  153. .set_state = atmel_pinctrl_set_state,
  154. };
  155. static int atmel_pinctrl_probe(struct udevice *dev)
  156. {
  157. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  158. ulong priv = dev_get_driver_data(dev);
  159. fdt_addr_t addr_base;
  160. dev = dev_get_parent(dev);
  161. addr_base = dev_read_addr(dev);
  162. if (addr_base == FDT_ADDR_T_NONE)
  163. return -EINVAL;
  164. plat->reg_base = (struct atmel_pio4_port *)addr_base;
  165. plat->slew_rate_support = priv;
  166. return 0;
  167. }
  168. static const struct udevice_id atmel_pinctrl_match[] = {
  169. { .compatible = "atmel,sama5d2-pinctrl" },
  170. { .compatible = "microchip,sama7g5-pinctrl",
  171. .data = (ulong)1, },
  172. {}
  173. };
  174. U_BOOT_DRIVER(atmel_pinctrl) = {
  175. .name = "pinctrl_atmel_pio4",
  176. .id = UCLASS_PINCTRL,
  177. .of_match = atmel_pinctrl_match,
  178. .probe = atmel_pinctrl_probe,
  179. .plat_auto = sizeof(struct atmel_pio4_plat),
  180. .ops = &atmel_pinctrl_ops,
  181. };