pinctrl_apl.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 Intel Corp.
  4. * Copyright 2019 Google LLC
  5. *
  6. * Taken partly from coreboot gpio.c
  7. */
  8. #define LOG_CATEGORY UCLASS_GPIO
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <dt-structs.h>
  12. #include <log.h>
  13. #include <p2sb.h>
  14. #include <asm/intel_pinctrl.h>
  15. #include <asm-generic/gpio.h>
  16. #include <asm/intel_pinctrl_defs.h>
  17. static const struct reset_mapping rst_map[] = {
  18. { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  19. { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  20. { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  21. };
  22. /* Groups for each community */
  23. static const struct pad_group apl_community_n_groups[] = {
  24. INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */
  25. INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */
  26. INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */
  27. };
  28. static const struct pad_group apl_community_w_groups[] = {
  29. INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1), /* WEST 0 */
  30. INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
  31. };
  32. static const struct pad_group apl_community_sw_groups[] = {
  33. INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */
  34. INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */
  35. };
  36. static const struct pad_group apl_community_nw_groups[] = {
  37. INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */
  38. INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106), /* NORTHWEST 1 */
  39. INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */
  40. };
  41. /* TODO(sjg@chromium.org): Consider moving this to device tree */
  42. static const struct pad_community apl_gpio_communities[] = {
  43. {
  44. .port = PID_GPIO_N,
  45. .first_pad = N_OFFSET,
  46. .last_pad = SVID0_CLK,
  47. .num_gpi_regs = NUM_N_GPI_REGS,
  48. .gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
  49. + NUM_SW_GPI_REGS,
  50. .pad_cfg_base = PAD_CFG_BASE,
  51. .host_own_reg_0 = HOSTSW_OWN_REG_0,
  52. .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  53. .gpi_int_en_reg_0 = GPI_INT_EN_0,
  54. .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  55. .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  56. .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  57. .name = "GPIO_GPE_N",
  58. .reset_map = rst_map,
  59. .num_reset_vals = ARRAY_SIZE(rst_map),
  60. .groups = apl_community_n_groups,
  61. .num_groups = ARRAY_SIZE(apl_community_n_groups),
  62. }, {
  63. .port = PID_GPIO_NW,
  64. .first_pad = NW_OFFSET,
  65. .last_pad = GPIO_123,
  66. .num_gpi_regs = NUM_NW_GPI_REGS,
  67. .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
  68. .pad_cfg_base = PAD_CFG_BASE,
  69. .host_own_reg_0 = HOSTSW_OWN_REG_0,
  70. .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  71. .gpi_int_en_reg_0 = GPI_INT_EN_0,
  72. .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  73. .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  74. .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  75. .name = "GPIO_GPE_NW",
  76. .reset_map = rst_map,
  77. .num_reset_vals = ARRAY_SIZE(rst_map),
  78. .groups = apl_community_nw_groups,
  79. .num_groups = ARRAY_SIZE(apl_community_nw_groups),
  80. }, {
  81. .port = PID_GPIO_W,
  82. .first_pad = W_OFFSET,
  83. .last_pad = SUSPWRDNACK,
  84. .num_gpi_regs = NUM_W_GPI_REGS,
  85. .gpi_status_offset = NUM_SW_GPI_REGS,
  86. .pad_cfg_base = PAD_CFG_BASE,
  87. .host_own_reg_0 = HOSTSW_OWN_REG_0,
  88. .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  89. .gpi_int_en_reg_0 = GPI_INT_EN_0,
  90. .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  91. .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  92. .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  93. .name = "GPIO_GPE_W",
  94. .reset_map = rst_map,
  95. .num_reset_vals = ARRAY_SIZE(rst_map),
  96. .groups = apl_community_w_groups,
  97. .num_groups = ARRAY_SIZE(apl_community_w_groups),
  98. }, {
  99. .port = PID_GPIO_SW,
  100. .first_pad = SW_OFFSET,
  101. .last_pad = LPC_FRAMEB,
  102. .num_gpi_regs = NUM_SW_GPI_REGS,
  103. .gpi_status_offset = 0,
  104. .pad_cfg_base = PAD_CFG_BASE,
  105. .host_own_reg_0 = HOSTSW_OWN_REG_0,
  106. .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  107. .gpi_int_en_reg_0 = GPI_INT_EN_0,
  108. .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  109. .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  110. .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  111. .name = "GPIO_GPE_SW",
  112. .reset_map = rst_map,
  113. .num_reset_vals = ARRAY_SIZE(rst_map),
  114. .groups = apl_community_sw_groups,
  115. .num_groups = ARRAY_SIZE(apl_community_sw_groups),
  116. },
  117. };
  118. static int apl_pinctrl_of_to_plat(struct udevice *dev)
  119. {
  120. struct p2sb_child_plat *pplat;
  121. const struct pad_community *comm = NULL;
  122. int i;
  123. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  124. struct apl_gpio_plat *plat = dev_get_plat(dev);
  125. int ret;
  126. /*
  127. * It would be nice to do this in the bind() method, but with
  128. * of-platdata binding happens in the order that DM finds things in the
  129. * linker list (i.e. alphabetical order by driver name). So the GPIO
  130. * device may well be bound before its parent (p2sb), and this call
  131. * will fail if p2sb is not bound yet.
  132. */
  133. ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id);
  134. if (ret)
  135. return log_msg_ret("Could not set port id", ret);
  136. #endif
  137. /* Attach this device to its community structure */
  138. pplat = dev_get_parent_plat(dev);
  139. for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
  140. if (apl_gpio_communities[i].port == pplat->pid)
  141. comm = &apl_gpio_communities[i];
  142. }
  143. return intel_pinctrl_of_to_plat(dev, comm, 2);
  144. }
  145. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  146. static const struct udevice_id apl_gpio_ids[] = {
  147. { .compatible = "intel,apl-pinctrl"},
  148. { }
  149. };
  150. #endif
  151. U_BOOT_DRIVER(intel_apl_pinctrl) = {
  152. .name = "intel_apl_pinctrl",
  153. .id = UCLASS_PINCTRL,
  154. .of_match = of_match_ptr(apl_gpio_ids),
  155. .probe = intel_pinctrl_probe,
  156. .ops = &intel_pinctrl_ops,
  157. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  158. .bind = dm_scan_fdt_dev,
  159. #endif
  160. .of_to_plat = apl_pinctrl_of_to_plat,
  161. .priv_auto = sizeof(struct intel_pinctrl_priv),
  162. .plat_auto = sizeof(struct apl_gpio_plat),
  163. };