pinctrl_ar933x.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <dm/pinctrl.h>
  12. #include <mach/ar71xx_regs.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. enum periph_id {
  15. PERIPH_ID_UART0,
  16. PERIPH_ID_SPI0,
  17. PERIPH_ID_NONE = -1,
  18. };
  19. struct ar933x_pinctrl_priv {
  20. void __iomem *regs;
  21. };
  22. static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
  23. {
  24. switch (cs) {
  25. case 0:
  26. clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
  27. AR933X_GPIO(4), AR933X_GPIO(3) |
  28. AR933X_GPIO(5) | AR933X_GPIO(2));
  29. setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
  30. AR933X_GPIO_FUNC_SPI_EN |
  31. AR933X_GPIO_FUNC_RES_TRUE);
  32. break;
  33. }
  34. }
  35. static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
  36. {
  37. switch (uart_id) {
  38. case PERIPH_ID_UART0:
  39. clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
  40. AR933X_GPIO(9), AR933X_GPIO(10));
  41. setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
  42. AR933X_GPIO_FUNC_UART_EN |
  43. AR933X_GPIO_FUNC_RES_TRUE);
  44. break;
  45. }
  46. }
  47. static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
  48. {
  49. struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
  50. debug("%s: func=%x, flags=%x\n", __func__, func, flags);
  51. switch (func) {
  52. case PERIPH_ID_SPI0:
  53. pinctrl_ar933x_spi_config(priv, flags);
  54. break;
  55. case PERIPH_ID_UART0:
  56. pinctrl_ar933x_uart_config(priv, func);
  57. break;
  58. default:
  59. return -EINVAL;
  60. }
  61. return 0;
  62. }
  63. static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
  64. struct udevice *periph)
  65. {
  66. u32 cell[2];
  67. int ret;
  68. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
  69. "interrupts", cell, ARRAY_SIZE(cell));
  70. if (ret < 0)
  71. return -EINVAL;
  72. switch (cell[0]) {
  73. case 128:
  74. return PERIPH_ID_UART0;
  75. case 129:
  76. return PERIPH_ID_SPI0;
  77. }
  78. return -ENOENT;
  79. }
  80. static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
  81. struct udevice *periph)
  82. {
  83. int func;
  84. func = ar933x_pinctrl_get_periph_id(dev, periph);
  85. if (func < 0)
  86. return func;
  87. return ar933x_pinctrl_request(dev, func, 0);
  88. }
  89. static struct pinctrl_ops ar933x_pinctrl_ops = {
  90. .set_state_simple = ar933x_pinctrl_set_state_simple,
  91. .request = ar933x_pinctrl_request,
  92. .get_periph_id = ar933x_pinctrl_get_periph_id,
  93. };
  94. static int ar933x_pinctrl_probe(struct udevice *dev)
  95. {
  96. struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
  97. fdt_addr_t addr;
  98. addr = dev_read_addr(dev);
  99. if (addr == FDT_ADDR_T_NONE)
  100. return -EINVAL;
  101. priv->regs = map_physmem(addr,
  102. AR71XX_GPIO_SIZE,
  103. MAP_NOCACHE);
  104. return 0;
  105. }
  106. static const struct udevice_id ar933x_pinctrl_ids[] = {
  107. { .compatible = "qca,ar933x-pinctrl" },
  108. { }
  109. };
  110. U_BOOT_DRIVER(pinctrl_ar933x) = {
  111. .name = "pinctrl_ar933x",
  112. .id = UCLASS_PINCTRL,
  113. .of_match = ar933x_pinctrl_ids,
  114. .priv_auto = sizeof(struct ar933x_pinctrl_priv),
  115. .ops = &ar933x_pinctrl_ops,
  116. .probe = ar933x_pinctrl_probe,
  117. };