ti-pipe3-phy.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
  4. * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dm/device.h>
  9. #include <generic-phy.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <syscon.h>
  14. #include <regmap.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. /* PLLCTRL Registers */
  19. #define PLL_STATUS 0x00000004
  20. #define PLL_GO 0x00000008
  21. #define PLL_CONFIGURATION1 0x0000000C
  22. #define PLL_CONFIGURATION2 0x00000010
  23. #define PLL_CONFIGURATION3 0x00000014
  24. #define PLL_CONFIGURATION4 0x00000020
  25. #define PLL_REGM_MASK 0x001FFE00
  26. #define PLL_REGM_SHIFT 9
  27. #define PLL_REGM_F_MASK 0x0003FFFF
  28. #define PLL_REGM_F_SHIFT 0
  29. #define PLL_REGN_MASK 0x000001FE
  30. #define PLL_REGN_SHIFT 1
  31. #define PLL_SELFREQDCO_MASK 0x0000000E
  32. #define PLL_SELFREQDCO_SHIFT 1
  33. #define PLL_SD_MASK 0x0003FC00
  34. #define PLL_SD_SHIFT 10
  35. #define SET_PLL_GO 0x1
  36. #define PLL_TICOPWDN BIT(16)
  37. #define PLL_LDOPWDN BIT(15)
  38. #define PLL_LOCK 0x2
  39. #define PLL_IDLE 0x1
  40. /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
  41. #define SATA_PLL_SOFT_RESET (1<<18)
  42. /* PHY POWER CONTROL Register */
  43. #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
  44. #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
  45. #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
  46. #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  47. #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  48. #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  49. /* PHY RX Registers */
  50. #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
  51. #define INTERFACE_MASK GENMASK(31, 27)
  52. #define INTERFACE_SHIFT 27
  53. #define INTERFACE_MODE_USBSS BIT(4)
  54. #define INTERFACE_MODE_SATA_1P5 BIT(3)
  55. #define INTERFACE_MODE_SATA_3P0 BIT(2)
  56. #define INTERFACE_MODE_PCIE BIT(0)
  57. #define LOSD_MASK GENMASK(17, 14)
  58. #define LOSD_SHIFT 14
  59. #define MEM_PLLDIV GENMASK(6, 5)
  60. #define PIPE3_PHY_RX_TRIM 0x0000001C
  61. #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
  62. #define MEM_DLL_TRIM_SHIFT 30
  63. #define PIPE3_PHY_RX_DLL 0x00000024
  64. #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
  65. #define MEM_DLL_PHINT_RATE_SHIFT 30
  66. #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
  67. #define MEM_HS_RATE_MASK GENMASK(28, 27)
  68. #define MEM_HS_RATE_SHIFT 27
  69. #define MEM_OVRD_HS_RATE BIT(26)
  70. #define MEM_OVRD_HS_RATE_SHIFT 26
  71. #define MEM_CDR_FASTLOCK BIT(23)
  72. #define MEM_CDR_FASTLOCK_SHIFT 23
  73. #define MEM_CDR_LBW_MASK GENMASK(22, 21)
  74. #define MEM_CDR_LBW_SHIFT 21
  75. #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
  76. #define MEM_CDR_STEPCNT_SHIFT 19
  77. #define MEM_CDR_STL_MASK GENMASK(18, 16)
  78. #define MEM_CDR_STL_SHIFT 16
  79. #define MEM_CDR_THR_MASK GENMASK(15, 13)
  80. #define MEM_CDR_THR_SHIFT 13
  81. #define MEM_CDR_THR_MODE BIT(12)
  82. #define MEM_CDR_THR_MODE_SHIFT 12
  83. #define MEM_CDR_2NDO_SDM_MODE BIT(11)
  84. #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
  85. #define PIPE3_PHY_RX_EQUALIZER 0x00000038
  86. #define MEM_EQLEV_MASK GENMASK(31, 16)
  87. #define MEM_EQLEV_SHIFT 16
  88. #define MEM_EQFTC_MASK GENMASK(15, 11)
  89. #define MEM_EQFTC_SHIFT 11
  90. #define MEM_EQCTL_MASK GENMASK(10, 7)
  91. #define MEM_EQCTL_SHIFT 7
  92. #define MEM_OVRD_EQLEV BIT(2)
  93. #define MEM_OVRD_EQLEV_SHIFT 2
  94. #define MEM_OVRD_EQFTC BIT(1)
  95. #define MEM_OVRD_EQFTC_SHIFT 1
  96. #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
  97. #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
  98. #define MEM_CDR_LOS_SOURCE_SHIFT 9
  99. #define PLL_IDLE_TIME 100 /* in milliseconds */
  100. #define PLL_LOCK_TIME 100 /* in milliseconds */
  101. enum pipe3_mode { PIPE3_MODE_PCIE = 1,
  102. PIPE3_MODE_SATA,
  103. PIPE3_MODE_USBSS };
  104. struct pipe3_settings {
  105. u8 ana_interface;
  106. u8 ana_losd;
  107. u8 dig_fastlock;
  108. u8 dig_lbw;
  109. u8 dig_stepcnt;
  110. u8 dig_stl;
  111. u8 dig_thr;
  112. u8 dig_thr_mode;
  113. u8 dig_2ndo_sdm_mode;
  114. u8 dig_hs_rate;
  115. u8 dig_ovrd_hs_rate;
  116. u8 dll_trim_sel;
  117. u8 dll_phint_rate;
  118. u8 eq_lev;
  119. u8 eq_ftc;
  120. u8 eq_ctl;
  121. u8 eq_ovrd_lev;
  122. u8 eq_ovrd_ftc;
  123. };
  124. struct omap_pipe3 {
  125. void __iomem *pll_ctrl_base;
  126. void __iomem *phy_rx;
  127. void __iomem *power_reg;
  128. void __iomem *pll_reset_reg;
  129. struct pipe3_dpll_map *dpll_map;
  130. enum pipe3_mode mode;
  131. struct pipe3_settings settings;
  132. };
  133. struct pipe3_dpll_params {
  134. u16 m;
  135. u8 n;
  136. u8 freq:3;
  137. u8 sd;
  138. u32 mf;
  139. };
  140. struct pipe3_dpll_map {
  141. unsigned long rate;
  142. struct pipe3_dpll_params params;
  143. };
  144. struct pipe3_data {
  145. enum pipe3_mode mode;
  146. struct pipe3_dpll_map *dpll_map;
  147. struct pipe3_settings settings;
  148. };
  149. static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
  150. {
  151. return readl(addr + offset);
  152. }
  153. static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
  154. u32 data)
  155. {
  156. writel(data, addr + offset);
  157. }
  158. static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
  159. *pipe3)
  160. {
  161. u32 rate;
  162. struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
  163. rate = get_sys_clk_freq();
  164. for (; dpll_map->rate; dpll_map++) {
  165. if (rate == dpll_map->rate)
  166. return &dpll_map->params;
  167. }
  168. printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
  169. __func__, rate);
  170. return NULL;
  171. }
  172. static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
  173. {
  174. u32 val;
  175. int timeout = PLL_LOCK_TIME;
  176. do {
  177. mdelay(1);
  178. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
  179. if (val & PLL_LOCK)
  180. break;
  181. } while (--timeout);
  182. if (!(val & PLL_LOCK)) {
  183. printf("%s: DPLL failed to lock\n", __func__);
  184. return -EBUSY;
  185. }
  186. return 0;
  187. }
  188. static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
  189. {
  190. u32 val;
  191. struct pipe3_dpll_params *dpll_params;
  192. dpll_params = omap_pipe3_get_dpll_params(pipe3);
  193. if (!dpll_params) {
  194. printf("%s: Invalid DPLL parameters\n", __func__);
  195. return -EINVAL;
  196. }
  197. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
  198. val &= ~PLL_REGN_MASK;
  199. val |= dpll_params->n << PLL_REGN_SHIFT;
  200. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
  201. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
  202. val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
  203. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  204. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
  205. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
  206. val &= ~PLL_REGM_MASK;
  207. val |= dpll_params->m << PLL_REGM_SHIFT;
  208. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
  209. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
  210. val &= ~PLL_REGM_F_MASK;
  211. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  212. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
  213. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
  214. val &= ~PLL_SD_MASK;
  215. val |= dpll_params->sd << PLL_SD_SHIFT;
  216. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
  217. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  218. return omap_pipe3_wait_lock(pipe3);
  219. }
  220. static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
  221. {
  222. u32 val, rate;
  223. val = readl(pipe3->power_reg);
  224. rate = get_sys_clk_freq();
  225. rate = rate/1000000;
  226. if (on) {
  227. val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
  228. PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
  229. val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  230. writel(val, pipe3->power_reg);
  231. /* Power up TX before RX for SATA & USB */
  232. val |= PIPE3_PHY_TX_POWERON;
  233. writel(val, pipe3->power_reg);
  234. val |= PIPE3_PHY_RX_POWERON;
  235. writel(val, pipe3->power_reg);
  236. } else {
  237. val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  238. writel(val, pipe3->power_reg);
  239. }
  240. }
  241. static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
  242. {
  243. u32 val;
  244. struct pipe3_settings *s = &phy->settings;
  245. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
  246. val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
  247. val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
  248. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
  249. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
  250. val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
  251. MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
  252. MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
  253. val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
  254. s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
  255. s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
  256. s->dig_lbw << MEM_CDR_LBW_SHIFT |
  257. s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
  258. s->dig_stl << MEM_CDR_STL_SHIFT |
  259. s->dig_thr << MEM_CDR_THR_SHIFT |
  260. s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
  261. s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
  262. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
  263. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
  264. val &= ~MEM_DLL_TRIM_SEL_MASK;
  265. val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
  266. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
  267. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
  268. val &= ~MEM_DLL_PHINT_RATE_MASK;
  269. val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
  270. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
  271. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
  272. val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
  273. MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
  274. val |= s->eq_lev << MEM_EQLEV_SHIFT |
  275. s->eq_ftc << MEM_EQFTC_SHIFT |
  276. s->eq_ctl << MEM_EQCTL_SHIFT |
  277. s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
  278. s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
  279. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
  280. if (phy->mode == PIPE3_MODE_SATA) {
  281. val = omap_pipe3_readl(phy->phy_rx,
  282. SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
  283. val &= ~MEM_CDR_LOS_SOURCE_MASK;
  284. omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
  285. val);
  286. }
  287. }
  288. static int pipe3_init(struct phy *phy)
  289. {
  290. int ret;
  291. u32 val;
  292. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  293. /* Program the DPLL only if not locked */
  294. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
  295. if (!(val & PLL_LOCK)) {
  296. ret = omap_pipe3_dpll_program(pipe3);
  297. if (ret)
  298. return ret;
  299. ti_pipe3_calibrate(pipe3);
  300. } else {
  301. /* else just bring it out of IDLE mode */
  302. val = omap_pipe3_readl(pipe3->pll_ctrl_base,
  303. PLL_CONFIGURATION2);
  304. if (val & PLL_IDLE) {
  305. val &= ~PLL_IDLE;
  306. omap_pipe3_writel(pipe3->pll_ctrl_base,
  307. PLL_CONFIGURATION2, val);
  308. ret = omap_pipe3_wait_lock(pipe3);
  309. if (ret)
  310. return ret;
  311. }
  312. }
  313. return 0;
  314. }
  315. static int pipe3_power_on(struct phy *phy)
  316. {
  317. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  318. /* Power up the PHY */
  319. omap_control_pipe3_power(pipe3, 1);
  320. return 0;
  321. }
  322. static int pipe3_power_off(struct phy *phy)
  323. {
  324. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  325. /* Power down the PHY */
  326. omap_control_pipe3_power(pipe3, 0);
  327. return 0;
  328. }
  329. static int pipe3_exit(struct phy *phy)
  330. {
  331. u32 val;
  332. int timeout = PLL_IDLE_TIME;
  333. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  334. pipe3_power_off(phy);
  335. /* Put DPLL in IDLE mode */
  336. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
  337. val |= PLL_IDLE;
  338. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
  339. /* wait for LDO and Oscillator to power down */
  340. do {
  341. mdelay(1);
  342. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
  343. if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
  344. break;
  345. } while (--timeout);
  346. if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
  347. pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
  348. __func__, val);
  349. return -EBUSY;
  350. }
  351. if (pipe3->pll_reset_reg) {
  352. val = readl(pipe3->pll_reset_reg);
  353. writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
  354. mdelay(1);
  355. writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
  356. }
  357. return 0;
  358. }
  359. static void *get_reg(struct udevice *dev, const char *name)
  360. {
  361. struct udevice *syscon;
  362. struct regmap *regmap;
  363. const fdt32_t *cell;
  364. int len, err;
  365. void *base;
  366. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  367. name, &syscon);
  368. if (err) {
  369. pr_err("unable to find syscon device for %s (%d)\n",
  370. name, err);
  371. return NULL;
  372. }
  373. regmap = syscon_get_regmap(syscon);
  374. if (IS_ERR(regmap)) {
  375. pr_err("unable to find regmap for %s (%ld)\n",
  376. name, PTR_ERR(regmap));
  377. return NULL;
  378. }
  379. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
  380. &len);
  381. if (len < 2*sizeof(fdt32_t)) {
  382. pr_err("offset not available for %s\n", name);
  383. return NULL;
  384. }
  385. base = regmap_get_range(regmap, 0);
  386. if (!base)
  387. return NULL;
  388. return fdtdec_get_number(cell + 1, 1) + base;
  389. }
  390. static int pipe3_phy_probe(struct udevice *dev)
  391. {
  392. fdt_addr_t addr;
  393. fdt_size_t sz;
  394. struct omap_pipe3 *pipe3 = dev_get_priv(dev);
  395. struct pipe3_data *data;
  396. /* PHY_RX */
  397. addr = devfdt_get_addr_size_index(dev, 0, &sz);
  398. if (addr == FDT_ADDR_T_NONE) {
  399. pr_err("missing phy_rx address\n");
  400. return -EINVAL;
  401. }
  402. pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
  403. if (!pipe3->phy_rx) {
  404. pr_err("unable to remap phy_rx\n");
  405. return -EINVAL;
  406. }
  407. /* PLLCTRL */
  408. addr = devfdt_get_addr_size_index(dev, 2, &sz);
  409. if (addr == FDT_ADDR_T_NONE) {
  410. pr_err("missing pll ctrl address\n");
  411. return -EINVAL;
  412. }
  413. pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
  414. if (!pipe3->pll_ctrl_base) {
  415. pr_err("unable to remap pll ctrl\n");
  416. return -EINVAL;
  417. }
  418. pipe3->power_reg = get_reg(dev, "syscon-phy-power");
  419. if (!pipe3->power_reg)
  420. return -EINVAL;
  421. data = (struct pipe3_data *)dev_get_driver_data(dev);
  422. pipe3->mode = data->mode;
  423. pipe3->dpll_map = data->dpll_map;
  424. pipe3->settings = data->settings;
  425. if (pipe3->mode == PIPE3_MODE_SATA) {
  426. pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
  427. if (!pipe3->pll_reset_reg)
  428. return -EINVAL;
  429. }
  430. return 0;
  431. }
  432. static struct pipe3_dpll_map dpll_map_sata[] = {
  433. {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
  434. {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
  435. {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
  436. {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
  437. {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
  438. {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
  439. { }, /* Terminator */
  440. };
  441. static struct pipe3_dpll_map dpll_map_usb[] = {
  442. {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
  443. {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
  444. {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
  445. {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
  446. {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
  447. {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
  448. { }, /* Terminator */
  449. };
  450. static struct pipe3_data data_usb = {
  451. .mode = PIPE3_MODE_USBSS,
  452. .dpll_map = dpll_map_usb,
  453. .settings = {
  454. /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
  455. .ana_interface = INTERFACE_MODE_USBSS,
  456. .ana_losd = 0xa,
  457. .dig_fastlock = 1,
  458. .dig_lbw = 3,
  459. .dig_stepcnt = 0,
  460. .dig_stl = 0x3,
  461. .dig_thr = 1,
  462. .dig_thr_mode = 1,
  463. .dig_2ndo_sdm_mode = 0,
  464. .dig_hs_rate = 0,
  465. .dig_ovrd_hs_rate = 1,
  466. .dll_trim_sel = 0x2,
  467. .dll_phint_rate = 0x3,
  468. .eq_lev = 0,
  469. .eq_ftc = 0,
  470. .eq_ctl = 0x9,
  471. .eq_ovrd_lev = 0,
  472. .eq_ovrd_ftc = 0,
  473. },
  474. };
  475. static struct pipe3_data data_sata = {
  476. .mode = PIPE3_MODE_SATA,
  477. .dpll_map = dpll_map_sata,
  478. .settings = {
  479. /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
  480. .ana_interface = INTERFACE_MODE_SATA_3P0,
  481. .ana_losd = 0x5,
  482. .dig_fastlock = 1,
  483. .dig_lbw = 3,
  484. .dig_stepcnt = 0,
  485. .dig_stl = 0x3,
  486. .dig_thr = 1,
  487. .dig_thr_mode = 1,
  488. .dig_2ndo_sdm_mode = 0,
  489. .dig_hs_rate = 0, /* Not in TRM preferred settings */
  490. .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
  491. .dll_trim_sel = 0x1,
  492. .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
  493. .eq_lev = 0,
  494. .eq_ftc = 0x1f,
  495. .eq_ctl = 0,
  496. .eq_ovrd_lev = 1,
  497. .eq_ovrd_ftc = 1,
  498. },
  499. };
  500. static const struct udevice_id pipe3_phy_ids[] = {
  501. { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
  502. { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
  503. { }
  504. };
  505. static struct phy_ops pipe3_phy_ops = {
  506. .init = pipe3_init,
  507. .power_on = pipe3_power_on,
  508. .power_off = pipe3_power_off,
  509. .exit = pipe3_exit,
  510. };
  511. U_BOOT_DRIVER(pipe3_phy) = {
  512. .name = "pipe3_phy",
  513. .id = UCLASS_PHY,
  514. .of_match = pipe3_phy_ids,
  515. .ops = &pipe3_phy_ops,
  516. .probe = pipe3_phy_probe,
  517. .priv_auto = sizeof(struct omap_pipe3),
  518. };