phy-core-mipi-dphy.c 3.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2013 NVIDIA Corporation
  4. * Copyright (C) 2018 Cadence Design Systems Inc.
  5. */
  6. #include <common.h>
  7. #include <div64.h>
  8. #include <phy-mipi-dphy.h>
  9. #define PSEC_PER_SEC 1000000000000LL
  10. /*
  11. * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
  12. * from the valid ranges specified in Section 6.9, Table 14, Page 41
  13. * of the D-PHY specification (v2.1).
  14. */
  15. int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
  16. unsigned int bpp,
  17. unsigned int lanes,
  18. struct phy_configure_opts_mipi_dphy *cfg)
  19. {
  20. unsigned long long hs_clk_rate;
  21. unsigned long long ui;
  22. if (!cfg)
  23. return -EINVAL;
  24. hs_clk_rate = pixel_clock * bpp;
  25. do_div(hs_clk_rate, lanes);
  26. ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
  27. do_div(ui, hs_clk_rate);
  28. cfg->clk_miss = 0;
  29. cfg->clk_post = 60000 + 52 * ui;
  30. cfg->clk_pre = 8000;
  31. cfg->clk_prepare = 38000;
  32. cfg->clk_settle = 95000;
  33. cfg->clk_term_en = 0;
  34. cfg->clk_trail = 60000;
  35. cfg->clk_zero = 262000;
  36. cfg->d_term_en = 0;
  37. cfg->eot = 0;
  38. cfg->hs_exit = 100000;
  39. cfg->hs_prepare = 40000 + 4 * ui;
  40. cfg->hs_zero = 105000 + 6 * ui;
  41. cfg->hs_settle = 85000 + 6 * ui;
  42. cfg->hs_skip = 40000;
  43. /*
  44. * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
  45. * contains this formula as:
  46. *
  47. * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
  48. *
  49. * where n = 1 for forward-direction HS mode and n = 4 for reverse-
  50. * direction HS mode. There's only one setting and this function does
  51. * not parameterize on anything other that ui, so this code will
  52. * assumes that reverse-direction HS mode is supported and uses n = 4.
  53. */
  54. cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
  55. cfg->init = 100;
  56. cfg->lpx = 60000;
  57. cfg->ta_get = 5 * cfg->lpx;
  58. cfg->ta_go = 4 * cfg->lpx;
  59. cfg->ta_sure = 2 * cfg->lpx;
  60. cfg->wakeup = 1000;
  61. cfg->hs_clk_rate = hs_clk_rate;
  62. cfg->lanes = lanes;
  63. return 0;
  64. }
  65. /*
  66. * Validate D-PHY configuration according to MIPI D-PHY specification
  67. * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
  68. */
  69. int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
  70. {
  71. unsigned long long ui;
  72. if (!cfg)
  73. return -EINVAL;
  74. ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
  75. do_div(ui, cfg->hs_clk_rate);
  76. if (cfg->clk_miss > 60000)
  77. return -EINVAL;
  78. if (cfg->clk_post < (60000 + 52 * ui))
  79. return -EINVAL;
  80. if (cfg->clk_pre < 8000)
  81. return -EINVAL;
  82. if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
  83. return -EINVAL;
  84. if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
  85. return -EINVAL;
  86. if (cfg->clk_term_en > 38000)
  87. return -EINVAL;
  88. if (cfg->clk_trail < 60000)
  89. return -EINVAL;
  90. if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
  91. return -EINVAL;
  92. if (cfg->d_term_en > (35000 + 4 * ui))
  93. return -EINVAL;
  94. if (cfg->eot > (105000 + 12 * ui))
  95. return -EINVAL;
  96. if (cfg->hs_exit < 100000)
  97. return -EINVAL;
  98. if (cfg->hs_prepare < (40000 + 4 * ui) ||
  99. cfg->hs_prepare > (85000 + 6 * ui))
  100. return -EINVAL;
  101. if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
  102. return -EINVAL;
  103. if ((cfg->hs_settle < (85000 + 6 * ui)) ||
  104. (cfg->hs_settle > (145000 + 10 * ui)))
  105. return -EINVAL;
  106. if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
  107. return -EINVAL;
  108. if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
  109. return -EINVAL;
  110. if (cfg->init < 100)
  111. return -EINVAL;
  112. if (cfg->lpx < 50000)
  113. return -EINVAL;
  114. if (cfg->ta_get != (5 * cfg->lpx))
  115. return -EINVAL;
  116. if (cfg->ta_go != (4 * cfg->lpx))
  117. return -EINVAL;
  118. if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
  119. return -EINVAL;
  120. if (cfg->wakeup < 1000)
  121. return -EINVAL;
  122. return 0;
  123. }