pcie-cadence-ep.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019
  4. * Written by Ramon Fried <ramon.fried@gmail.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <pci_ep.h>
  10. #include <asm/global_data.h>
  11. #include <linux/sizes.h>
  12. #include <linux/log2.h>
  13. #include "pcie-cadence.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. static int cdns_write_header(struct udevice *dev, uint fn,
  16. struct pci_ep_header *hdr)
  17. {
  18. struct cdns_pcie *pcie = dev_get_priv(dev);
  19. cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
  20. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
  21. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
  22. hdr->progif_code);
  23. cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
  24. hdr->subclass_code |
  25. hdr->baseclass_code << 8);
  26. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
  27. hdr->cache_line_size);
  28. cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
  29. hdr->subsys_id);
  30. cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
  31. hdr->interrupt_pin);
  32. /*
  33. * Vendor ID can only be modified from function 0, all other functions
  34. * use the same vendor ID as function 0.
  35. */
  36. if (fn == 0) {
  37. /* Update the vendor IDs. */
  38. u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
  39. CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
  40. cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
  41. }
  42. return 0;
  43. }
  44. static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
  45. {
  46. struct cdns_pcie *pcie = dev_get_priv(dev);
  47. dma_addr_t bar_phys = ep_bar->phys_addr;
  48. enum pci_barno bar = ep_bar->barno;
  49. int flags = ep_bar->flags;
  50. u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
  51. u64 sz;
  52. /* BAR size is 2^(aperture + 7) */
  53. sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
  54. /*
  55. * roundup_pow_of_two() returns an unsigned long, which is not suited
  56. * for 64bit values.
  57. */
  58. sz = 1ULL << fls64(sz - 1);
  59. aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
  60. if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
  61. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
  62. } else {
  63. bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
  64. bool is_64bits = (sz > SZ_2G) |
  65. !!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
  66. if (is_64bits && (bar & 1))
  67. return -EINVAL;
  68. if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
  69. ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
  70. if (is_64bits && is_prefetch)
  71. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
  72. else if (is_prefetch)
  73. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
  74. else if (is_64bits)
  75. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
  76. else
  77. ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
  78. }
  79. addr0 = lower_32_bits(bar_phys);
  80. addr1 = upper_32_bits(bar_phys);
  81. cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
  82. addr0);
  83. cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
  84. addr1);
  85. if (bar < BAR_4) {
  86. reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
  87. b = bar;
  88. } else {
  89. reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
  90. b = bar - BAR_4;
  91. }
  92. cfg = cdns_pcie_readl(pcie, reg);
  93. cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
  94. CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
  95. cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
  96. CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
  97. cdns_pcie_writel(pcie, reg, cfg);
  98. return 0;
  99. }
  100. static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
  101. {
  102. struct cdns_pcie *pcie = dev_get_priv(dev);
  103. u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
  104. /*
  105. * Set the Multiple Message Capable bitfield into the Message Control
  106. * register.
  107. */
  108. u16 flags;
  109. flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
  110. flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
  111. flags |= PCI_MSI_FLAGS_64BIT;
  112. flags &= ~PCI_MSI_FLAGS_MASKBIT;
  113. cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
  114. return 0;
  115. }
  116. static struct pci_ep_ops cdns_pci_ep_ops = {
  117. .write_header = cdns_write_header,
  118. .set_bar = cdns_set_bar,
  119. .set_msi = cdns_set_msi,
  120. };
  121. static int cdns_pci_ep_probe(struct udevice *dev)
  122. {
  123. struct cdns_pcie *pdata = dev_get_priv(dev);
  124. pdata->reg_base = dev_read_addr_ptr(dev);
  125. if (!pdata->reg_base)
  126. return -ENOMEM;
  127. pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  128. "max-functions", 1);
  129. pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  130. "cdns,max-outbound-regions", 8);
  131. return 0;
  132. }
  133. static int cdns_pci_ep_remove(struct udevice *dev)
  134. {
  135. return 0;
  136. }
  137. const struct udevice_id cadence_pci_ep_of_match[] = {
  138. { .compatible = "cdns,cdns-pcie-ep" },
  139. { }
  140. };
  141. U_BOOT_DRIVER(cdns_pcie) = {
  142. .name = "cdns,pcie-ep",
  143. .id = UCLASS_PCI_EP,
  144. .of_match = cadence_pci_ep_of_match,
  145. .ops = &cdns_pci_ep_ops,
  146. .probe = cdns_pci_ep_probe,
  147. .remove = cdns_pci_ep_remove,
  148. .priv_auto = sizeof(struct cdns_pcie),
  149. };