pcie_starfive.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Starfive PLDA PCIe host controller driver
  4. *
  5. * Copyright (c) 2023 Starfive, Inc.
  6. * Author: Mason Huo <mason.huo@starfivetech.com>
  7. *
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <asm/global_data.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/pinctrl.h>
  15. #include <generic-phy.h>
  16. #include <pci.h>
  17. #include <power-domain.h>
  18. #include <power/regulator.h>
  19. #include <regmap.h>
  20. #include <reset.h>
  21. #include <syscon.h>
  22. #include <asm/io.h>
  23. #include <asm-generic/gpio.h>
  24. #include <linux/delay.h>
  25. #include <linux/iopoll.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define GEN_SETTINGS 0x80
  28. #define PCIE_PCI_IDS 0x9C
  29. #define PCIE_WINROM 0xFC
  30. #define PMSG_SUPPORT_RX 0x3F0
  31. #define PCI_MISC 0xB4
  32. #define PLDA_EP_ENABLE 0
  33. #define PLDA_RP_ENABLE 1
  34. #define IDS_REVISION_ID 0x02
  35. #define IDS_PCI_TO_PCI_BRIDGE 0x060400
  36. #define IDS_CLASS_CODE_SHIFT 8
  37. #define PLDA_LINK_UP 1
  38. #define PLDA_LINK_DOWN 0
  39. #define PLDA_DATA_LINK_ACTIVE BIT(5)
  40. #define PREF_MEM_WIN_64_SUPPORT BIT(3)
  41. #define PMSG_LTR_SUPPORT BIT(2)
  42. #define PLDA_FUNCTION_DIS BIT(15)
  43. #define PLDA_FUNC_NUM 4
  44. #define PLDA_PHY_FUNC_SHIFT 9
  45. #define XR3PCI_ATR_AXI4_SLV0 0x800
  46. #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
  47. #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
  48. #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
  49. #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
  50. #define XR3PCI_ATR_TRSL_PARAM 0x10
  51. #define XR3PCI_ATR_TABLE_OFFSET 0x20
  52. #define XR3PCI_ATR_MAX_TABLE_NUM 8
  53. #define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
  54. #define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
  55. #define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
  56. #define XR3_PCI_ECAM_SIZE 28
  57. #define XR3PCI_ATR_TRSL_DIR BIT(22)
  58. /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
  59. #define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
  60. #define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
  61. #define ECAM_BUS_SHIFT 20
  62. #define ECAM_DEV_SHIFT 15
  63. #define ECAM_FUNC_SHIFT 12
  64. /* Secondary bus number offset in config space */
  65. #define PCI_SECONDARY_BUS 0x19
  66. /* system control */
  67. #define STG_SYSCON_K_RP_NEP_SHIFT 0x8
  68. #define STG_SYSCON_K_RP_NEP_MASK 0x100
  69. #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
  70. #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8
  71. #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
  72. #define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0
  73. #define STG_SYSCON_CLKREQ_SHIFT 0x16
  74. #define STG_SYSCON_CLKREQ_MASK 0x400000
  75. #define STG_SYSCON_CKREF_SRC_SHIFT 0x12
  76. #define STG_SYSCON_CKREF_SRC_MASK 0xC0000
  77. struct starfive_pcie {
  78. struct udevice *dev;
  79. void __iomem *reg_base;
  80. void __iomem *cfg_base;
  81. struct regmap *regmap;
  82. u32 stg_arfun;
  83. u32 stg_awfun;
  84. u32 stg_rp_nep;
  85. u32 stg_lnksta;
  86. struct clk_bulk clks;
  87. struct reset_ctl_bulk rsts;
  88. int atr_table_num;
  89. int first_busno;
  90. struct gpio_desc *power_gpio;
  91. struct gpio_desc *reset_gpio;
  92. };
  93. static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
  94. {
  95. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  96. return 0;
  97. if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
  98. return 0;
  99. return 1;
  100. }
  101. static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset, int first_busno)
  102. {
  103. unsigned int bus = PCI_BUS(bdf) - first_busno;
  104. unsigned int dev = PCI_DEV(bdf);
  105. unsigned int func = PCI_FUNC(bdf);
  106. return (bus << ECAM_BUS_SHIFT) | (dev << ECAM_DEV_SHIFT) |
  107. (func << ECAM_FUNC_SHIFT) | (offset & ~0x3);
  108. }
  109. static bool plda_pcie_hide_rc_bar(pci_dev_t bdf, int offset, int first_busno)
  110. {
  111. if ((PCI_BUS(bdf) == first_busno) &&
  112. (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
  113. return true;
  114. return false;
  115. }
  116. static int starfive_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
  117. uint offset, ulong *valuep,
  118. enum pci_size_t size)
  119. {
  120. void __iomem *addr;
  121. ulong value;
  122. struct starfive_pcie *priv = dev_get_priv(udev);
  123. int where = starfive_pcie_off_conf(bdf, offset, priv->first_busno);
  124. if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
  125. pr_debug("Out of range\n");
  126. *valuep = pci_get_ff(size);
  127. return 0;
  128. }
  129. addr = priv->cfg_base;
  130. addr += where;
  131. if (!addr)
  132. return -1;
  133. /* Make sure the LAST TLP is finished, before reading vendor ID. */
  134. if (offset == PCI_VENDOR_ID)
  135. mdelay(20);
  136. value = readl(addr);
  137. *valuep = pci_conv_32_to_size(value, offset, size);
  138. return 0;
  139. }
  140. int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
  141. uint offset, ulong value,
  142. enum pci_size_t size)
  143. {
  144. void __iomem *addr;
  145. ulong old;
  146. struct starfive_pcie *priv = dev_get_priv(udev);
  147. int where = starfive_pcie_off_conf(bdf, offset, priv->first_busno);
  148. if (plda_pcie_hide_rc_bar(bdf, offset, priv->first_busno))
  149. return -1;
  150. if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
  151. pr_debug("Out of range\n");
  152. return 0;
  153. }
  154. addr = priv->cfg_base;
  155. addr += where;
  156. if (!addr)
  157. return -1;
  158. old = readl(addr);
  159. value = pci_conv_size_to_32(old, value, offset, size);
  160. writel(value, addr);
  161. return 0;
  162. }
  163. static void starfive_pcie_set_atr_entry(struct starfive_pcie *priv, phys_addr_t src_addr,
  164. phys_addr_t trsl_addr, size_t window_size,
  165. int trsl_param)
  166. {
  167. void __iomem *base =
  168. priv->reg_base + XR3PCI_ATR_AXI4_SLV0;
  169. /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
  170. if (priv->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM)
  171. priv->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1;
  172. base += XR3PCI_ATR_TABLE_OFFSET * priv->atr_table_num;
  173. priv->atr_table_num++;
  174. /* X3PCI_ATR_SRC_ADDR_LOW:
  175. * - bit 0: enable entry,
  176. * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
  177. * - bits 7-11: reserved
  178. * - bits 12-31: start of source address
  179. */
  180. writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
  181. (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
  182. base + XR3PCI_ATR_SRC_ADDR_LOW);
  183. writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
  184. writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
  185. base + XR3PCI_ATR_TRSL_ADDR_LOW);
  186. writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
  187. writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
  188. dev_info(priv->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
  189. src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
  190. trsl_addr, (u64)window_size, trsl_param);
  191. }
  192. static int starfive_pcie_atr_init(struct starfive_pcie *priv)
  193. {
  194. struct udevice *ctlr = pci_get_controller(priv->dev);
  195. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  196. int i;
  197. /* As the two host bridges in JH7110 soc have the same default
  198. * address translation table, this cause the second root port can't
  199. * access it's host bridge config space correctly.
  200. * To workaround, config the ATR of host bridge config space by SW.
  201. */
  202. starfive_pcie_set_atr_entry(priv,
  203. (phys_addr_t)priv->cfg_base,
  204. 0,
  205. 1 << XR3_PCI_ECAM_SIZE,
  206. XR3PCI_ATR_TRSLID_PCIE_CONFIG);
  207. for (i = 0; i < hose->region_count; i++) {
  208. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  209. continue;
  210. /* Only support identity mappings. */
  211. if (hose->regions[i].bus_start !=
  212. hose->regions[i].phys_start)
  213. return -EINVAL;
  214. starfive_pcie_set_atr_entry(priv,
  215. hose->regions[i].phys_start,
  216. hose->regions[i].bus_start,
  217. hose->regions[i].size,
  218. XR3PCI_ATR_TRSLID_PCIE_MEMORY);
  219. }
  220. return 0;
  221. }
  222. static int starfive_pcie_get_syscon(struct udevice *dev)
  223. {
  224. struct starfive_pcie *priv = dev_get_priv(dev);
  225. struct udevice *syscon;
  226. struct ofnode_phandle_args syscfg_phandle;
  227. u32 cells[5];
  228. int ret;
  229. /* get corresponding syscon phandle */
  230. ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
  231. &syscfg_phandle);
  232. if (ret < 0) {
  233. dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
  234. return ret;
  235. }
  236. ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
  237. &syscon);
  238. if (ret) {
  239. dev_err(dev, "Unable to find syscon device (%d)\n", ret);
  240. return ret;
  241. }
  242. priv->regmap = syscon_get_regmap(syscon);
  243. if (!priv->regmap) {
  244. dev_err(dev, "Unable to find regmap\n");
  245. return -ENODEV;
  246. }
  247. /* get syscon register offset */
  248. ret = dev_read_u32_array(dev, "starfive,stg-syscon",
  249. cells, ARRAY_SIZE(cells));
  250. if (ret) {
  251. dev_err(dev, "Get syscon register count err %d\n", ret);
  252. return -EINVAL;
  253. }
  254. dev_dbg(dev, "Get syscon values: %x, %x, %x, %x\n",
  255. cells[1], cells[2], cells[3], cells[4]);
  256. priv->stg_arfun = cells[1];
  257. priv->stg_awfun = cells[2];
  258. priv->stg_rp_nep = cells[3];
  259. priv->stg_lnksta = cells[4];
  260. return 0;
  261. }
  262. static int starfive_pcie_parse_dt(struct udevice *dev)
  263. {
  264. struct starfive_pcie *priv = dev_get_priv(dev);
  265. int ret;
  266. priv->reg_base = (void *)dev_read_addr_name(dev, "reg");
  267. if (priv->reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
  268. dev_err(dev, "Missing required reg address range\n");
  269. return -EINVAL;
  270. }
  271. priv->cfg_base = (void *)dev_read_addr_name(dev, "config");
  272. if (priv->cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
  273. dev_err(dev, "Missing required config address range");
  274. return -EINVAL;
  275. }
  276. ret = starfive_pcie_get_syscon(dev);
  277. if (ret) {
  278. dev_err(dev, "Can't get syscon: %d\n", ret);
  279. return ret;
  280. }
  281. ret = reset_get_bulk(dev, &priv->rsts);
  282. if (ret) {
  283. dev_err(dev, "Can't get reset: %d\n", ret);
  284. return ret;
  285. }
  286. ret = clk_get_bulk(dev, &priv->clks);
  287. if (ret) {
  288. dev_err(dev, "Can't get clock: %d\n", ret);
  289. return ret;
  290. }
  291. return 0;
  292. }
  293. static int starfive_pcie_init_port(struct udevice *dev)
  294. {
  295. int ret, i;
  296. unsigned int value;
  297. struct starfive_pcie *priv = dev_get_priv(dev);
  298. ret = clk_enable_bulk(&priv->clks);
  299. if (ret) {
  300. dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
  301. return ret;
  302. }
  303. ret = reset_deassert_bulk(&priv->rsts);
  304. if (ret) {
  305. dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
  306. goto err_deassert_clk;
  307. }
  308. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_DEVKITS)
  309. ret = pinctrl_select_state(dev, "power-active");
  310. if (ret) {
  311. priv->power_gpio =
  312. devm_gpiod_get_optional(dev, "power", GPIOD_IS_OUT);
  313. if (IS_ERR(priv->power_gpio)) {
  314. dev_err(dev, "Get power-acvtive gpio failed: %d\n", ret);
  315. goto err_deassert_reset;
  316. }
  317. dm_gpio_set_value(priv->power_gpio, 1);
  318. }
  319. #endif
  320. ret = pinctrl_select_state(dev, "perst-active");
  321. if (ret) {
  322. priv->reset_gpio =
  323. devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT);
  324. if (IS_ERR(priv->reset_gpio)) {
  325. dev_err(dev, "Set perst-active gpio failed: %d\n", ret);
  326. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_DEVKITS)
  327. goto err_release_power_pin;
  328. #else
  329. goto err_deassert_reset;
  330. #endif
  331. }
  332. dm_gpio_set_value(priv->reset_gpio, 1);
  333. }
  334. /* Disable physical functions except #0 */
  335. for (i = 1; i < PLDA_FUNC_NUM; i++) {
  336. regmap_update_bits(priv->regmap,
  337. priv->stg_arfun,
  338. STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
  339. (i << PLDA_PHY_FUNC_SHIFT) <<
  340. STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
  341. regmap_update_bits(priv->regmap,
  342. priv->stg_awfun,
  343. STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
  344. (i << PLDA_PHY_FUNC_SHIFT) <<
  345. STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
  346. value = readl(priv->reg_base + PCI_MISC);
  347. value |= PLDA_FUNCTION_DIS;
  348. writel(value, priv->reg_base + PCI_MISC);
  349. }
  350. regmap_update_bits(priv->regmap,
  351. priv->stg_arfun,
  352. STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
  353. 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
  354. regmap_update_bits(priv->regmap,
  355. priv->stg_awfun,
  356. STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
  357. 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
  358. /* Enable root port*/
  359. value = readl(priv->reg_base + GEN_SETTINGS);
  360. value |= PLDA_RP_ENABLE;
  361. writel(value, priv->reg_base + GEN_SETTINGS);
  362. /* PCIe PCI Standard Configuration Identification Settings. */
  363. value = (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID;
  364. writel(value, priv->reg_base + PCIE_PCI_IDS);
  365. /* The LTR message forwarding of PCIe Message Reception was set by core
  366. * as default, but the forward id & addr are also need to be reset.
  367. * If we do not disable LTR message forwarding here, or set a legal
  368. * forwarding address, the kernel will get stuck after this driver probe.
  369. * To workaround, disable the LTR message forwarding support on
  370. * PCIe Message Reception.
  371. */
  372. value = readl(priv->reg_base + PMSG_SUPPORT_RX);
  373. value &= ~PMSG_LTR_SUPPORT;
  374. writel(value, priv->reg_base + PMSG_SUPPORT_RX);
  375. /* Prefetchable memory window 64-bit addressing support */
  376. value = readl(priv->reg_base + PCIE_WINROM);
  377. value |= PREF_MEM_WIN_64_SUPPORT;
  378. writel(value, priv->reg_base + PCIE_WINROM);
  379. starfive_pcie_atr_init(priv);
  380. /* Ensure that PERST has been asserted for at least 300 ms */
  381. mdelay(100);
  382. ret = pinctrl_select_state(dev, "perst-default");
  383. if (ret) {
  384. if (priv->reset_gpio) {
  385. dm_gpio_set_value(priv->reset_gpio, 0);
  386. return 0;
  387. } else
  388. dev_err(dev, "Set perst-default pinctrl failed: %d\n", ret);
  389. return ret;
  390. }
  391. return 0;
  392. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB) || CONFIG_IS_ENABLED(TARGET_STARFIVE_DEVKITS)
  393. err_release_power_pin:
  394. pinctrl_select_state(dev, "power-default");
  395. #endif
  396. err_deassert_reset:
  397. reset_assert_bulk(&priv->rsts);
  398. err_deassert_clk:
  399. clk_disable_bulk(&priv->clks);
  400. return ret;
  401. }
  402. static int plda_pcie_is_link_up(struct udevice *dev)
  403. {
  404. struct starfive_pcie *priv = dev_get_priv(dev);
  405. int ret;
  406. u32 stg_reg_val;
  407. /* 100ms timeout value should be enough for Gen1/2 training */
  408. ret = regmap_read_poll_timeout(priv->regmap,
  409. priv->stg_lnksta,
  410. stg_reg_val,
  411. stg_reg_val & PLDA_DATA_LINK_ACTIVE,
  412. 10 * 1000, 100);
  413. /* If the link is down (no device in slot), then exit. */
  414. if (ret == -ETIMEDOUT) {
  415. dev_err(dev, "Port link down.\n");
  416. return PLDA_LINK_DOWN;
  417. } else if (ret == 0) {
  418. dev_err(dev, "Port link up.\n");
  419. return PLDA_LINK_UP;
  420. }
  421. dev_warn(dev, "Read stg_linksta failed.\n");
  422. return ret;
  423. }
  424. static int starfive_pcie_probe(struct udevice *dev)
  425. {
  426. struct starfive_pcie *priv = dev_get_priv(dev);
  427. int ret;
  428. priv->atr_table_num = 0;
  429. priv->dev = dev;
  430. priv->first_busno = dev_seq(dev);
  431. ret = starfive_pcie_parse_dt(dev);
  432. if (ret)
  433. return ret;
  434. regmap_update_bits(priv->regmap,
  435. priv->stg_rp_nep,
  436. STG_SYSCON_K_RP_NEP_MASK,
  437. 1 << STG_SYSCON_K_RP_NEP_SHIFT);
  438. regmap_update_bits(priv->regmap,
  439. priv->stg_awfun,
  440. STG_SYSCON_CKREF_SRC_MASK,
  441. 2 << STG_SYSCON_CKREF_SRC_SHIFT);
  442. regmap_update_bits(priv->regmap,
  443. priv->stg_awfun,
  444. STG_SYSCON_CLKREQ_MASK,
  445. 1 << STG_SYSCON_CLKREQ_SHIFT);
  446. ret = starfive_pcie_init_port(dev);
  447. if (ret)
  448. return ret;
  449. if (plda_pcie_is_link_up(dev) == PLDA_LINK_UP) {
  450. /* As the requirement in PCIe base spec r6.0, system (<=5GT/s) must
  451. * wait a minimum of 100 ms following exit from a conventional reset
  452. * before sending a configuration request to the device.
  453. */
  454. mdelay(100);
  455. }
  456. dev_err(dev, "Starfive PCIe bus probed.\n");
  457. return 0;
  458. }
  459. static const struct dm_pci_ops starfive_pcie_ops = {
  460. .read_config = starfive_pcie_config_read,
  461. .write_config = starfive_pcie_config_write,
  462. };
  463. static const struct udevice_id starfive_pcie_ids[] = {
  464. { .compatible = "starfive,jh7110-pcie" },
  465. { }
  466. };
  467. U_BOOT_DRIVER(starfive_pcie_drv) = {
  468. .name = "starfive_pcie",
  469. .id = UCLASS_PCI,
  470. .of_match = starfive_pcie_ids,
  471. .ops = &starfive_pcie_ops,
  472. .probe = starfive_pcie_probe,
  473. .priv_auto = sizeof(struct starfive_pcie),
  474. };