pcie_layerscape_gen4.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2019 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. */
  8. #ifndef _PCIE_LAYERSCAPE_GEN4_H_
  9. #define _PCIE_LAYERSCAPE_GEN4_H_
  10. #include <pci.h>
  11. #include <linux/bitops.h>
  12. #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
  13. #define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL)
  14. #endif
  15. #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
  16. #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
  17. #endif
  18. #define PCIE_PF_NUM 2
  19. #define PCIE_VF_NUM 32
  20. #define LS_G4_PF0 0
  21. #define LS_G4_PF1 1
  22. #define PF_BAR_NUM 4
  23. #define VF_BAR_NUM 4
  24. #define PCIE_BAR_SIZE (8 * 1024) /* 8K */
  25. #define PCIE_BAR0_SIZE PCIE_BAR_SIZE
  26. #define PCIE_BAR1_SIZE PCIE_BAR_SIZE
  27. #define PCIE_BAR2_SIZE PCIE_BAR_SIZE
  28. #define PCIE_BAR4_SIZE PCIE_BAR_SIZE
  29. #define SIZE_1T (1024 * 1024 * 1024 * 1024ULL)
  30. /* GPEX CSR */
  31. #define GPEX_CLASSCODE 0x474
  32. #define GPEX_CLASSCODE_SHIFT 16
  33. #define GPEX_CLASSCODE_MASK 0xffff
  34. #define GPEX_CFG_READY 0x4b0
  35. #define PCIE_CONFIG_READY BIT(0)
  36. #define GPEX_BAR_ENABLE 0x4d4
  37. #define GPEX_BAR_SIZE_LDW 0x4d8
  38. #define GPEX_BAR_SIZE_UDW 0x4dC
  39. #define GPEX_BAR_SELECT 0x4e0
  40. #define BAR_POS(bar, pf, vf_bar) \
  41. ((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
  42. #define GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf) (0x644 + (pf) * 4)
  43. #define TTL_VF_MASK 0xffff
  44. #define TTL_VF_SHIFT 16
  45. #define INI_VF_MASK 0xffff
  46. #define INI_VF_SHIFT 0
  47. #define GPEX_SRIOV_VF_OFFSET_STRIDE(pf) (0x704 + (pf) * 4)
  48. /* PAB CSR */
  49. #define PAB_CTRL 0x808
  50. #define PAB_CTRL_APIO_EN BIT(0)
  51. #define PAB_CTRL_PPIO_EN BIT(1)
  52. #define PAB_CTRL_MAX_BRST_LEN_SHIFT 4
  53. #define PAB_CTRL_MAX_BRST_LEN_MASK 0x3
  54. #define PAB_CTRL_PAGE_SEL_SHIFT 13
  55. #define PAB_CTRL_PAGE_SEL_MASK 0x3f
  56. #define PAB_CTRL_FUNC_SEL_SHIFT 19
  57. #define PAB_CTRL_FUNC_SEL_MASK 0x1ff
  58. #define PAB_RST_CTRL 0x820
  59. #define PAB_BR_STAT 0x80c
  60. /* AXI PIO Engines */
  61. #define PAB_AXI_PIO_CTRL(idx) (0x840 + 0x10 * (idx))
  62. #define APIO_EN BIT(0)
  63. #define MEM_WIN_EN BIT(1)
  64. #define IO_WIN_EN BIT(2)
  65. #define CFG_WIN_EN BIT(3)
  66. #define PAB_AXI_PIO_STAT(idx) (0x844 + 0x10 * (idx))
  67. #define PAB_AXI_PIO_SL_CMD_STAT(idx) (0x848 + 0x10 * (idx))
  68. #define PAB_AXI_PIO_SL_ADDR_STAT(idx) (0x84c + 0x10 * (idx))
  69. #define PAB_AXI_PIO_SL_EXT_ADDR_STAT(idx) (0xb8a0 + 0x4 * (idx))
  70. /* PEX PIO Engines */
  71. #define PAB_PEX_PIO_CTRL(idx) (0x8c0 + 0x10 * (idx))
  72. #define PPIO_EN BIT(0)
  73. #define PAB_PEX_PIO_STAT(idx) (0x8c4 + 0x10 * (idx))
  74. #define PAB_PEX_PIO_MT_STAT(idx) (0x8c8 + 0x10 * (idx))
  75. #define INDIRECT_ADDR_BNDRY 0xc00
  76. #define PAGE_IDX_SHIFT 10
  77. #define PAGE_ADDR_MASK 0x3ff
  78. #define OFFSET_TO_PAGE_IDX(off) \
  79. (((off) >> PAGE_IDX_SHIFT) & PAB_CTRL_PAGE_SEL_MASK)
  80. #define OFFSET_TO_PAGE_ADDR(off) \
  81. (((off) & PAGE_ADDR_MASK) | INDIRECT_ADDR_BNDRY)
  82. /* APIO WINs */
  83. #define PAB_AXI_AMAP_CTRL(idx) (0xba0 + 0x10 * (idx))
  84. #define PAB_EXT_AXI_AMAP_SIZE(idx) (0xbaf0 + 0x4 * (idx))
  85. #define PAB_AXI_AMAP_AXI_WIN(idx) (0xba4 + 0x10 * (idx))
  86. #define PAB_EXT_AXI_AMAP_AXI_WIN(idx) (0x80a0 + 0x4 * (idx))
  87. #define PAB_AXI_AMAP_PEX_WIN_L(idx) (0xba8 + 0x10 * (idx))
  88. #define PAB_AXI_AMAP_PEX_WIN_H(idx) (0xbac + 0x10 * (idx))
  89. #define PAB_AXI_AMAP_PCI_HDR_PARAM(idx) (0x5ba0 + 0x4 * (idx))
  90. #define FUNC_NUM_PCIE_MASK GENMASK(7, 0)
  91. #define AXI_AMAP_CTRL_EN BIT(0)
  92. #define AXI_AMAP_CTRL_TYPE_SHIFT 1
  93. #define AXI_AMAP_CTRL_TYPE_MASK 0x3
  94. #define AXI_AMAP_CTRL_SIZE_SHIFT 10
  95. #define AXI_AMAP_CTRL_SIZE_MASK 0x3fffff
  96. #define PAB_TARGET_BUS(x) (((x) & 0xff) << 24)
  97. #define PAB_TARGET_DEV(x) (((x) & 0x1f) << 19)
  98. #define PAB_TARGET_FUNC(x) (((x) & 0x7) << 16)
  99. #define PAB_AXI_TYPE_CFG 0x00
  100. #define PAB_AXI_TYPE_IO 0x01
  101. #define PAB_AXI_TYPE_MEM 0x02
  102. #define PAB_AXI_TYPE_ATOM 0x03
  103. #define PAB_WINS_NUM 256
  104. /* PPIO WINs RC mode */
  105. #define PAB_PEX_AMAP_CTRL(idx) (0x4ba0 + 0x10 * (idx))
  106. #define PAB_EXT_PEX_AMAP_SIZE(idx) (0xbef0 + 0x04 * (idx))
  107. #define PAB_PEX_AMAP_AXI_WIN(idx) (0x4ba4 + 0x10 * (idx))
  108. #define PAB_EXT_PEX_AMAP_AXI_WIN(idx) (0xb4a0 + 0x04 * (idx))
  109. #define PAB_PEX_AMAP_PEX_WIN_L(idx) (0x4ba8 + 0x10 * (idx))
  110. #define PAB_PEX_AMAP_PEX_WIN_H(idx) (0x4bac + 0x10 * (idx))
  111. #define IB_TYPE_MEM_F 0x2
  112. #define IB_TYPE_MEM_NF 0x3
  113. #define PEX_AMAP_CTRL_TYPE_SHIFT 0x1
  114. #define PEX_AMAP_CTRL_EN_SHIFT 0x0
  115. #define PEX_AMAP_CTRL_TYPE_MASK 0x3
  116. #define PEX_AMAP_CTRL_EN_MASK 0x1
  117. /* PPIO WINs EP mode */
  118. #define PAB_PEX_BAR_AMAP(pf, bar) \
  119. (0x1ba0 + 0x20 * (pf) + 4 * (bar))
  120. #define BAR_AMAP_EN BIT(0)
  121. #define PAB_EXT_PEX_BAR_AMAP(pf, bar) \
  122. (0x84a0 + 0x20 * (pf) + 4 * (bar))
  123. /* CCSR registers */
  124. #define PCIE_LINK_CTRL_STA 0x5c
  125. #define PCIE_LINK_SPEED_SHIFT 16
  126. #define PCIE_LINK_SPEED_MASK 0x0f
  127. #define PCIE_LINK_WIDTH_SHIFT 20
  128. #define PCIE_LINK_WIDTH_MASK 0x3f
  129. #define PCIE_SRIOV_CAPABILITY 0x2a0
  130. #define PCIE_SRIOV_VF_OFFSET_STRIDE 0x2b4
  131. /* LUT registers */
  132. #define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
  133. #define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
  134. #define PCIE_LUT_ENABLE BIT(31)
  135. #define PCIE_LUT_ENTRY_COUNT 32
  136. /* PF control registers */
  137. #define PCIE_LTSSM_STA 0x7fc
  138. #define LTSSM_STATE_MASK 0x7f
  139. #define LTSSM_PCIE_L0 0x2d /* L0 state */
  140. #define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
  141. #define PCIE_SYS_BASE_ADDR 0x3400000
  142. #define PCIE_CCSR_SIZE 0x0100000
  143. struct ls_pcie_g4 {
  144. int idx;
  145. struct list_head list;
  146. struct udevice *bus;
  147. struct fdt_resource ccsr_res;
  148. struct fdt_resource cfg_res;
  149. struct fdt_resource lut_res;
  150. struct fdt_resource pf_ctrl_res;
  151. void __iomem *ccsr;
  152. void __iomem *cfg;
  153. void __iomem *lut;
  154. void __iomem *pf_ctrl;
  155. bool big_endian;
  156. bool enabled;
  157. int next_lut_index;
  158. struct pci_controller hose;
  159. int stream_id_cur;
  160. int mode;
  161. int sriov_support;
  162. };
  163. extern struct list_head ls_pcie_g4_list;
  164. static inline void lut_writel(struct ls_pcie_g4 *pcie, unsigned int value,
  165. unsigned int offset)
  166. {
  167. if (pcie->big_endian)
  168. out_be32(pcie->lut + offset, value);
  169. else
  170. out_le32(pcie->lut + offset, value);
  171. }
  172. static inline u32 lut_readl(struct ls_pcie_g4 *pcie, unsigned int offset)
  173. {
  174. if (pcie->big_endian)
  175. return in_be32(pcie->lut + offset);
  176. else
  177. return in_le32(pcie->lut + offset);
  178. }
  179. static inline void ccsr_set_page(struct ls_pcie_g4 *pcie, u8 pg_idx)
  180. {
  181. u32 val;
  182. val = in_le32(pcie->ccsr + PAB_CTRL);
  183. val &= ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT);
  184. val |= (pg_idx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT;
  185. out_le32(pcie->ccsr + PAB_CTRL, val);
  186. }
  187. static inline unsigned int ccsr_readl(struct ls_pcie_g4 *pcie, u32 offset)
  188. {
  189. if (offset < INDIRECT_ADDR_BNDRY) {
  190. ccsr_set_page(pcie, 0);
  191. return in_le32(pcie->ccsr + offset);
  192. }
  193. ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
  194. return in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset));
  195. }
  196. static inline void ccsr_writel(struct ls_pcie_g4 *pcie, u32 offset, u32 value)
  197. {
  198. if (offset < INDIRECT_ADDR_BNDRY) {
  199. ccsr_set_page(pcie, 0);
  200. out_le32(pcie->ccsr + offset, value);
  201. } else {
  202. ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
  203. out_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value);
  204. }
  205. }
  206. static inline unsigned int pf_ctrl_readl(struct ls_pcie_g4 *pcie, u32 offset)
  207. {
  208. if (pcie->big_endian)
  209. return in_be32(pcie->pf_ctrl + offset);
  210. else
  211. return in_le32(pcie->pf_ctrl + offset);
  212. }
  213. static inline void pf_ctrl_writel(struct ls_pcie_g4 *pcie, u32 offset,
  214. u32 value)
  215. {
  216. if (pcie->big_endian)
  217. out_be32(pcie->pf_ctrl + offset, value);
  218. else
  219. out_le32(pcie->pf_ctrl + offset, value);
  220. }
  221. #endif /* _PCIE_LAYERSCAPE_GEN4_H_ */