pcie_layerscape_fixup.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2020 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. * Layerscape PCIe driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <pci.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <asm/io.h>
  14. #include <errno.h>
  15. #ifdef CONFIG_OF_BOARD_SETUP
  16. #include <linux/libfdt.h>
  17. #include <fdt_support.h>
  18. #ifdef CONFIG_ARM
  19. #include <asm/arch/clock.h>
  20. #endif
  21. #include <malloc.h>
  22. #include <env.h>
  23. #include "pcie_layerscape.h"
  24. #include "pcie_layerscape_fixup_common.h"
  25. static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc)
  26. {
  27. int nodeoffset;
  28. uint svr;
  29. char *compat = NULL;
  30. /* find pci controller node */
  31. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  32. pcie_rc->dbi_res.start);
  33. if (nodeoffset < 0) {
  34. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  35. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  36. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  37. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  38. svr == SVR_LS2081A || svr == SVR_LS2041A)
  39. compat = "fsl,ls2088a-pcie";
  40. else
  41. compat = CONFIG_FSL_PCIE_COMPAT;
  42. nodeoffset =
  43. fdt_node_offset_by_compat_reg(blob, compat,
  44. pcie_rc->dbi_res.start);
  45. #endif
  46. }
  47. return nodeoffset;
  48. }
  49. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  50. /*
  51. * Return next available LUT index.
  52. */
  53. static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
  54. {
  55. if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  56. return pcie_rc->next_lut_index++;
  57. else
  58. return -ENOSPC; /* LUT is full */
  59. }
  60. static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
  61. unsigned int offset)
  62. {
  63. struct ls_pcie *pcie = pcie_rc->pcie;
  64. if (pcie->big_endian)
  65. out_be32(pcie->lut + offset, value);
  66. else
  67. out_le32(pcie->lut + offset, value);
  68. }
  69. /*
  70. * Program a single LUT entry
  71. */
  72. static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
  73. u32 devid, u32 streamid)
  74. {
  75. /* leave mask as all zeroes, want to match all bits */
  76. lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
  77. lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  78. }
  79. /*
  80. * An msi-map is a property to be added to the pci controller
  81. * node. It is a table, where each entry consists of 4 fields
  82. * e.g.:
  83. *
  84. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  85. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  86. */
  87. static void fdt_pcie_set_msi_map_entry_ls(void *blob,
  88. struct ls_pcie_rc *pcie_rc,
  89. u32 devid, u32 streamid)
  90. {
  91. u32 *prop;
  92. u32 phandle;
  93. int nodeoffset;
  94. uint svr;
  95. char *compat = NULL;
  96. struct ls_pcie *pcie = pcie_rc->pcie;
  97. /* find pci controller node */
  98. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  99. pcie_rc->dbi_res.start);
  100. if (nodeoffset < 0) {
  101. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  102. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  103. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  104. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  105. svr == SVR_LS2081A || svr == SVR_LS2041A)
  106. compat = "fsl,ls2088a-pcie";
  107. else
  108. compat = CONFIG_FSL_PCIE_COMPAT;
  109. if (compat)
  110. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  111. compat, pcie_rc->dbi_res.start);
  112. #endif
  113. if (nodeoffset < 0)
  114. return;
  115. }
  116. /* get phandle to MSI controller */
  117. prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
  118. if (prop == NULL) {
  119. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  120. __func__, pcie->idx);
  121. return;
  122. }
  123. phandle = fdt32_to_cpu(*prop);
  124. /* set one msi-map row */
  125. fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
  126. fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
  127. fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
  128. fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
  129. }
  130. /*
  131. * An iommu-map is a property to be added to the pci controller
  132. * node. It is a table, where each entry consists of 4 fields
  133. * e.g.:
  134. *
  135. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  136. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  137. */
  138. static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
  139. struct ls_pcie_rc *pcie_rc,
  140. u32 devid, u32 streamid)
  141. {
  142. u32 *prop;
  143. u32 iommu_map[4];
  144. int nodeoffset;
  145. int lenp;
  146. struct ls_pcie *pcie = pcie_rc->pcie;
  147. nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
  148. if (nodeoffset < 0)
  149. return;
  150. /* get phandle to iommu controller */
  151. prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
  152. if (prop == NULL) {
  153. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  154. __func__, pcie->idx);
  155. return;
  156. }
  157. /* set iommu-map row */
  158. iommu_map[0] = cpu_to_fdt32(devid);
  159. iommu_map[1] = *++prop;
  160. iommu_map[2] = cpu_to_fdt32(streamid);
  161. iommu_map[3] = cpu_to_fdt32(1);
  162. if (devid == 0) {
  163. fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
  164. iommu_map, 16);
  165. } else {
  166. fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
  167. }
  168. }
  169. static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf,
  170. struct ls_pcie_rc *pcie_rc)
  171. {
  172. int streamid, index;
  173. streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
  174. pcie_rc->pcie->idx);
  175. if (streamid < 0) {
  176. printf("ERROR: out of stream ids for BDF %d.%d.%d\n",
  177. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  178. return -ENOENT;
  179. }
  180. pcie_rc->stream_id_cur++;
  181. index = ls_pcie_next_lut_index(pcie_rc);
  182. if (index < 0) {
  183. printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n",
  184. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  185. return -ENOENT;
  186. }
  187. /* map PCI b.d.f to streamID in LUT */
  188. ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid);
  189. /* update msi-map in device tree */
  190. fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
  191. /* update iommu-map in device tree */
  192. fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid);
  193. return 0;
  194. }
  195. struct extra_iommu_entry {
  196. int action;
  197. pci_dev_t bdf;
  198. int num_vfs;
  199. bool noari;
  200. };
  201. #define EXTRA_IOMMU_ENTRY_HOTPLUG 1
  202. #define EXTRA_IOMMU_ENTRY_VFS 2
  203. static struct extra_iommu_entry *get_extra_iommu_ents(void *blob,
  204. int nodeoffset,
  205. phys_addr_t addr,
  206. int *cnt)
  207. {
  208. const char *s, *p, *tok;
  209. struct extra_iommu_entry *entries;
  210. int i = 0, b, d, f;
  211. /*
  212. * Retrieve extra IOMMU configuration from env var or from device tree.
  213. * Env var is given priority.
  214. */
  215. s = env_get("pci_iommu_extra");
  216. if (!s) {
  217. s = fdt_getprop(blob, nodeoffset, "pci-iommu-extra", NULL);
  218. } else {
  219. phys_addr_t pci_base;
  220. char *endp;
  221. /*
  222. * In env var case the config string has "pci@0x..." in
  223. * addition. Parse this part and match it by address against
  224. * the input pci controller's registers base address.
  225. */
  226. tok = s;
  227. p = strchrnul(s + 1, ',');
  228. s = NULL;
  229. do {
  230. if (!strncmp(tok, "pci", 3)) {
  231. pci_base = simple_strtoul(tok + 4, &endp, 0);
  232. if (pci_base == addr) {
  233. s = endp + 1;
  234. break;
  235. }
  236. }
  237. p = strchrnul(p + 1, ',');
  238. tok = p + 1;
  239. } while (*p);
  240. }
  241. /*
  242. * If no env var or device tree property found or pci register base
  243. * address mismatches, bail out
  244. */
  245. if (!s)
  246. return NULL;
  247. /*
  248. * In order to find how many action entries to allocate, count number
  249. * of actions by interating through the pairs of bdfs and actions.
  250. */
  251. *cnt = 0;
  252. p = s;
  253. while (*p && strncmp(p, "pci", 3)) {
  254. if (*p == ',')
  255. (*cnt)++;
  256. p++;
  257. }
  258. if (!(*p))
  259. (*cnt)++;
  260. if (!(*cnt) || (*cnt) % 2) {
  261. printf("ERROR: invalid or odd extra iommu token count %d\n",
  262. *cnt);
  263. return NULL;
  264. }
  265. *cnt = (*cnt) / 2;
  266. entries = malloc((*cnt) * sizeof(*entries));
  267. if (!entries) {
  268. printf("ERROR: fail to allocate extra iommu entries\n");
  269. return NULL;
  270. }
  271. /*
  272. * Parse action entries one by one and store the information in the
  273. * newly allocated actions array.
  274. */
  275. p = s;
  276. while (p) {
  277. /* Extract BDF */
  278. b = simple_strtoul(p, (char **)&p, 0); p++;
  279. d = simple_strtoul(p, (char **)&p, 0); p++;
  280. f = simple_strtoul(p, (char **)&p, 0); p++;
  281. entries[i].bdf = PCI_BDF(b, d, f);
  282. /* Parse action */
  283. if (!strncmp(p, "hp", 2)) {
  284. /* Hot-plug entry */
  285. entries[i].action = EXTRA_IOMMU_ENTRY_HOTPLUG;
  286. p += 2;
  287. } else if (!strncmp(p, "vfs", 3) ||
  288. !strncmp(p, "noari_vfs", 9)) {
  289. /* VFs or VFs with ARI disabled entry */
  290. entries[i].action = EXTRA_IOMMU_ENTRY_VFS;
  291. entries[i].noari = !strncmp(p, "noari_vfs", 9);
  292. /*
  293. * Parse and store total number of VFs to allocate
  294. * IOMMU entries for.
  295. */
  296. p = strchr(p, '=');
  297. entries[i].num_vfs = simple_strtoul(p + 1, (char **)&p,
  298. 0);
  299. if (*p)
  300. p++;
  301. } else {
  302. printf("ERROR: invalid action in extra iommu entry\n");
  303. free(entries);
  304. return NULL;
  305. }
  306. if (!(*p) || !strncmp(p, "pci", 3))
  307. break;
  308. i++;
  309. }
  310. return entries;
  311. }
  312. static void get_vf_offset_and_stride(struct udevice *dev, int sriov_pos,
  313. struct extra_iommu_entry *entry,
  314. u16 *offset, u16 *stride)
  315. {
  316. u16 tmp16;
  317. u32 tmp32;
  318. bool have_ari = false;
  319. int pos;
  320. struct udevice *pf_dev;
  321. dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_TOTAL_VF, &tmp16);
  322. if (entry->num_vfs > tmp16) {
  323. printf("WARN: requested no. of VFs %d exceeds total of %d\n",
  324. entry->num_vfs, tmp16);
  325. }
  326. /*
  327. * The code below implements the VF Discovery recomandations specified
  328. * in PCIe base spec "9.2.1.2 VF Discovery", quoted below:
  329. *
  330. * VF Discovery
  331. *
  332. * The First VF Offset and VF Stride fields in the SR-IOV extended
  333. * capability are 16-bit Routing ID offsets. These offsets are used to
  334. * compute the Routing IDs for the VFs with the following restrictions:
  335. * - The value in NumVFs in a PF (Section 9.3.3.7) may affect the
  336. * values in First VF Offset (Section 9.3.3.9) and VF Stride
  337. * (Section 9.3.3.10) of that PF.
  338. * - The value in ARI Capable Hierarchy (Section 9.3.3.3.5) in the
  339. * lowest-numbered PF of the Device (for example PF0) may affect
  340. * the values in First VF Offset and VF Stride in all PFs of the
  341. * Device.
  342. * - NumVFs of a PF may only be changed when VF Enable
  343. * (Section 9.3.3.3.1) of that PF is Clear.
  344. * - ARI Capable Hierarchy (Section 9.3.3.3.5) may only be changed
  345. * when VF Enable is Clear in all PFs of a Device.
  346. */
  347. /* Clear VF enable for all PFs */
  348. device_foreach_child(pf_dev, dev->parent) {
  349. dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
  350. &tmp16);
  351. tmp16 &= ~PCI_SRIOV_CTRL_VFE;
  352. dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
  353. tmp16);
  354. }
  355. /* Obtain a reference to PF0 device */
  356. if (dm_pci_bus_find_bdf(PCI_BDF(PCI_BUS(entry->bdf),
  357. PCI_DEV(entry->bdf), 0), &pf_dev)) {
  358. printf("WARN: failed to get PF0\n");
  359. }
  360. if (entry->noari)
  361. goto skip_ari;
  362. /* Check that connected downstream port supports ARI Forwarding */
  363. pos = dm_pci_find_capability(dev->parent, PCI_CAP_ID_EXP);
  364. dm_pci_read_config32(dev->parent, pos + PCI_EXP_DEVCAP2, &tmp32);
  365. if (!(tmp32 & PCI_EXP_DEVCAP2_ARI))
  366. goto skip_ari;
  367. /* Check that PF supports Alternate Routing ID */
  368. if (!dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
  369. goto skip_ari;
  370. /* Set ARI Capable Hierarcy for PF0 */
  371. dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, &tmp16);
  372. tmp16 |= PCI_SRIOV_CTRL_ARI;
  373. dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, tmp16);
  374. have_ari = true;
  375. skip_ari:
  376. if (!have_ari) {
  377. /*
  378. * No ARI support or disabled so clear ARI Capable Hierarcy
  379. * for PF0
  380. */
  381. dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
  382. &tmp16);
  383. tmp16 &= ~PCI_SRIOV_CTRL_ARI;
  384. dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
  385. tmp16);
  386. }
  387. /* Set requested number of VFs */
  388. dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF,
  389. entry->num_vfs);
  390. /* Read VF stride and offset with the configs just made */
  391. dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_OFFSET, offset);
  392. dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_STRIDE, stride);
  393. if (have_ari) {
  394. /* Reset to default ARI Capable Hierarcy bit for PF0 */
  395. dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
  396. &tmp16);
  397. tmp16 &= ~PCI_SRIOV_CTRL_ARI;
  398. dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL,
  399. tmp16);
  400. }
  401. /* Reset to default the number of VFs */
  402. dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF, 0);
  403. }
  404. static int fdt_fixup_pci_vfs(void *blob, struct extra_iommu_entry *entry,
  405. struct ls_pcie_rc *pcie_rc)
  406. {
  407. struct udevice *dev, *bus;
  408. u16 vf_offset, vf_stride;
  409. int i, sriov_pos;
  410. pci_dev_t bdf;
  411. if (dm_pci_bus_find_bdf(entry->bdf, &dev)) {
  412. printf("ERROR: BDF %d.%d.%d not found\n", PCI_BUS(entry->bdf),
  413. PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf));
  414. return 0;
  415. }
  416. sriov_pos = dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
  417. if (!sriov_pos) {
  418. printf("WARN: trying to set VFs on non-SRIOV dev\n");
  419. return 0;
  420. }
  421. get_vf_offset_and_stride(dev, sriov_pos, entry, &vf_offset, &vf_stride);
  422. for (bus = dev; device_is_on_pci_bus(bus);)
  423. bus = bus->parent;
  424. bdf = entry->bdf - PCI_BDF(dev_seq(bus), 0, 0) + (vf_offset << 8);
  425. for (i = 0; i < entry->num_vfs; i++) {
  426. if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
  427. return -1;
  428. bdf += vf_stride << 8;
  429. }
  430. printf("Added %d iommu VF mappings for PF %d.%d.%d\n",
  431. entry->num_vfs, PCI_BUS(entry->bdf),
  432. PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf));
  433. return 0;
  434. }
  435. static void fdt_fixup_pcie_ls(void *blob)
  436. {
  437. struct udevice *dev, *bus;
  438. struct ls_pcie_rc *pcie_rc;
  439. pci_dev_t bdf;
  440. struct extra_iommu_entry *entries;
  441. int i, cnt, nodeoffset;
  442. /* Scan all known buses */
  443. for (pci_find_first_device(&dev);
  444. dev;
  445. pci_find_next_device(&dev)) {
  446. for (bus = dev; device_is_on_pci_bus(bus);)
  447. bus = bus->parent;
  448. /* Only do the fixups for layerscape PCIe controllers */
  449. if (!device_is_compatible(bus, "fsl,ls-pcie") &&
  450. !device_is_compatible(bus, CONFIG_FSL_PCIE_COMPAT))
  451. continue;
  452. pcie_rc = dev_get_priv(bus);
  453. /* the DT fixup must be relative to the hose first_busno */
  454. bdf = dm_pci_get_bdf(dev) - PCI_BDF(dev_seq(bus), 0, 0);
  455. if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0)
  456. break;
  457. }
  458. if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS))
  459. goto skip;
  460. list_for_each_entry(pcie_rc, &ls_pcie_list, list) {
  461. nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc);
  462. if (nodeoffset < 0) {
  463. printf("ERROR: couldn't find pci node\n");
  464. continue;
  465. }
  466. entries = get_extra_iommu_ents(blob, nodeoffset,
  467. pcie_rc->dbi_res.start, &cnt);
  468. if (!entries)
  469. continue;
  470. for (i = 0; i < cnt; i++) {
  471. if (entries[i].action == EXTRA_IOMMU_ENTRY_HOTPLUG) {
  472. bdf = entries[i].bdf;
  473. printf("Added iommu map for hotplug %d.%d.%d\n",
  474. PCI_BUS(bdf), PCI_DEV(bdf),
  475. PCI_FUNC(bdf));
  476. if (fdt_fixup_pcie_device_ls(blob, bdf,
  477. pcie_rc) < 0) {
  478. free(entries);
  479. return;
  480. }
  481. } else if (entries[i].action == EXTRA_IOMMU_ENTRY_VFS) {
  482. if (fdt_fixup_pci_vfs(blob, &entries[i],
  483. pcie_rc) < 0) {
  484. free(entries);
  485. return;
  486. }
  487. } else {
  488. printf("Invalid action %d for BDF %d.%d.%d\n",
  489. entries[i].action,
  490. PCI_BUS(entries[i].bdf),
  491. PCI_DEV(entries[i].bdf),
  492. PCI_FUNC(entries[i].bdf));
  493. }
  494. }
  495. free(entries);
  496. }
  497. skip:
  498. pcie_board_fix_fdt(blob);
  499. }
  500. #endif
  501. static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
  502. {
  503. int off;
  504. struct ls_pcie *pcie = pcie_rc->pcie;
  505. off = fdt_pcie_get_nodeoffset(blob, pcie_rc);
  506. if (off < 0)
  507. return;
  508. if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
  509. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  510. else
  511. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  512. }
  513. static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
  514. {
  515. int off;
  516. struct ls_pcie *pcie = pcie_rc->pcie;
  517. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
  518. pcie_rc->dbi_res.start);
  519. if (off < 0)
  520. return;
  521. if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  522. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  523. else
  524. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  525. }
  526. static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
  527. {
  528. ft_pcie_ep_fix(blob, pcie_rc);
  529. ft_pcie_rc_fix(blob, pcie_rc);
  530. }
  531. /* Fixup Kernel DT for PCIe */
  532. void ft_pci_setup_ls(void *blob, struct bd_info *bd)
  533. {
  534. struct ls_pcie_rc *pcie_rc;
  535. list_for_each_entry(pcie_rc, &ls_pcie_list, list)
  536. ft_pcie_ls_setup(blob, pcie_rc);
  537. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  538. fdt_fixup_pcie_ls(blob);
  539. #endif
  540. }
  541. #else /* !CONFIG_OF_BOARD_SETUP */
  542. void ft_pci_setup_ls(void *blob, struct bd_info *bd)
  543. {
  544. }
  545. #endif