pcie_imx.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale i.MX6 PCI Express Root-Complex driver
  4. *
  5. * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  6. *
  7. * Based on upstream Linux kernel driver:
  8. * pci-imx6.c: Sean Cross <xobs@kosagi.com>
  9. * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <pci.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/iomux.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/gpio.h>
  20. #include <asm/io.h>
  21. #include <dm.h>
  22. #include <linux/delay.h>
  23. #include <linux/sizes.h>
  24. #include <errno.h>
  25. #include <asm/arch/sys_proto.h>
  26. #define PCI_ACCESS_READ 0
  27. #define PCI_ACCESS_WRITE 1
  28. #ifdef CONFIG_MX6SX
  29. #define MX6_DBI_ADDR 0x08ffc000
  30. #define MX6_IO_ADDR 0x08000000
  31. #define MX6_MEM_ADDR 0x08100000
  32. #define MX6_ROOT_ADDR 0x08f00000
  33. #else
  34. #define MX6_DBI_ADDR 0x01ffc000
  35. #define MX6_IO_ADDR 0x01000000
  36. #define MX6_MEM_ADDR 0x01100000
  37. #define MX6_ROOT_ADDR 0x01f00000
  38. #endif
  39. #define MX6_DBI_SIZE 0x4000
  40. #define MX6_IO_SIZE 0x100000
  41. #define MX6_MEM_SIZE 0xe00000
  42. #define MX6_ROOT_SIZE 0xfc000
  43. /* PCIe Port Logic registers (memory-mapped) */
  44. #define PL_OFFSET 0x700
  45. #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
  46. #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
  47. #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
  48. #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  49. #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  50. #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
  51. #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
  52. #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  53. #define PCIE_PHY_CTRL_DATA_LOC 0
  54. #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  55. #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  56. #define PCIE_PHY_CTRL_WR_LOC 18
  57. #define PCIE_PHY_CTRL_RD_LOC 19
  58. #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  59. #define PCIE_PHY_STAT_DATA_LOC 0
  60. #define PCIE_PHY_STAT_ACK_LOC 16
  61. /* PHY registers (not memory-mapped) */
  62. #define PCIE_PHY_RX_ASIC_OUT 0x100D
  63. #define PHY_RX_OVRD_IN_LO 0x1005
  64. #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  65. #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  66. #define PCIE_PHY_PUP_REQ (1 << 7)
  67. /* iATU registers */
  68. #define PCIE_ATU_VIEWPORT 0x900
  69. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  70. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  71. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  72. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  73. #define PCIE_ATU_CR1 0x904
  74. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  75. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  76. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  77. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  78. #define PCIE_ATU_CR2 0x908
  79. #define PCIE_ATU_ENABLE (0x1 << 31)
  80. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  81. #define PCIE_ATU_LOWER_BASE 0x90C
  82. #define PCIE_ATU_UPPER_BASE 0x910
  83. #define PCIE_ATU_LIMIT 0x914
  84. #define PCIE_ATU_LOWER_TARGET 0x918
  85. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  86. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  87. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  88. #define PCIE_ATU_UPPER_TARGET 0x91C
  89. struct imx_pcie_priv {
  90. void __iomem *dbi_base;
  91. void __iomem *cfg_base;
  92. struct gpio_desc reset_gpio;
  93. bool reset_active_high;
  94. };
  95. /*
  96. * PHY access functions
  97. */
  98. static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
  99. {
  100. u32 val;
  101. u32 max_iterations = 10;
  102. u32 wait_counter = 0;
  103. do {
  104. val = readl(dbi_base + PCIE_PHY_STAT);
  105. val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
  106. wait_counter++;
  107. if (val == exp_val)
  108. return 0;
  109. udelay(1);
  110. } while (wait_counter < max_iterations);
  111. return -ETIMEDOUT;
  112. }
  113. static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
  114. {
  115. u32 val;
  116. int ret;
  117. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  118. writel(val, dbi_base + PCIE_PHY_CTRL);
  119. val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
  120. writel(val, dbi_base + PCIE_PHY_CTRL);
  121. ret = pcie_phy_poll_ack(dbi_base, 1);
  122. if (ret)
  123. return ret;
  124. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  125. writel(val, dbi_base + PCIE_PHY_CTRL);
  126. ret = pcie_phy_poll_ack(dbi_base, 0);
  127. if (ret)
  128. return ret;
  129. return 0;
  130. }
  131. /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
  132. static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
  133. {
  134. u32 val, phy_ctl;
  135. int ret;
  136. ret = pcie_phy_wait_ack(dbi_base, addr);
  137. if (ret)
  138. return ret;
  139. /* assert Read signal */
  140. phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
  141. writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
  142. ret = pcie_phy_poll_ack(dbi_base, 1);
  143. if (ret)
  144. return ret;
  145. val = readl(dbi_base + PCIE_PHY_STAT);
  146. *data = val & 0xffff;
  147. /* deassert Read signal */
  148. writel(0x00, dbi_base + PCIE_PHY_CTRL);
  149. ret = pcie_phy_poll_ack(dbi_base, 0);
  150. if (ret)
  151. return ret;
  152. return 0;
  153. }
  154. static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
  155. {
  156. u32 var;
  157. int ret;
  158. /* write addr */
  159. /* cap addr */
  160. ret = pcie_phy_wait_ack(dbi_base, addr);
  161. if (ret)
  162. return ret;
  163. var = data << PCIE_PHY_CTRL_DATA_LOC;
  164. writel(var, dbi_base + PCIE_PHY_CTRL);
  165. /* capture data */
  166. var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
  167. writel(var, dbi_base + PCIE_PHY_CTRL);
  168. ret = pcie_phy_poll_ack(dbi_base, 1);
  169. if (ret)
  170. return ret;
  171. /* deassert cap data */
  172. var = data << PCIE_PHY_CTRL_DATA_LOC;
  173. writel(var, dbi_base + PCIE_PHY_CTRL);
  174. /* wait for ack de-assertion */
  175. ret = pcie_phy_poll_ack(dbi_base, 0);
  176. if (ret)
  177. return ret;
  178. /* assert wr signal */
  179. var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
  180. writel(var, dbi_base + PCIE_PHY_CTRL);
  181. /* wait for ack */
  182. ret = pcie_phy_poll_ack(dbi_base, 1);
  183. if (ret)
  184. return ret;
  185. /* deassert wr signal */
  186. var = data << PCIE_PHY_CTRL_DATA_LOC;
  187. writel(var, dbi_base + PCIE_PHY_CTRL);
  188. /* wait for ack de-assertion */
  189. ret = pcie_phy_poll_ack(dbi_base, 0);
  190. if (ret)
  191. return ret;
  192. writel(0x0, dbi_base + PCIE_PHY_CTRL);
  193. return 0;
  194. }
  195. static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
  196. {
  197. u32 rc, ltssm;
  198. int rx_valid, temp;
  199. /* link is debug bit 36, debug register 1 starts at bit 32 */
  200. rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
  201. if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
  202. !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
  203. return -EAGAIN;
  204. /*
  205. * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
  206. * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
  207. * If (MAC/LTSSM.state == Recovery.RcvrLock)
  208. * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
  209. * to gen2 is stuck
  210. */
  211. pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
  212. ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
  213. if (rx_valid & 0x01)
  214. return 0;
  215. if (ltssm != 0x0d)
  216. return 0;
  217. printf("transition to gen2 is stuck, reset PHY!\n");
  218. pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  219. temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  220. pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  221. udelay(3000);
  222. pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  223. temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  224. pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  225. return 0;
  226. }
  227. /*
  228. * iATU region setup
  229. */
  230. static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
  231. {
  232. /*
  233. * i.MX6 defines 16MB in the AXI address map for PCIe.
  234. *
  235. * That address space excepted the pcie registers is
  236. * split and defined into different regions by iATU,
  237. * with sizes and offsets as follows:
  238. *
  239. * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
  240. * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
  241. * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
  242. */
  243. /* CMD reg:I/O space, MEM space, and Bus Master Enable */
  244. setbits_le32(priv->dbi_base + PCI_COMMAND,
  245. PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  246. /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
  247. setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
  248. PCI_CLASS_BRIDGE_PCI << 16);
  249. /* Region #0 is used for Outbound CFG space access. */
  250. writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  251. writel(lower_32_bits((uintptr_t)priv->cfg_base),
  252. priv->dbi_base + PCIE_ATU_LOWER_BASE);
  253. writel(upper_32_bits((uintptr_t)priv->cfg_base),
  254. priv->dbi_base + PCIE_ATU_UPPER_BASE);
  255. writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
  256. priv->dbi_base + PCIE_ATU_LIMIT);
  257. writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  258. writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
  259. writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  260. writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
  261. return 0;
  262. }
  263. /*
  264. * PCI Express accessors
  265. */
  266. static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
  267. pci_dev_t d, int where)
  268. {
  269. void __iomem *va_address;
  270. /* Reconfigure Region #0 */
  271. writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  272. if (PCI_BUS(d) < 2)
  273. writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  274. else
  275. writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
  276. if (PCI_BUS(d) == 0) {
  277. va_address = priv->dbi_base;
  278. } else {
  279. writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  280. va_address = priv->cfg_base;
  281. }
  282. va_address += (where & ~0x3);
  283. return va_address;
  284. }
  285. static int imx_pcie_addr_valid(pci_dev_t d)
  286. {
  287. if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
  288. return -EINVAL;
  289. if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
  290. return -EINVAL;
  291. return 0;
  292. }
  293. /*
  294. * Replace the original ARM DABT handler with a simple jump-back one.
  295. *
  296. * The problem here is that if we have a PCIe bridge attached to this PCIe
  297. * controller, but no PCIe device is connected to the bridges' downstream
  298. * port, the attempt to read/write from/to the config space will produce
  299. * a DABT. This is a behavior of the controller and can not be disabled
  300. * unfortuatelly.
  301. *
  302. * To work around the problem, we backup the current DABT handler address
  303. * and replace it with our own DABT handler, which only bounces right back
  304. * into the code.
  305. */
  306. static void imx_pcie_fix_dabt_handler(bool set)
  307. {
  308. extern uint32_t *_data_abort;
  309. uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
  310. static const uint32_t data_abort_bounce_handler = 0xe25ef004;
  311. uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
  312. static uint32_t data_abort_backup;
  313. if (set) {
  314. data_abort_backup = *data_abort_addr;
  315. *data_abort_addr = data_abort_bounce_addr;
  316. } else {
  317. *data_abort_addr = data_abort_backup;
  318. }
  319. }
  320. static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
  321. int where, u32 *val)
  322. {
  323. void __iomem *va_address;
  324. int ret;
  325. ret = imx_pcie_addr_valid(d);
  326. if (ret) {
  327. *val = 0xffffffff;
  328. return 0;
  329. }
  330. va_address = get_bus_address(priv, d, where);
  331. /*
  332. * Read the PCIe config space. We must replace the DABT handler
  333. * here in case we got data abort from the PCIe controller, see
  334. * imx_pcie_fix_dabt_handler() description. Note that writing the
  335. * "val" with valid value is also imperative here as in case we
  336. * did got DABT, the val would contain random value.
  337. */
  338. imx_pcie_fix_dabt_handler(true);
  339. writel(0xffffffff, val);
  340. *val = readl(va_address);
  341. imx_pcie_fix_dabt_handler(false);
  342. return 0;
  343. }
  344. static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
  345. int where, u32 val)
  346. {
  347. void __iomem *va_address = NULL;
  348. int ret;
  349. ret = imx_pcie_addr_valid(d);
  350. if (ret)
  351. return ret;
  352. va_address = get_bus_address(priv, d, where);
  353. /*
  354. * Write the PCIe config space. We must replace the DABT handler
  355. * here in case we got data abort from the PCIe controller, see
  356. * imx_pcie_fix_dabt_handler() description.
  357. */
  358. imx_pcie_fix_dabt_handler(true);
  359. writel(val, va_address);
  360. imx_pcie_fix_dabt_handler(false);
  361. return 0;
  362. }
  363. /*
  364. * Initial bus setup
  365. */
  366. static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
  367. bool prepare_for_boot)
  368. {
  369. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  370. if (is_mx6dqp())
  371. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  372. #if defined(CONFIG_MX6SX)
  373. struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
  374. /* SSP_EN is not used on MX6SX anymore */
  375. setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  376. /* Force PCIe PHY reset */
  377. setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  378. /* Power up PCIe PHY */
  379. setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
  380. #else
  381. /*
  382. * If the bootloader already enabled the link we need some special
  383. * handling to get the core back into a state where it is safe to
  384. * touch it for configuration. As there is no dedicated reset signal
  385. * wired up for MX6QDL, we need to manually force LTSSM into "detect"
  386. * state before completely disabling LTSSM, which is a prerequisite
  387. * for core configuration.
  388. *
  389. * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
  390. * indication that the bootloader activated the link.
  391. */
  392. if ((is_mx6dq() || is_mx6sdl()) && prepare_for_boot) {
  393. u32 val, gpr1, gpr12;
  394. gpr1 = readl(&iomuxc_regs->gpr[1]);
  395. gpr12 = readl(&iomuxc_regs->gpr[12]);
  396. if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
  397. (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
  398. val = readl(priv->dbi_base + PCIE_PL_PFLR);
  399. val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
  400. val |= PCIE_PL_PFLR_FORCE_LINK;
  401. imx_pcie_fix_dabt_handler(true);
  402. writel(val, priv->dbi_base + PCIE_PL_PFLR);
  403. imx_pcie_fix_dabt_handler(false);
  404. gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
  405. writel(val, &iomuxc_regs->gpr[12]);
  406. }
  407. }
  408. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
  409. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  410. #endif
  411. return 0;
  412. }
  413. static int imx6_pcie_init_phy(void)
  414. {
  415. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  416. clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  417. clrsetbits_le32(&iomuxc_regs->gpr[12],
  418. IOMUXC_GPR12_DEVICE_TYPE_MASK,
  419. IOMUXC_GPR12_DEVICE_TYPE_RC);
  420. clrsetbits_le32(&iomuxc_regs->gpr[12],
  421. IOMUXC_GPR12_LOS_LEVEL_MASK,
  422. IOMUXC_GPR12_LOS_LEVEL_9);
  423. #ifdef CONFIG_MX6SX
  424. clrsetbits_le32(&iomuxc_regs->gpr[12],
  425. IOMUXC_GPR12_RX_EQ_MASK,
  426. IOMUXC_GPR12_RX_EQ_2);
  427. #endif
  428. writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
  429. (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
  430. (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
  431. (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
  432. (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
  433. &iomuxc_regs->gpr[8]);
  434. return 0;
  435. }
  436. __weak int imx6_pcie_toggle_power(void)
  437. {
  438. #ifdef CONFIG_PCIE_IMX_POWER_GPIO
  439. gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
  440. gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
  441. mdelay(20);
  442. gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
  443. mdelay(20);
  444. gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
  445. #endif
  446. return 0;
  447. }
  448. __weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
  449. {
  450. /*
  451. * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
  452. * for detailed understanding of the PCIe CR reset logic.
  453. *
  454. * The PCIe #PERST reset line _MUST_ be connected, otherwise your
  455. * design does not conform to the specification. You must wait at
  456. * least 20 ms after de-asserting the #PERST so the EP device can
  457. * do self-initialisation.
  458. *
  459. * In case your #PERST pin is connected to a plain GPIO pin of the
  460. * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
  461. * configuration file and the condition below will handle the rest
  462. * of the reset toggling.
  463. *
  464. * In case your #PERST toggling logic is more complex, for example
  465. * connected via CPLD or somesuch, you can override this function
  466. * in your board file and implement reset logic as needed. You must
  467. * not forget to wait at least 20 ms after de-asserting #PERST in
  468. * this case either though.
  469. *
  470. * In case your #PERST line of the PCIe EP device is not connected
  471. * at all, your design is broken and you should fix your design,
  472. * otherwise you will observe problems like for example the link
  473. * not coming up after rebooting the system back from running Linux
  474. * that uses the PCIe as well OR the PCIe link might not come up in
  475. * Linux at all in the first place since it's in some non-reset
  476. * state due to being previously used in U-Boot.
  477. */
  478. #ifdef CONFIG_PCIE_IMX_PERST_GPIO
  479. gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
  480. gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
  481. mdelay(20);
  482. gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
  483. mdelay(20);
  484. gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
  485. #else
  486. if (dm_gpio_is_valid(gpio)) {
  487. /* Assert PERST# for 20ms then de-assert */
  488. dm_gpio_set_value(gpio, active_high ? 0 : 1);
  489. mdelay(20);
  490. dm_gpio_set_value(gpio, active_high ? 1 : 0);
  491. mdelay(20);
  492. } else {
  493. puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
  494. }
  495. #endif
  496. return 0;
  497. }
  498. static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
  499. {
  500. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  501. imx6_pcie_toggle_power();
  502. enable_pcie_clock();
  503. if (is_mx6dqp())
  504. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  505. /*
  506. * Wait for the clock to settle a bit, when the clock are sourced
  507. * from the CPU, we need about 30 ms to settle.
  508. */
  509. mdelay(50);
  510. #if defined(CONFIG_MX6SX)
  511. /* SSP_EN is not used on MX6SX anymore */
  512. clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  513. /* Clear PCIe PHY reset bit */
  514. clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  515. #else
  516. /* Enable PCIe */
  517. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
  518. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  519. #endif
  520. imx6_pcie_toggle_reset(&priv->reset_gpio, priv->reset_active_high);
  521. return 0;
  522. }
  523. static int imx_pcie_link_up(struct imx_pcie_priv *priv)
  524. {
  525. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  526. uint32_t tmp;
  527. int count = 0;
  528. imx6_pcie_assert_core_reset(priv, false);
  529. imx6_pcie_init_phy();
  530. imx6_pcie_deassert_core_reset(priv);
  531. imx_pcie_regions_setup(priv);
  532. /*
  533. * By default, the subordinate is set equally to the secondary
  534. * bus (0x01) when the RC boots.
  535. * This means that theoretically, only bus 1 is reachable from the RC.
  536. * Force the PCIe RC subordinate to 0xff, otherwise no downstream
  537. * devices will be detected if the enumeration is applied strictly.
  538. */
  539. tmp = readl(priv->dbi_base + 0x18);
  540. tmp |= (0xff << 16);
  541. writel(tmp, priv->dbi_base + 0x18);
  542. /*
  543. * FIXME: Force the PCIe RC to Gen1 operation
  544. * The RC must be forced into Gen1 mode before bringing the link
  545. * up, otherwise no downstream devices are detected. After the
  546. * link is up, a managed Gen1->Gen2 transition can be initiated.
  547. */
  548. tmp = readl(priv->dbi_base + 0x7c);
  549. tmp &= ~0xf;
  550. tmp |= 0x1;
  551. writel(tmp, priv->dbi_base + 0x7c);
  552. /* LTSSM enable, starting link. */
  553. setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  554. while (!imx6_pcie_link_up(priv)) {
  555. udelay(10);
  556. count++;
  557. if (count >= 4000) {
  558. #ifdef CONFIG_PCI_SCAN_SHOW
  559. puts("PCI: pcie phy link never came up\n");
  560. #endif
  561. debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
  562. readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
  563. readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
  564. return -EINVAL;
  565. }
  566. }
  567. return 0;
  568. }
  569. static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
  570. uint offset, ulong *value,
  571. enum pci_size_t size)
  572. {
  573. struct imx_pcie_priv *priv = dev_get_priv(dev);
  574. u32 tmpval;
  575. int ret;
  576. ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
  577. if (ret)
  578. return ret;
  579. *value = pci_conv_32_to_size(tmpval, offset, size);
  580. return 0;
  581. }
  582. static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
  583. uint offset, ulong value,
  584. enum pci_size_t size)
  585. {
  586. struct imx_pcie_priv *priv = dev_get_priv(dev);
  587. u32 tmpval, newval;
  588. int ret;
  589. ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
  590. if (ret)
  591. return ret;
  592. newval = pci_conv_size_to_32(tmpval, value, offset, size);
  593. return imx_pcie_write_cfg(priv, bdf, offset, newval);
  594. }
  595. static int imx_pcie_dm_probe(struct udevice *dev)
  596. {
  597. struct imx_pcie_priv *priv = dev_get_priv(dev);
  598. /* if PERST# valid from dt then assert it */
  599. gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
  600. GPIOD_IS_OUT);
  601. priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high");
  602. if (dm_gpio_is_valid(&priv->reset_gpio)) {
  603. dm_gpio_set_value(&priv->reset_gpio,
  604. priv->reset_active_high ? 0 : 1);
  605. }
  606. return imx_pcie_link_up(priv);
  607. }
  608. static int imx_pcie_dm_remove(struct udevice *dev)
  609. {
  610. struct imx_pcie_priv *priv = dev_get_priv(dev);
  611. imx6_pcie_assert_core_reset(priv, true);
  612. return 0;
  613. }
  614. static int imx_pcie_of_to_plat(struct udevice *dev)
  615. {
  616. struct imx_pcie_priv *priv = dev_get_priv(dev);
  617. priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
  618. priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
  619. if (!priv->dbi_base || !priv->cfg_base)
  620. return -EINVAL;
  621. return 0;
  622. }
  623. static const struct dm_pci_ops imx_pcie_ops = {
  624. .read_config = imx_pcie_dm_read_config,
  625. .write_config = imx_pcie_dm_write_config,
  626. };
  627. static const struct udevice_id imx_pcie_ids[] = {
  628. { .compatible = "fsl,imx6q-pcie" },
  629. { .compatible = "fsl,imx6sx-pcie" },
  630. { }
  631. };
  632. U_BOOT_DRIVER(imx_pcie) = {
  633. .name = "imx_pcie",
  634. .id = UCLASS_PCI,
  635. .of_match = imx_pcie_ids,
  636. .ops = &imx_pcie_ops,
  637. .probe = imx_pcie_dm_probe,
  638. .remove = imx_pcie_dm_remove,
  639. .of_to_plat = imx_pcie_of_to_plat,
  640. .priv_auto = sizeof(struct imx_pcie_priv),
  641. .flags = DM_FLAG_OS_PREPARE,
  642. };