pcie_dw_common.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2021 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. *
  6. * Copyright (c) 2021 Rockchip, Inc.
  7. *
  8. * Copyright (C) 2018 Texas Instruments, Inc
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <pci.h>
  14. #include <dm/device_compat.h>
  15. #include <asm/io.h>
  16. #include <linux/delay.h>
  17. #include "pcie_dw_common.h"
  18. int pcie_dw_get_link_speed(struct pcie_dw *pci)
  19. {
  20. return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
  21. PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
  22. }
  23. int pcie_dw_get_link_width(struct pcie_dw *pci)
  24. {
  25. return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
  26. PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
  27. }
  28. static void dw_pcie_writel_ob_unroll(struct pcie_dw *pci, u32 index, u32 reg,
  29. u32 val)
  30. {
  31. u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  32. void __iomem *base = pci->atu_base;
  33. writel(val, base + offset + reg);
  34. }
  35. static u32 dw_pcie_readl_ob_unroll(struct pcie_dw *pci, u32 index, u32 reg)
  36. {
  37. u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  38. void __iomem *base = pci->atu_base;
  39. return readl(base + offset + reg);
  40. }
  41. /**
  42. * pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
  43. *
  44. * @pcie: Pointer to the PCI controller state
  45. * @index: ATU region index
  46. * @type: ATU accsess type
  47. * @cpu_addr: the physical address for the translation entry
  48. * @pci_addr: the pcie bus address for the translation entry
  49. * @size: the size of the translation entry
  50. *
  51. * Return: 0 is successful and -1 is failure
  52. */
  53. int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index,
  54. int type, u64 cpu_addr,
  55. u64 pci_addr, u32 size)
  56. {
  57. u32 retries, val;
  58. dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
  59. index, type, cpu_addr, pci_addr, size);
  60. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
  61. lower_32_bits(cpu_addr));
  62. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
  63. upper_32_bits(cpu_addr));
  64. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
  65. lower_32_bits(cpu_addr + size - 1));
  66. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
  67. lower_32_bits(pci_addr));
  68. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
  69. upper_32_bits(pci_addr));
  70. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
  71. type);
  72. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
  73. PCIE_ATU_ENABLE);
  74. /*
  75. * Make sure ATU enable takes effect before any subsequent config
  76. * and I/O accesses.
  77. */
  78. for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
  79. val = dw_pcie_readl_ob_unroll(pci, index,
  80. PCIE_ATU_UNR_REGION_CTRL2);
  81. if (val & PCIE_ATU_ENABLE)
  82. return 0;
  83. udelay(LINK_WAIT_IATU);
  84. }
  85. dev_err(pci->dev, "outbound iATU is not being enabled\n");
  86. return -1;
  87. }
  88. /**
  89. * set_cfg_address() - Configure the PCIe controller config space access
  90. *
  91. * @pcie: Pointer to the PCI controller state
  92. * @d: PCI device to access
  93. * @where: Offset in the configuration space
  94. *
  95. * Configures the PCIe controller to access the configuration space of
  96. * a specific PCIe device and returns the address to use for this
  97. * access.
  98. *
  99. * Return: Address that can be used to access the configation space
  100. * of the requested device / offset
  101. */
  102. static uintptr_t set_cfg_address(struct pcie_dw *pcie,
  103. pci_dev_t d, uint where)
  104. {
  105. int bus = PCI_BUS(d) - pcie->first_busno;
  106. uintptr_t va_address;
  107. u32 atu_type;
  108. int ret;
  109. /* Use dbi_base for own configuration read and write */
  110. if (!bus) {
  111. va_address = (uintptr_t)pcie->dbi_base;
  112. goto out;
  113. }
  114. if (bus == 1)
  115. /*
  116. * For local bus whose primary bus number is root bridge,
  117. * change TLP Type field to 4.
  118. */
  119. atu_type = PCIE_ATU_TYPE_CFG0;
  120. else
  121. /* Otherwise, change TLP Type field to 5. */
  122. atu_type = PCIE_ATU_TYPE_CFG1;
  123. /*
  124. * Not accessing root port configuration space?
  125. * Region #0 is used for Outbound CFG space access.
  126. * Direction = Outbound
  127. * Region Index = 0
  128. */
  129. d = PCI_MASK_BUS(d);
  130. d = PCI_ADD_BUS(bus, d);
  131. ret = pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  132. atu_type, (u64)pcie->cfg_base,
  133. d << 8, pcie->cfg_size);
  134. if (ret)
  135. return (uintptr_t)ret;
  136. va_address = (uintptr_t)pcie->cfg_base;
  137. out:
  138. va_address += where & ~0x3;
  139. return va_address;
  140. }
  141. /**
  142. * pcie_dw_addr_valid() - Check for valid bus address
  143. *
  144. * @d: The PCI device to access
  145. * @first_busno: Bus number of the PCIe controller root complex
  146. *
  147. * Return 1 (true) if the PCI device can be accessed by this controller.
  148. *
  149. * Return: 1 on valid, 0 on invalid
  150. */
  151. static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
  152. {
  153. if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
  154. return 0;
  155. if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
  156. return 0;
  157. return 1;
  158. }
  159. /**
  160. * pcie_dw_read_config() - Read from configuration space
  161. *
  162. * @bus: Pointer to the PCI bus
  163. * @bdf: Identifies the PCIe device to access
  164. * @offset: The offset into the device's configuration space
  165. * @valuep: A pointer at which to store the read value
  166. * @size: Indicates the size of access to perform
  167. *
  168. * Read a value of size @size from offset @offset within the configuration
  169. * space of the device identified by the bus, device & function numbers in @bdf
  170. * on the PCI bus @bus.
  171. *
  172. * Return: 0 on success
  173. */
  174. int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf,
  175. uint offset, ulong *valuep,
  176. enum pci_size_t size)
  177. {
  178. struct pcie_dw *pcie = dev_get_priv(bus);
  179. uintptr_t va_address;
  180. ulong value;
  181. dev_dbg(pcie->dev, "PCIE CFG read: bdf=%2x:%2x:%2x ",
  182. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  183. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  184. debug("- out of range\n");
  185. *valuep = pci_get_ff(size);
  186. return 0;
  187. }
  188. va_address = set_cfg_address(pcie, bdf, offset);
  189. value = readl((void __iomem *)va_address);
  190. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  191. *valuep = pci_conv_32_to_size(value, offset, size);
  192. return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  193. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  194. pcie->io.bus_start, pcie->io.size);
  195. }
  196. /**
  197. * pcie_dw_write_config() - Write to configuration space
  198. *
  199. * @bus: Pointer to the PCI bus
  200. * @bdf: Identifies the PCIe device to access
  201. * @offset: The offset into the device's configuration space
  202. * @value: The value to write
  203. * @size: Indicates the size of access to perform
  204. *
  205. * Write the value @value of size @size from offset @offset within the
  206. * configuration space of the device identified by the bus, device & function
  207. * numbers in @bdf on the PCI bus @bus.
  208. *
  209. * Return: 0 on success
  210. */
  211. int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf,
  212. uint offset, ulong value,
  213. enum pci_size_t size)
  214. {
  215. struct pcie_dw *pcie = dev_get_priv(bus);
  216. uintptr_t va_address;
  217. ulong old;
  218. dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  219. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  220. dev_dbg(pcie->dev, "(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  221. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  222. debug("- out of range\n");
  223. return 0;
  224. }
  225. va_address = set_cfg_address(pcie, bdf, offset);
  226. old = readl((void __iomem *)va_address);
  227. value = pci_conv_size_to_32(old, value, offset, size);
  228. writel(value, (void __iomem *)va_address);
  229. return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  230. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  231. pcie->io.bus_start, pcie->io.size);
  232. }
  233. /**
  234. * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
  235. *
  236. * @pcie: Pointer to the PCI controller state
  237. *
  238. * Configure the host BARs of the PCIe controller root port so that
  239. * PCI(e) devices may access the system memory.
  240. */
  241. void pcie_dw_setup_host(struct pcie_dw *pci)
  242. {
  243. struct udevice *ctlr = pci_get_controller(pci->dev);
  244. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  245. u32 ret;
  246. if (!pci->atu_base)
  247. pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
  248. /* setup RC BARs */
  249. writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
  250. pci->dbi_base + PCI_BASE_ADDRESS_0);
  251. writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
  252. /* setup interrupt pins */
  253. clrsetbits_le32(pci->dbi_base + PCI_INTERRUPT_LINE,
  254. 0xff00, 0x100);
  255. /* setup bus numbers */
  256. clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
  257. 0xffffff, 0x00ff0100);
  258. /* setup command register */
  259. clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
  260. 0xffff,
  261. PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  262. PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
  263. /* Enable write permission for the DBI read-only register */
  264. dw_pcie_dbi_write_enable(pci, true);
  265. /* program correct class for RC */
  266. writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
  267. /* Better disable write permission right after the update */
  268. dw_pcie_dbi_write_enable(pci, false);
  269. setbits_le32(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL,
  270. PORT_LOGIC_SPEED_CHANGE);
  271. for (ret = 0; ret < hose->region_count; ret++) {
  272. if (hose->regions[ret].flags == PCI_REGION_IO) {
  273. pci->io.phys_start = hose->regions[ret].phys_start; /* IO base */
  274. pci->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */
  275. pci->io.size = hose->regions[ret].size; /* IO size */
  276. } else if (hose->regions[ret].flags == PCI_REGION_MEM) {
  277. pci->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */
  278. pci->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */
  279. pci->mem.size = hose->regions[ret].size; /* MEM size */
  280. } else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) {
  281. pci->prefetch.phys_start = hose->regions[ret].phys_start; /* PREFETCH base */
  282. pci->prefetch.bus_start = hose->regions[ret].bus_start; /* PREFETCH_bus_addr */
  283. pci->prefetch.size = hose->regions[ret].size; /* PREFETCH size */
  284. } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) {
  285. pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size);
  286. pci->cfg_size = pci->io.size;
  287. } else {
  288. dev_err(pci->dev, "invalid flags type!\n");
  289. }
  290. }
  291. dev_dbg(pci->dev, "Config space: [0x%llx - 0x%llx, size 0x%llx]\n",
  292. (u64)pci->cfg_base, (u64)pci->cfg_base + pci->cfg_size,
  293. (u64)pci->cfg_size);
  294. dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n",
  295. (u64)pci->io.phys_start, (u64)pci->io.phys_start + pci->io.size,
  296. (u64)pci->io.size);
  297. dev_dbg(pci->dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n",
  298. (u64)pci->io.bus_start, (u64)pci->io.bus_start + pci->io.size,
  299. (u64)pci->io.size);
  300. dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%llx]\n",
  301. (u64)pci->mem.phys_start,
  302. (u64)pci->mem.phys_start + pci->mem.size,
  303. (u64)pci->mem.size);
  304. dev_dbg(pci->dev, "MEM bus: [0x%llx - 0x%llx, size 0x%llx]\n",
  305. (u64)pci->mem.bus_start,
  306. (u64)pci->mem.bus_start + pci->mem.size,
  307. (u64)pci->mem.size);
  308. if (pci->prefetch.size) {
  309. dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%llx]\n",
  310. (u64)pci->prefetch.phys_start,
  311. (u64)pci->prefetch.phys_start + pci->prefetch.size,
  312. (u64)pci->prefetch.size);
  313. dev_dbg(pci->dev, "PREFETCH bus: [0x%llx - 0x%llx, size 0x%llx]\n",
  314. (u64)pci->prefetch.bus_start,
  315. (u64)pci->prefetch.bus_start + pci->prefetch.size,
  316. (u64)pci->prefetch.size);
  317. }
  318. }