zynq_gem.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 Michal Simek
  4. *
  5. * Michal SIMEK <monstr@monstr.eu>
  6. *
  7. * Based on Xilinx gmac driver:
  8. * (C) Copyright 2011 Xilinx
  9. */
  10. #include <clk.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <config.h>
  18. #include <console.h>
  19. #include <malloc.h>
  20. #include <asm/cache.h>
  21. #include <asm/io.h>
  22. #include <phy.h>
  23. #include <miiphy.h>
  24. #include <wait_bit.h>
  25. #include <watchdog.h>
  26. #include <asm/system.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <dm/device_compat.h>
  30. #include <linux/bitops.h>
  31. #include <linux/err.h>
  32. #include <linux/errno.h>
  33. /* Bit/mask specification */
  34. #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
  35. #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
  36. #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
  37. #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
  38. #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
  39. #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
  40. #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
  41. #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
  42. #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
  43. #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
  44. #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
  45. /* Wrap bit, last descriptor */
  46. #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
  47. #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
  48. #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
  49. #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
  50. #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
  51. #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
  52. #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
  53. #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
  54. #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
  55. #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
  56. #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
  57. #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
  58. #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
  59. #ifdef CONFIG_ARM64
  60. #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
  61. #else
  62. #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
  63. #endif
  64. #ifdef CONFIG_ARM64
  65. # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
  66. #else
  67. # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
  68. #endif
  69. #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
  70. ZYNQ_GEM_NWCFG_FDEN | \
  71. ZYNQ_GEM_NWCFG_FSREM | \
  72. ZYNQ_GEM_NWCFG_MDCCLKDIV)
  73. #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
  74. #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
  75. /* Use full configured addressable space (8 Kb) */
  76. #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
  77. /* Use full configured addressable space (4 Kb) */
  78. #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
  79. /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
  80. #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
  81. #if defined(CONFIG_PHYS_64BIT)
  82. # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
  83. #else
  84. # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
  85. #endif
  86. #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
  87. ZYNQ_GEM_DMACR_RXSIZE | \
  88. ZYNQ_GEM_DMACR_TXSIZE | \
  89. ZYNQ_GEM_DMACR_RXBUF | \
  90. ZYNQ_GEM_DMA_BUS_WIDTH)
  91. #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
  92. #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
  93. #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
  94. /* Use MII register 1 (MII status register) to detect PHY */
  95. #define PHY_DETECT_REG 1
  96. /* Mask used to verify certain PHY features (or register contents)
  97. * in the register above:
  98. * 0x1000: 10Mbps full duplex support
  99. * 0x0800: 10Mbps half duplex support
  100. * 0x0008: Auto-negotiation support
  101. */
  102. #define PHY_DETECT_MASK 0x1808
  103. /* TX BD status masks */
  104. #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
  105. #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
  106. #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
  107. /* Clock frequencies for different speeds */
  108. #define ZYNQ_GEM_FREQUENCY_10 2500000UL
  109. #define ZYNQ_GEM_FREQUENCY_100 25000000UL
  110. #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
  111. #define RXCLK_EN BIT(0)
  112. /* Device registers */
  113. struct zynq_gem_regs {
  114. u32 nwctrl; /* 0x0 - Network Control reg */
  115. u32 nwcfg; /* 0x4 - Network Config reg */
  116. u32 nwsr; /* 0x8 - Network Status reg */
  117. u32 reserved1;
  118. u32 dmacr; /* 0x10 - DMA Control reg */
  119. u32 txsr; /* 0x14 - TX Status reg */
  120. u32 rxqbase; /* 0x18 - RX Q Base address reg */
  121. u32 txqbase; /* 0x1c - TX Q Base address reg */
  122. u32 rxsr; /* 0x20 - RX Status reg */
  123. u32 reserved2[2];
  124. u32 idr; /* 0x2c - Interrupt Disable reg */
  125. u32 reserved3;
  126. u32 phymntnc; /* 0x34 - Phy Maintaince reg */
  127. u32 reserved4[18];
  128. u32 hashl; /* 0x80 - Hash Low address reg */
  129. u32 hashh; /* 0x84 - Hash High address reg */
  130. #define LADDR_LOW 0
  131. #define LADDR_HIGH 1
  132. u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
  133. u32 match[4]; /* 0xa8 - Type ID1 Match reg */
  134. u32 reserved6[18];
  135. #define STAT_SIZE 44
  136. u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
  137. u32 reserved9[20];
  138. u32 pcscntrl;
  139. u32 rserved12[36];
  140. u32 dcfg6; /* 0x294 Design config reg6 */
  141. u32 reserved7[106];
  142. u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
  143. u32 reserved8[15];
  144. u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
  145. u32 reserved10[17];
  146. u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
  147. u32 reserved11[2];
  148. u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
  149. };
  150. /* BD descriptors */
  151. struct emac_bd {
  152. u32 addr; /* Next descriptor pointer */
  153. u32 status;
  154. #if defined(CONFIG_PHYS_64BIT)
  155. u32 addr_hi;
  156. u32 reserved;
  157. #endif
  158. };
  159. /* Reduce amount of BUFs if you have limited amount of memory */
  160. #define RX_BUF 32
  161. /* Page table entries are set to 1MB, or multiples of 1MB
  162. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  163. */
  164. #define BD_SPACE 0x100000
  165. /* BD separation space */
  166. #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
  167. /* Setup the first free TX descriptor */
  168. #define TX_FREE_DESC 2
  169. /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
  170. struct zynq_gem_priv {
  171. struct emac_bd *tx_bd;
  172. struct emac_bd *rx_bd;
  173. char *rxbuffers;
  174. u32 rxbd_current;
  175. u32 rx_first_buf;
  176. int phyaddr;
  177. int init;
  178. struct zynq_gem_regs *iobase;
  179. struct zynq_gem_regs *mdiobase;
  180. phy_interface_t interface;
  181. struct phy_device *phydev;
  182. ofnode phy_of_node;
  183. struct mii_dev *bus;
  184. struct clk rx_clk;
  185. struct clk tx_clk;
  186. u32 max_speed;
  187. bool int_pcs;
  188. bool dma_64bit;
  189. u32 clk_en_info;
  190. };
  191. static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
  192. u32 op, u16 *data)
  193. {
  194. u32 mgtcr;
  195. struct zynq_gem_regs *regs = priv->mdiobase;
  196. int err;
  197. err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
  198. true, 20000, false);
  199. if (err)
  200. return err;
  201. /* Construct mgtcr mask for the operation */
  202. mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
  203. (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
  204. (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
  205. /* Write mgtcr and wait for completion */
  206. writel(mgtcr, &regs->phymntnc);
  207. err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
  208. true, 20000, false);
  209. if (err)
  210. return err;
  211. if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
  212. *data = readl(&regs->phymntnc);
  213. return 0;
  214. }
  215. static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
  216. u32 regnum, u16 *val)
  217. {
  218. int ret;
  219. ret = phy_setup_op(priv, phy_addr, regnum,
  220. ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
  221. if (!ret)
  222. debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
  223. phy_addr, regnum, *val);
  224. return ret;
  225. }
  226. static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
  227. u32 regnum, u16 data)
  228. {
  229. debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
  230. regnum, data);
  231. return phy_setup_op(priv, phy_addr, regnum,
  232. ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
  233. }
  234. static int zynq_gem_setup_mac(struct udevice *dev)
  235. {
  236. u32 i, macaddrlow, macaddrhigh;
  237. struct eth_pdata *pdata = dev_get_plat(dev);
  238. struct zynq_gem_priv *priv = dev_get_priv(dev);
  239. struct zynq_gem_regs *regs = priv->iobase;
  240. /* Set the MAC bits [31:0] in BOT */
  241. macaddrlow = pdata->enetaddr[0];
  242. macaddrlow |= pdata->enetaddr[1] << 8;
  243. macaddrlow |= pdata->enetaddr[2] << 16;
  244. macaddrlow |= pdata->enetaddr[3] << 24;
  245. /* Set MAC bits [47:32] in TOP */
  246. macaddrhigh = pdata->enetaddr[4];
  247. macaddrhigh |= pdata->enetaddr[5] << 8;
  248. for (i = 0; i < 4; i++) {
  249. writel(0, &regs->laddr[i][LADDR_LOW]);
  250. writel(0, &regs->laddr[i][LADDR_HIGH]);
  251. /* Do not use MATCHx register */
  252. writel(0, &regs->match[i]);
  253. }
  254. writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
  255. writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
  256. return 0;
  257. }
  258. static int zynq_phy_init(struct udevice *dev)
  259. {
  260. int ret;
  261. struct zynq_gem_priv *priv = dev_get_priv(dev);
  262. struct zynq_gem_regs *regs_mdio = priv->mdiobase;
  263. const u32 supported = SUPPORTED_10baseT_Half |
  264. SUPPORTED_10baseT_Full |
  265. SUPPORTED_100baseT_Half |
  266. SUPPORTED_100baseT_Full |
  267. SUPPORTED_1000baseT_Half |
  268. SUPPORTED_1000baseT_Full;
  269. /* Enable only MDIO bus */
  270. writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs_mdio->nwctrl);
  271. priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
  272. priv->interface);
  273. if (!priv->phydev)
  274. return -ENODEV;
  275. if (priv->max_speed) {
  276. ret = phy_set_supported(priv->phydev, priv->max_speed);
  277. if (ret)
  278. return ret;
  279. }
  280. priv->phydev->supported &= supported | ADVERTISED_Pause |
  281. ADVERTISED_Asym_Pause;
  282. priv->phydev->advertising = priv->phydev->supported;
  283. priv->phydev->node = priv->phy_of_node;
  284. return phy_config(priv->phydev);
  285. }
  286. static int zynq_gem_init(struct udevice *dev)
  287. {
  288. u32 i, nwconfig;
  289. int ret;
  290. unsigned long clk_rate = 0;
  291. struct zynq_gem_priv *priv = dev_get_priv(dev);
  292. struct zynq_gem_regs *regs = priv->iobase;
  293. struct zynq_gem_regs *regs_mdio = priv->mdiobase;
  294. struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
  295. struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
  296. if (readl(&regs->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
  297. priv->dma_64bit = true;
  298. else
  299. priv->dma_64bit = false;
  300. #if defined(CONFIG_PHYS_64BIT)
  301. if (!priv->dma_64bit) {
  302. printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
  303. __func__);
  304. return -EINVAL;
  305. }
  306. #else
  307. if (priv->dma_64bit)
  308. debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
  309. __func__);
  310. #endif
  311. if (!priv->init) {
  312. /* Disable all interrupts */
  313. writel(0xFFFFFFFF, &regs->idr);
  314. /* Disable the receiver & transmitter */
  315. writel(0, &regs->nwctrl);
  316. writel(0, &regs->txsr);
  317. writel(0, &regs->rxsr);
  318. writel(0, &regs->phymntnc);
  319. /* Clear the Hash registers for the mac address
  320. * pointed by AddressPtr
  321. */
  322. writel(0x0, &regs->hashl);
  323. /* Write bits [63:32] in TOP */
  324. writel(0x0, &regs->hashh);
  325. /* Clear all counters */
  326. for (i = 0; i < STAT_SIZE; i++)
  327. readl(&regs->stat[i]);
  328. /* Setup RxBD space */
  329. memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
  330. for (i = 0; i < RX_BUF; i++) {
  331. priv->rx_bd[i].status = 0xF0000000;
  332. priv->rx_bd[i].addr =
  333. (lower_32_bits((ulong)(priv->rxbuffers)
  334. + (i * PKTSIZE_ALIGN)));
  335. #if defined(CONFIG_PHYS_64BIT)
  336. priv->rx_bd[i].addr_hi =
  337. (upper_32_bits((ulong)(priv->rxbuffers)
  338. + (i * PKTSIZE_ALIGN)));
  339. #endif
  340. }
  341. /* WRAP bit to last BD */
  342. priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
  343. /* Write RxBDs to IP */
  344. writel(lower_32_bits((ulong)priv->rx_bd), &regs->rxqbase);
  345. #if defined(CONFIG_PHYS_64BIT)
  346. writel(upper_32_bits((ulong)priv->rx_bd), &regs->upper_rxqbase);
  347. #endif
  348. /* Setup for DMA Configuration register */
  349. writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
  350. /* Setup for Network Control register, MDIO, Rx and Tx enable */
  351. setbits_le32(&regs_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
  352. /* Disable the second priority queue */
  353. dummy_tx_bd->addr = 0;
  354. #if defined(CONFIG_PHYS_64BIT)
  355. dummy_tx_bd->addr_hi = 0;
  356. #endif
  357. dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
  358. ZYNQ_GEM_TXBUF_LAST_MASK|
  359. ZYNQ_GEM_TXBUF_USED_MASK;
  360. dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
  361. ZYNQ_GEM_RXBUF_NEW_MASK;
  362. #if defined(CONFIG_PHYS_64BIT)
  363. dummy_rx_bd->addr_hi = 0;
  364. #endif
  365. dummy_rx_bd->status = 0;
  366. writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
  367. writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
  368. priv->init++;
  369. }
  370. ret = phy_startup(priv->phydev);
  371. if (ret)
  372. return ret;
  373. if (!priv->phydev->link) {
  374. printf("%s: No link.\n", priv->phydev->dev->name);
  375. return -1;
  376. }
  377. nwconfig = ZYNQ_GEM_NWCFG_INIT;
  378. /*
  379. * Set SGMII enable PCS selection only if internal PCS/PMA
  380. * core is used and interface is SGMII.
  381. */
  382. if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
  383. priv->int_pcs) {
  384. nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
  385. ZYNQ_GEM_NWCFG_PCS_SEL;
  386. }
  387. switch (priv->phydev->speed) {
  388. case SPEED_1000:
  389. writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
  390. &regs->nwcfg);
  391. clk_rate = ZYNQ_GEM_FREQUENCY_1000;
  392. break;
  393. case SPEED_100:
  394. writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
  395. &regs->nwcfg);
  396. clk_rate = ZYNQ_GEM_FREQUENCY_100;
  397. break;
  398. case SPEED_10:
  399. clk_rate = ZYNQ_GEM_FREQUENCY_10;
  400. break;
  401. }
  402. #ifdef CONFIG_ARM64
  403. if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
  404. priv->int_pcs) {
  405. /*
  406. * Disable AN for fixed link configuration, enable otherwise.
  407. * Must be written after PCS_SEL is set in nwconfig,
  408. * otherwise writes will not take effect.
  409. */
  410. if (priv->phydev->phy_id != PHY_FIXED_ID)
  411. writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
  412. &regs->pcscntrl);
  413. else
  414. writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
  415. &regs->pcscntrl);
  416. }
  417. #endif
  418. ret = clk_set_rate(&priv->tx_clk, clk_rate);
  419. if (IS_ERR_VALUE(ret)) {
  420. dev_err(dev, "failed to set tx clock rate\n");
  421. return ret;
  422. }
  423. ret = clk_enable(&priv->tx_clk);
  424. if (ret) {
  425. dev_err(dev, "failed to enable tx clock\n");
  426. return ret;
  427. }
  428. if (priv->clk_en_info & RXCLK_EN) {
  429. ret = clk_enable(&priv->rx_clk);
  430. if (ret) {
  431. dev_err(dev, "failed to enable rx clock\n");
  432. return ret;
  433. }
  434. }
  435. setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
  436. ZYNQ_GEM_NWCTRL_TXEN_MASK);
  437. return 0;
  438. }
  439. static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
  440. {
  441. dma_addr_t addr;
  442. u32 size;
  443. struct zynq_gem_priv *priv = dev_get_priv(dev);
  444. struct zynq_gem_regs *regs = priv->iobase;
  445. struct emac_bd *current_bd = &priv->tx_bd[1];
  446. /* Setup Tx BD */
  447. memset(priv->tx_bd, 0, sizeof(struct emac_bd));
  448. priv->tx_bd->addr = lower_32_bits((ulong)ptr);
  449. #if defined(CONFIG_PHYS_64BIT)
  450. priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
  451. #endif
  452. priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
  453. ZYNQ_GEM_TXBUF_LAST_MASK;
  454. /* Dummy descriptor to mark it as the last in descriptor chain */
  455. current_bd->addr = 0x0;
  456. #if defined(CONFIG_PHYS_64BIT)
  457. current_bd->addr_hi = 0x0;
  458. #endif
  459. current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
  460. ZYNQ_GEM_TXBUF_LAST_MASK|
  461. ZYNQ_GEM_TXBUF_USED_MASK;
  462. /* setup BD */
  463. writel(lower_32_bits((ulong)priv->tx_bd), &regs->txqbase);
  464. #if defined(CONFIG_PHYS_64BIT)
  465. writel(upper_32_bits((ulong)priv->tx_bd), &regs->upper_txqbase);
  466. #endif
  467. addr = (ulong) ptr;
  468. addr &= ~(ARCH_DMA_MINALIGN - 1);
  469. size = roundup(len, ARCH_DMA_MINALIGN);
  470. flush_dcache_range(addr, addr + size);
  471. barrier();
  472. /* Start transmit */
  473. setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
  474. /* Read TX BD status */
  475. if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
  476. printf("TX buffers exhausted in mid frame\n");
  477. return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
  478. true, 20000, true);
  479. }
  480. /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
  481. static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
  482. {
  483. int frame_len;
  484. dma_addr_t addr;
  485. struct zynq_gem_priv *priv = dev_get_priv(dev);
  486. struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
  487. if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
  488. return -1;
  489. if (!(current_bd->status &
  490. (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
  491. printf("GEM: SOF or EOF not set for last buffer received!\n");
  492. return -1;
  493. }
  494. frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
  495. if (!frame_len) {
  496. printf("%s: Zero size packet?\n", __func__);
  497. return -1;
  498. }
  499. #if defined(CONFIG_PHYS_64BIT)
  500. addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
  501. | ((dma_addr_t)current_bd->addr_hi << 32));
  502. #else
  503. addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
  504. #endif
  505. addr &= ~(ARCH_DMA_MINALIGN - 1);
  506. *packetp = (uchar *)(uintptr_t)addr;
  507. invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
  508. barrier();
  509. return frame_len;
  510. }
  511. static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
  512. {
  513. struct zynq_gem_priv *priv = dev_get_priv(dev);
  514. struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
  515. struct emac_bd *first_bd;
  516. dma_addr_t addr;
  517. if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
  518. priv->rx_first_buf = priv->rxbd_current;
  519. } else {
  520. current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
  521. current_bd->status = 0xF0000000; /* FIXME */
  522. }
  523. if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
  524. first_bd = &priv->rx_bd[priv->rx_first_buf];
  525. first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
  526. first_bd->status = 0xF0000000;
  527. }
  528. /* Flush the cache for the packet as well */
  529. #if defined(CONFIG_PHYS_64BIT)
  530. addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
  531. | ((dma_addr_t)current_bd->addr_hi << 32));
  532. #else
  533. addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
  534. #endif
  535. flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
  536. ARCH_DMA_MINALIGN));
  537. barrier();
  538. if ((++priv->rxbd_current) >= RX_BUF)
  539. priv->rxbd_current = 0;
  540. return 0;
  541. }
  542. static void zynq_gem_halt(struct udevice *dev)
  543. {
  544. struct zynq_gem_priv *priv = dev_get_priv(dev);
  545. struct zynq_gem_regs *regs = priv->iobase;
  546. clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
  547. ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
  548. }
  549. __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
  550. {
  551. return -ENOSYS;
  552. }
  553. static int zynq_gem_read_rom_mac(struct udevice *dev)
  554. {
  555. struct eth_pdata *pdata = dev_get_plat(dev);
  556. if (!pdata)
  557. return -ENOSYS;
  558. return zynq_board_read_rom_ethaddr(pdata->enetaddr);
  559. }
  560. static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
  561. int devad, int reg)
  562. {
  563. struct zynq_gem_priv *priv = bus->priv;
  564. int ret;
  565. u16 val = 0;
  566. ret = phyread(priv, addr, reg, &val);
  567. debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
  568. return val;
  569. }
  570. static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
  571. int reg, u16 value)
  572. {
  573. struct zynq_gem_priv *priv = bus->priv;
  574. debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
  575. return phywrite(priv, addr, reg, value);
  576. }
  577. static int zynq_gem_probe(struct udevice *dev)
  578. {
  579. void *bd_space;
  580. struct zynq_gem_priv *priv = dev_get_priv(dev);
  581. int ret;
  582. /* Align rxbuffers to ARCH_DMA_MINALIGN */
  583. priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
  584. if (!priv->rxbuffers)
  585. return -ENOMEM;
  586. memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
  587. ulong addr = (ulong)priv->rxbuffers;
  588. flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
  589. barrier();
  590. /* Align bd_space to MMU_SECTION_SHIFT */
  591. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  592. if (!bd_space) {
  593. ret = -ENOMEM;
  594. goto err1;
  595. }
  596. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
  597. BD_SPACE, DCACHE_OFF);
  598. /* Initialize the bd spaces for tx and rx bd's */
  599. priv->tx_bd = (struct emac_bd *)bd_space;
  600. priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
  601. ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk);
  602. if (ret < 0) {
  603. dev_err(dev, "failed to get tx_clock\n");
  604. goto err2;
  605. }
  606. if (priv->clk_en_info & RXCLK_EN) {
  607. ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk);
  608. if (ret < 0) {
  609. dev_err(dev, "failed to get rx_clock\n");
  610. goto err2;
  611. }
  612. }
  613. priv->bus = mdio_alloc();
  614. priv->bus->read = zynq_gem_miiphy_read;
  615. priv->bus->write = zynq_gem_miiphy_write;
  616. priv->bus->priv = priv;
  617. ret = mdio_register_seq(priv->bus, dev_seq(dev));
  618. if (ret)
  619. goto err2;
  620. ret = zynq_phy_init(dev);
  621. if (ret)
  622. goto err3;
  623. return ret;
  624. err3:
  625. mdio_unregister(priv->bus);
  626. err2:
  627. free(priv->tx_bd);
  628. err1:
  629. free(priv->rxbuffers);
  630. return ret;
  631. }
  632. static int zynq_gem_remove(struct udevice *dev)
  633. {
  634. struct zynq_gem_priv *priv = dev_get_priv(dev);
  635. free(priv->phydev);
  636. mdio_unregister(priv->bus);
  637. mdio_free(priv->bus);
  638. return 0;
  639. }
  640. static const struct eth_ops zynq_gem_ops = {
  641. .start = zynq_gem_init,
  642. .send = zynq_gem_send,
  643. .recv = zynq_gem_recv,
  644. .free_pkt = zynq_gem_free_pkt,
  645. .stop = zynq_gem_halt,
  646. .write_hwaddr = zynq_gem_setup_mac,
  647. .read_rom_hwaddr = zynq_gem_read_rom_mac,
  648. };
  649. static int zynq_gem_of_to_plat(struct udevice *dev)
  650. {
  651. struct eth_pdata *pdata = dev_get_plat(dev);
  652. struct zynq_gem_priv *priv = dev_get_priv(dev);
  653. struct ofnode_phandle_args phandle_args;
  654. const char *phy_mode;
  655. pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  656. priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
  657. priv->mdiobase = priv->iobase;
  658. /* Hardcode for now */
  659. priv->phyaddr = -1;
  660. if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  661. &phandle_args)) {
  662. fdt_addr_t addr;
  663. ofnode parent;
  664. debug("phy-handle does exist %s\n", dev->name);
  665. priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
  666. "reg", -1);
  667. priv->phy_of_node = phandle_args.node;
  668. priv->max_speed = ofnode_read_u32_default(phandle_args.node,
  669. "max-speed",
  670. SPEED_1000);
  671. parent = ofnode_get_parent(phandle_args.node);
  672. addr = ofnode_get_addr(parent);
  673. if (addr != FDT_ADDR_T_NONE) {
  674. debug("MDIO bus not found %s\n", dev->name);
  675. priv->mdiobase = (struct zynq_gem_regs *)addr;
  676. }
  677. }
  678. phy_mode = dev_read_prop(dev, "phy-mode", NULL);
  679. if (phy_mode)
  680. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  681. if (pdata->phy_interface == -1) {
  682. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  683. return -EINVAL;
  684. }
  685. priv->interface = pdata->phy_interface;
  686. priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
  687. printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
  688. (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
  689. phy_string_for_interface(priv->interface));
  690. priv->clk_en_info = dev_get_driver_data(dev);
  691. return 0;
  692. }
  693. static const struct udevice_id zynq_gem_ids[] = {
  694. { .compatible = "cdns,versal-gem", .data = RXCLK_EN },
  695. { .compatible = "cdns,zynqmp-gem" },
  696. { .compatible = "cdns,zynq-gem" },
  697. { .compatible = "cdns,gem" },
  698. { }
  699. };
  700. U_BOOT_DRIVER(zynq_gem) = {
  701. .name = "zynq_gem",
  702. .id = UCLASS_ETH,
  703. .of_match = zynq_gem_ids,
  704. .of_to_plat = zynq_gem_of_to_plat,
  705. .probe = zynq_gem_probe,
  706. .remove = zynq_gem_remove,
  707. .ops = &zynq_gem_ops,
  708. .priv_auto = sizeof(struct zynq_gem_priv),
  709. .plat_auto = sizeof(struct eth_pdata),
  710. };