xilinx_emaclite.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2009 Michal Simek
  4. * (C) Copyright 2003 Xilinx Inc.
  5. *
  6. * Michal SIMEK <monstr@monstr.eu>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <net.h>
  11. #include <config.h>
  12. #include <dm.h>
  13. #include <console.h>
  14. #include <malloc.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <phy.h>
  18. #include <miiphy.h>
  19. #include <fdtdec.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <linux/kernel.h>
  23. #include <asm/io.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define ENET_ADDR_LENGTH 6
  26. #define ETH_FCS_LEN 4 /* Octets in the FCS */
  27. /* Xmit complete */
  28. #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
  29. /* Xmit interrupt enable bit */
  30. #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
  31. /* Program the MAC address */
  32. #define XEL_TSR_PROGRAM_MASK 0x00000002UL
  33. /* define for programming the MAC address into the EMAC Lite */
  34. #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
  35. /* Transmit packet length upper byte */
  36. #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
  37. /* Transmit packet length lower byte */
  38. #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
  39. /* Recv complete */
  40. #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
  41. /* Recv interrupt enable bit */
  42. #define XEL_RSR_RECV_IE_MASK 0x00000008UL
  43. /* MDIO Address Register Bit Masks */
  44. #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
  45. #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
  46. #define XEL_MDIOADDR_PHYADR_SHIFT 5
  47. #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
  48. /* MDIO Write Data Register Bit Masks */
  49. #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
  50. /* MDIO Read Data Register Bit Masks */
  51. #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
  52. /* MDIO Control Register Bit Masks */
  53. #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
  54. #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
  55. struct emaclite_regs {
  56. u32 tx_ping; /* 0x0 - TX Ping buffer */
  57. u32 reserved1[504];
  58. u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
  59. u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
  60. u32 mdiord;/* 0x7ec - MDIO Read Data Register */
  61. u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
  62. u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
  63. u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
  64. u32 tx_ping_tsr; /* 0x7fc - Tx status */
  65. u32 tx_pong; /* 0x800 - TX Pong buffer */
  66. u32 reserved2[508];
  67. u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
  68. u32 reserved3; /* 0xff8 */
  69. u32 tx_pong_tsr; /* 0xffc - Tx status */
  70. u32 rx_ping; /* 0x1000 - Receive Buffer */
  71. u32 reserved4[510];
  72. u32 rx_ping_rsr; /* 0x17fc - Rx status */
  73. u32 rx_pong; /* 0x1800 - Receive Buffer */
  74. u32 reserved5[510];
  75. u32 rx_pong_rsr; /* 0x1ffc - Rx status */
  76. };
  77. struct xemaclite {
  78. bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
  79. u32 txpp; /* TX ping pong buffer */
  80. u32 rxpp; /* RX ping pong buffer */
  81. int phyaddr;
  82. struct emaclite_regs *regs;
  83. struct phy_device *phydev;
  84. struct mii_dev *bus;
  85. };
  86. static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
  87. static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
  88. {
  89. u32 i;
  90. u32 alignbuffer;
  91. u32 *to32ptr;
  92. u32 *from32ptr;
  93. u8 *to8ptr;
  94. u8 *from8ptr;
  95. from32ptr = (u32 *) srcptr;
  96. /* Word aligned buffer, no correction needed. */
  97. to32ptr = (u32 *) destptr;
  98. while (bytecount > 3) {
  99. *to32ptr++ = *from32ptr++;
  100. bytecount -= 4;
  101. }
  102. to8ptr = (u8 *) to32ptr;
  103. alignbuffer = *from32ptr++;
  104. from8ptr = (u8 *) &alignbuffer;
  105. for (i = 0; i < bytecount; i++)
  106. *to8ptr++ = *from8ptr++;
  107. }
  108. static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
  109. {
  110. u32 i;
  111. u32 alignbuffer;
  112. u32 *to32ptr = (u32 *) destptr;
  113. u32 *from32ptr;
  114. u8 *to8ptr;
  115. u8 *from8ptr;
  116. from32ptr = (u32 *) srcptr;
  117. while (bytecount > 3) {
  118. *to32ptr++ = *from32ptr++;
  119. bytecount -= 4;
  120. }
  121. alignbuffer = 0;
  122. to8ptr = (u8 *) &alignbuffer;
  123. from8ptr = (u8 *) from32ptr;
  124. for (i = 0; i < bytecount; i++)
  125. *to8ptr++ = *from8ptr++;
  126. *to32ptr++ = alignbuffer;
  127. }
  128. static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
  129. bool set, unsigned int timeout)
  130. {
  131. u32 val;
  132. unsigned long start = get_timer(0);
  133. while (1) {
  134. val = __raw_readl(reg);
  135. if (!set)
  136. val = ~val;
  137. if ((val & mask) == mask)
  138. return 0;
  139. if (get_timer(start) > timeout)
  140. break;
  141. if (ctrlc()) {
  142. puts("Abort\n");
  143. return -EINTR;
  144. }
  145. udelay(1);
  146. }
  147. debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  148. func, reg, mask, set);
  149. return -ETIMEDOUT;
  150. }
  151. static int mdio_wait(struct emaclite_regs *regs)
  152. {
  153. return wait_for_bit(__func__, &regs->mdioctrl,
  154. XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
  155. }
  156. static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
  157. u16 *data)
  158. {
  159. struct emaclite_regs *regs = emaclite->regs;
  160. if (mdio_wait(regs))
  161. return 1;
  162. u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
  163. __raw_writel(XEL_MDIOADDR_OP_MASK
  164. | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
  165. | registernum), &regs->mdioaddr);
  166. __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
  167. if (mdio_wait(regs))
  168. return 1;
  169. /* Read data */
  170. *data = __raw_readl(&regs->mdiord);
  171. return 0;
  172. }
  173. static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
  174. u16 data)
  175. {
  176. struct emaclite_regs *regs = emaclite->regs;
  177. if (mdio_wait(regs))
  178. return 1;
  179. /*
  180. * Write the PHY address, register number and clear the OP bit in the
  181. * MDIO Address register and then write the value into the MDIO Write
  182. * Data register. Finally, set the Status bit in the MDIO Control
  183. * register to start a MDIO write transaction.
  184. */
  185. u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
  186. __raw_writel(~XEL_MDIOADDR_OP_MASK
  187. & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
  188. | registernum), &regs->mdioaddr);
  189. __raw_writel(data, &regs->mdiowr);
  190. __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
  191. if (mdio_wait(regs))
  192. return 1;
  193. return 0;
  194. }
  195. static void emaclite_stop(struct udevice *dev)
  196. {
  197. debug("eth_stop\n");
  198. }
  199. /* Use MII register 1 (MII status register) to detect PHY */
  200. #define PHY_DETECT_REG 1
  201. /* Mask used to verify certain PHY features (or register contents)
  202. * in the register above:
  203. * 0x1000: 10Mbps full duplex support
  204. * 0x0800: 10Mbps half duplex support
  205. * 0x0008: Auto-negotiation support
  206. */
  207. #define PHY_DETECT_MASK 0x1808
  208. static int setup_phy(struct udevice *dev)
  209. {
  210. int i, ret;
  211. u16 phyreg;
  212. struct xemaclite *emaclite = dev_get_priv(dev);
  213. struct phy_device *phydev;
  214. u32 supported = SUPPORTED_10baseT_Half |
  215. SUPPORTED_10baseT_Full |
  216. SUPPORTED_100baseT_Half |
  217. SUPPORTED_100baseT_Full;
  218. if (emaclite->phyaddr != -1) {
  219. phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
  220. if ((phyreg != 0xFFFF) &&
  221. ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  222. /* Found a valid PHY address */
  223. debug("Default phy address %d is valid\n",
  224. emaclite->phyaddr);
  225. } else {
  226. debug("PHY address is not setup correctly %d\n",
  227. emaclite->phyaddr);
  228. emaclite->phyaddr = -1;
  229. }
  230. }
  231. if (emaclite->phyaddr == -1) {
  232. /* detect the PHY address */
  233. for (i = 31; i >= 0; i--) {
  234. phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
  235. if ((phyreg != 0xFFFF) &&
  236. ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  237. /* Found a valid PHY address */
  238. emaclite->phyaddr = i;
  239. debug("emaclite: Found valid phy address, %d\n",
  240. i);
  241. break;
  242. }
  243. }
  244. }
  245. /* interface - look at tsec */
  246. phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
  247. PHY_INTERFACE_MODE_MII);
  248. /*
  249. * Phy can support 1000baseT but device NOT that's why phydev->supported
  250. * must be setup for 1000baseT. phydev->advertising setups what speeds
  251. * will be used for autonegotiation where 1000baseT must be disabled.
  252. */
  253. phydev->supported = supported | SUPPORTED_1000baseT_Half |
  254. SUPPORTED_1000baseT_Full;
  255. phydev->advertising = supported;
  256. emaclite->phydev = phydev;
  257. phy_config(phydev);
  258. ret = phy_startup(phydev);
  259. if (ret)
  260. return ret;
  261. if (!phydev->link) {
  262. printf("%s: No link.\n", phydev->dev->name);
  263. return 0;
  264. }
  265. /* Do not setup anything */
  266. return 1;
  267. }
  268. static int emaclite_start(struct udevice *dev)
  269. {
  270. struct xemaclite *emaclite = dev_get_priv(dev);
  271. struct eth_pdata *pdata = dev_get_plat(dev);
  272. struct emaclite_regs *regs = emaclite->regs;
  273. debug("EmacLite Initialization Started\n");
  274. /*
  275. * TX - TX_PING & TX_PONG initialization
  276. */
  277. /* Restart PING TX */
  278. __raw_writel(0, &regs->tx_ping_tsr);
  279. /* Copy MAC address */
  280. xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
  281. ENET_ADDR_LENGTH);
  282. /* Set the length */
  283. __raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
  284. /* Update the MAC address in the EMAC Lite */
  285. __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
  286. /* Wait for EMAC Lite to finish with the MAC address update */
  287. while ((__raw_readl(&regs->tx_ping_tsr) &
  288. XEL_TSR_PROG_MAC_ADDR) != 0)
  289. ;
  290. if (emaclite->txpp) {
  291. /* The same operation with PONG TX */
  292. __raw_writel(0, &regs->tx_pong_tsr);
  293. xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
  294. ENET_ADDR_LENGTH);
  295. __raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
  296. __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
  297. while ((__raw_readl(&regs->tx_pong_tsr) &
  298. XEL_TSR_PROG_MAC_ADDR) != 0)
  299. ;
  300. }
  301. /*
  302. * RX - RX_PING & RX_PONG initialization
  303. */
  304. /* Write out the value to flush the RX buffer */
  305. __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
  306. if (emaclite->rxpp)
  307. __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
  308. __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
  309. if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
  310. if (!setup_phy(dev))
  311. return -1;
  312. debug("EmacLite Initialization complete\n");
  313. return 0;
  314. }
  315. static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
  316. {
  317. u32 tmp;
  318. struct emaclite_regs *regs = emaclite->regs;
  319. /*
  320. * Read the other buffer register
  321. * and determine if the other buffer is available
  322. */
  323. tmp = ~__raw_readl(&regs->tx_ping_tsr);
  324. if (emaclite->txpp)
  325. tmp |= ~__raw_readl(&regs->tx_pong_tsr);
  326. return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
  327. }
  328. static int emaclite_send(struct udevice *dev, void *ptr, int len)
  329. {
  330. u32 reg;
  331. struct xemaclite *emaclite = dev_get_priv(dev);
  332. struct emaclite_regs *regs = emaclite->regs;
  333. u32 maxtry = 1000;
  334. if (len > PKTSIZE)
  335. len = PKTSIZE;
  336. while (xemaclite_txbufferavailable(emaclite) && maxtry) {
  337. udelay(10);
  338. maxtry--;
  339. }
  340. if (!maxtry) {
  341. printf("Error: Timeout waiting for ethernet TX buffer\n");
  342. /* Restart PING TX */
  343. __raw_writel(0, &regs->tx_ping_tsr);
  344. if (emaclite->txpp) {
  345. __raw_writel(0, &regs->tx_pong_tsr);
  346. }
  347. return -1;
  348. }
  349. /* Determine if the expected buffer address is empty */
  350. reg = __raw_readl(&regs->tx_ping_tsr);
  351. if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
  352. debug("Send packet from tx_ping buffer\n");
  353. /* Write the frame to the buffer */
  354. xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
  355. __raw_writel(len
  356. & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
  357. &regs->tx_ping_tplr);
  358. reg = __raw_readl(&regs->tx_ping_tsr);
  359. reg |= XEL_TSR_XMIT_BUSY_MASK;
  360. __raw_writel(reg, &regs->tx_ping_tsr);
  361. return 0;
  362. }
  363. if (emaclite->txpp) {
  364. /* Determine if the expected buffer address is empty */
  365. reg = __raw_readl(&regs->tx_pong_tsr);
  366. if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
  367. debug("Send packet from tx_pong buffer\n");
  368. /* Write the frame to the buffer */
  369. xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
  370. __raw_writel(len &
  371. (XEL_TPLR_LENGTH_MASK_HI |
  372. XEL_TPLR_LENGTH_MASK_LO),
  373. &regs->tx_pong_tplr);
  374. reg = __raw_readl(&regs->tx_pong_tsr);
  375. reg |= XEL_TSR_XMIT_BUSY_MASK;
  376. __raw_writel(reg, &regs->tx_pong_tsr);
  377. return 0;
  378. }
  379. }
  380. puts("Error while sending frame\n");
  381. return -1;
  382. }
  383. static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
  384. {
  385. u32 length, first_read, reg, attempt = 0;
  386. void *addr, *ack;
  387. struct xemaclite *emaclite = dev_get_priv(dev);
  388. struct emaclite_regs *regs = emaclite->regs;
  389. struct ethernet_hdr *eth;
  390. struct ip_udp_hdr *ip;
  391. try_again:
  392. if (!emaclite->use_rx_pong_buffer_next) {
  393. reg = __raw_readl(&regs->rx_ping_rsr);
  394. debug("Testing data at rx_ping\n");
  395. if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
  396. debug("Data found in rx_ping buffer\n");
  397. addr = &regs->rx_ping;
  398. ack = &regs->rx_ping_rsr;
  399. } else {
  400. debug("Data not found in rx_ping buffer\n");
  401. /* Pong buffer is not available - return immediately */
  402. if (!emaclite->rxpp)
  403. return -1;
  404. /* Try pong buffer if this is first attempt */
  405. if (attempt++)
  406. return -1;
  407. emaclite->use_rx_pong_buffer_next =
  408. !emaclite->use_rx_pong_buffer_next;
  409. goto try_again;
  410. }
  411. } else {
  412. reg = __raw_readl(&regs->rx_pong_rsr);
  413. debug("Testing data at rx_pong\n");
  414. if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
  415. debug("Data found in rx_pong buffer\n");
  416. addr = &regs->rx_pong;
  417. ack = &regs->rx_pong_rsr;
  418. } else {
  419. debug("Data not found in rx_pong buffer\n");
  420. /* Try ping buffer if this is first attempt */
  421. if (attempt++)
  422. return -1;
  423. emaclite->use_rx_pong_buffer_next =
  424. !emaclite->use_rx_pong_buffer_next;
  425. goto try_again;
  426. }
  427. }
  428. /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
  429. first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
  430. xemaclite_alignedread(addr, etherrxbuff, first_read);
  431. /* Detect real packet size */
  432. eth = (struct ethernet_hdr *)etherrxbuff;
  433. switch (ntohs(eth->et_protlen)) {
  434. case PROT_ARP:
  435. length = first_read;
  436. debug("ARP Packet %x\n", length);
  437. break;
  438. case PROT_IP:
  439. ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
  440. length = ntohs(ip->ip_len);
  441. length += ETHER_HDR_SIZE + ETH_FCS_LEN;
  442. debug("IP Packet %x\n", length);
  443. break;
  444. default:
  445. debug("Other Packet\n");
  446. length = PKTSIZE;
  447. break;
  448. }
  449. /* Read the rest of the packet which is longer then first read */
  450. if (length != first_read)
  451. xemaclite_alignedread(addr + first_read,
  452. etherrxbuff + first_read,
  453. length - first_read);
  454. /* Acknowledge the frame */
  455. reg = __raw_readl(ack);
  456. reg &= ~XEL_RSR_RECV_DONE_MASK;
  457. __raw_writel(reg, ack);
  458. debug("Packet receive from 0x%p, length %dB\n", addr, length);
  459. *packetp = etherrxbuff;
  460. return length;
  461. }
  462. static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
  463. int devad, int reg)
  464. {
  465. u32 ret;
  466. u16 val = 0;
  467. ret = phyread(bus->priv, addr, reg, &val);
  468. debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
  469. return val;
  470. }
  471. static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
  472. int reg, u16 value)
  473. {
  474. debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
  475. return phywrite(bus->priv, addr, reg, value);
  476. }
  477. static int emaclite_probe(struct udevice *dev)
  478. {
  479. struct xemaclite *emaclite = dev_get_priv(dev);
  480. int ret;
  481. emaclite->bus = mdio_alloc();
  482. emaclite->bus->read = emaclite_miiphy_read;
  483. emaclite->bus->write = emaclite_miiphy_write;
  484. emaclite->bus->priv = emaclite;
  485. ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
  486. if (ret)
  487. return ret;
  488. return 0;
  489. }
  490. static int emaclite_remove(struct udevice *dev)
  491. {
  492. struct xemaclite *emaclite = dev_get_priv(dev);
  493. free(emaclite->phydev);
  494. mdio_unregister(emaclite->bus);
  495. mdio_free(emaclite->bus);
  496. return 0;
  497. }
  498. static const struct eth_ops emaclite_ops = {
  499. .start = emaclite_start,
  500. .send = emaclite_send,
  501. .recv = emaclite_recv,
  502. .stop = emaclite_stop,
  503. };
  504. static int emaclite_of_to_plat(struct udevice *dev)
  505. {
  506. struct eth_pdata *pdata = dev_get_plat(dev);
  507. struct xemaclite *emaclite = dev_get_priv(dev);
  508. int offset = 0;
  509. pdata->iobase = dev_read_addr(dev);
  510. emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
  511. 0x10000);
  512. emaclite->phyaddr = -1;
  513. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  514. "phy-handle");
  515. if (offset > 0)
  516. emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
  517. "reg", -1);
  518. emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  519. "xlnx,tx-ping-pong", 0);
  520. emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  521. "xlnx,rx-ping-pong", 0);
  522. printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
  523. emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
  524. return 0;
  525. }
  526. static const struct udevice_id emaclite_ids[] = {
  527. { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
  528. { }
  529. };
  530. U_BOOT_DRIVER(emaclite) = {
  531. .name = "emaclite",
  532. .id = UCLASS_ETH,
  533. .of_match = emaclite_ids,
  534. .of_to_plat = emaclite_of_to_plat,
  535. .probe = emaclite_probe,
  536. .remove = emaclite_remove,
  537. .ops = &emaclite_ops,
  538. .priv_auto = sizeof(struct xemaclite),
  539. .plat_auto = sizeof(struct eth_pdata),
  540. };