xilinx_axi_mrmac.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Xilinx Multirate Ethernet MAC(MRMAC) driver
  4. *
  5. * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
  6. * Michal Simek <michal.simek@xilinx.com>
  7. *
  8. * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
  9. */
  10. #ifndef __XILINX_AXI_MRMAC_H
  11. #define __XILINX_AXI_MRMAC_H
  12. #define MIN_PKT_SIZE 60
  13. /* MRMAC needs atleast two buffer descriptors for Tx/Rx to work.
  14. * Otherwise MRMAC will drop the packets. So, have atleast two Tx and
  15. * two Rx bd's.
  16. */
  17. #define TX_DESC 2
  18. #define RX_DESC 2
  19. /* MRMAC platform data structure */
  20. struct axi_mrmac_plat {
  21. struct eth_pdata eth_pdata;
  22. struct mcdma_common_regs *mm2s_cmn;
  23. u32 mrmac_rate; /* Hold the value from DT property "mrmac-rate" */
  24. };
  25. /* MRMAC private driver structure */
  26. struct axi_mrmac_priv {
  27. struct mrmac_regs *iobase;
  28. struct mcdma_common_regs *mm2s_cmn;
  29. struct mcdma_common_regs *s2mm_cmn;
  30. struct mcdma_chan_reg *mcdma_tx;
  31. struct mcdma_chan_reg *mcdma_rx;
  32. struct mcdma_bd *tx_bd[TX_DESC];
  33. struct mcdma_bd *rx_bd[RX_DESC];
  34. u8 *txminframe; /* Pointer to hold min length Tx frame(60) */
  35. u32 mrmac_rate; /* Speed to configure(Read from DT 10G/25G..) */
  36. };
  37. /* MRMAC Register Definitions */
  38. struct mrmac_regs {
  39. u32 revision; /* 0x0: Revision Register */
  40. u32 reset; /* 0x4: Reset Register */
  41. u32 mode; /* 0x8: Mode */
  42. u32 tx_config; /* 0xc: Tx Configuration */
  43. u32 rx_config; /* 0x10: Rx Configuration */
  44. u32 reserved[6];/* 0x14-0x28: Reserved */
  45. u32 tick_reg; /* 0x2c: Tick Register */
  46. };
  47. #define TX_BD_TOTAL_SIZE (TX_DESC * sizeof(struct mcdma_bd))
  48. #define RX_BD_TOTAL_SIZE (RX_DESC * sizeof(struct mcdma_bd))
  49. #define RX_BUFF_TOTAL_SIZE (RX_DESC * PKTSIZE_ALIGN)
  50. /* Status Registers */
  51. #define MRMAC_TX_STS_OFFSET 0x740
  52. #define MRMAC_RX_STS_OFFSET 0x744
  53. #define MRMAC_TX_RT_STS_OFFSET 0x748
  54. #define MRMAC_RX_RT_STS_OFFSET 0x74c
  55. #define MRMAC_STATRX_BLKLCK_OFFSET 0x754
  56. /* Register bit masks */
  57. #define MRMAC_RX_SERDES_RST_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0))
  58. #define MRMAC_TX_SERDES_RST_MASK BIT(4)
  59. #define MRMAC_RX_RST_MASK BIT(5)
  60. #define MRMAC_TX_RST_MASK BIT(6)
  61. #define MRMAC_RX_AXI_RST_MASK BIT(8)
  62. #define MRMAC_TX_AXI_RST_MASK BIT(9)
  63. #define MRMAC_STS_ALL_MASK 0xffffffff
  64. #define MRMAC_RX_EN_MASK BIT(0)
  65. #define MRMAC_RX_DEL_FCS_MASK BIT(1)
  66. #define MRMAC_TX_EN_MASK BIT(0)
  67. #define MRMAC_TX_INS_FCS_MASK BIT(1)
  68. #define MRMAC_RX_BLKLCK_MASK BIT(0)
  69. #define MRMAC_TICK_TRIGGER BIT(0)
  70. #define MRMAC_RESET_DELAY 1 /* Delay in msecs */
  71. #define MRMAC_BLKLCK_TIMEOUT 100 /* Block lock timeout in msecs */
  72. #define MRMAC_DMARST_TIMEOUT 500 /* MCDMA reset timeout in msecs */
  73. #define XMCDMA_RX_OFFSET 0x500
  74. #define XMCDMA_CHAN_OFFSET 0x40
  75. /* MCDMA Channel numbers are from 1-16 */
  76. #define XMCDMA_CHANNEL_1 BIT(0)
  77. #define XMCDMA_CHANNEL_2 BIT(1)
  78. #define XMCDMA_CR_RUNSTOP BIT(0)
  79. #define XMCDMA_CR_RESET BIT(2)
  80. #define XMCDMA_BD_CTRL_TXSOF_MASK BIT(31) /* First tx packet */
  81. #define XMCDMA_BD_CTRL_TXEOF_MASK BIT(30) /* Last tx packet */
  82. #define XMCDMA_BD_CTRL_ALL_MASK GENMASK(31, 30) /* All control bits */
  83. #define XMCDMA_BD_STS_ALL_MASK GENMASK(31, 28) /* All status bits */
  84. /* MCDMA Mask registers */
  85. #define XMCDMA_CR_RUNSTOP_MASK BIT(0) /* Start/stop DMA channel */
  86. #define XMCDMA_CR_RESET_MASK BIT(2) /* Reset DMA engine */
  87. #define XMCDMA_SR_HALTED_MASK BIT(0)
  88. #define XMCDMA_SR_IDLE_MASK BIT(1)
  89. #define XMCDMA_CH_IDLE BIT(0)
  90. #define XMCDMA_BD_STS_COMPLETE BIT(31) /* Completed */
  91. #define XMCDMA_BD_STS_DEC_ERR BIT(20) /* Decode error */
  92. #define XMCDMA_BD_STS_SLV_ERR BIT(29) /* Slave error */
  93. #define XMCDMA_BD_STS_INT_ERR BIT(28) /* Internal err */
  94. #define XMCDMA_BD_STS_ALL_ERR GENMASK(30, 28) /* All errors */
  95. #define XMCDMA_IRQ_ERRON_OTHERQ_MASK BIT(3)
  96. #define XMCDMA_IRQ_PKTDROP_MASK BIT(4)
  97. #define XMCDMA_IRQ_IOC_MASK BIT(5)
  98. #define XMCDMA_IRQ_DELAY_MASK BIT(6)
  99. #define XMCDMA_IRQ_ERR_MASK BIT(7)
  100. #define XMCDMA_IRQ_ALL_MASK GENMASK(7, 5)
  101. #define XMCDMA_PKTDROP_COALESCE_MASK GENMASK(15, 8)
  102. #define XMCDMA_COALESCE_MASK GENMASK(23, 16)
  103. #define XMCDMA_DELAY_MASK GENMASK(31, 24)
  104. #define MRMAC_CTL_DATA_RATE_MASK GENMASK(2, 0)
  105. #define MRMAC_CTL_DATA_RATE_10G 0
  106. #define MRMAC_CTL_DATA_RATE_25G 1
  107. #define MRMAC_CTL_DATA_RATE_40G 2
  108. #define MRMAC_CTL_DATA_RATE_50G 3
  109. #define MRMAC_CTL_DATA_RATE_100G 4
  110. #define MRMAC_CTL_AXIS_CFG_MASK GENMASK(11, 9)
  111. #define MRMAC_CTL_AXIS_CFG_SHIFT 9
  112. #define MRMAC_CTL_AXIS_CFG_10G_IND 1
  113. #define MRMAC_CTL_AXIS_CFG_25G_IND 1
  114. #define MRMAC_CTL_SERDES_WIDTH_MASK GENMASK(6, 4)
  115. #define MRMAC_CTL_SERDES_WIDTH_SHIFT 4
  116. #define MRMAC_CTL_SERDES_WIDTH_10G 4
  117. #define MRMAC_CTL_SERDES_WIDTH_25G 6
  118. #define MRMAC_CTL_RATE_CFG_MASK (MRMAC_CTL_DATA_RATE_MASK | \
  119. MRMAC_CTL_AXIS_CFG_MASK | \
  120. MRMAC_CTL_SERDES_WIDTH_MASK)
  121. #define MRMAC_CTL_PM_TICK_MASK BIT(30)
  122. #define MRMAC_TICK_TRIGGER BIT(0)
  123. #define XMCDMA_BD_STS_ACTUAL_LEN_MASK 0x007fffff /* Actual length */
  124. /* MCDMA common offsets */
  125. struct mcdma_common_regs {
  126. u32 control; /* Common control */
  127. u32 status; /* Common status */
  128. u32 chen; /* Channel enable/disable */
  129. u32 chser; /* Channel in progress */
  130. u32 err; /* Error */
  131. u32 ch_schd_type; /* Channel Q scheduler type */
  132. u32 wrr_reg1; /* Weight of each channel (ch1-8) */
  133. u32 wrr_reg2; /* Weight of each channel (ch9-16) */
  134. u32 ch_serviced; /* Channels completed */
  135. u32 arcache_aruser; /* ARCACHE and ARUSER values for AXI4 read */
  136. u32 intr_status; /* Interrupt monitor */
  137. u32 reserved[5];
  138. };
  139. /* MCDMA per-channel registers */
  140. struct mcdma_chan_reg {
  141. u32 control; /* Control */
  142. u32 status; /* Status */
  143. u32 current; /* Current descriptor */
  144. u32 current_hi; /* Current descriptor high 32bit */
  145. u32 tail; /* Tail descriptor */
  146. u32 tail_hi; /* Tail descriptor high 32bit */
  147. u32 pktcnt; /* Packet processed count */
  148. };
  149. /* MCDMA buffer descriptors */
  150. struct mcdma_bd {
  151. u32 next_desc; /* Next descriptor pointer */
  152. u32 next_desc_msb;
  153. u32 buf_addr; /* Buffer address */
  154. u32 buf_addr_msb;
  155. u32 reserved1;
  156. u32 cntrl; /* Control */
  157. u32 status; /* Status */
  158. u32 sband_stats;
  159. u32 app0;
  160. u32 app1; /* Tx start << 16 | insert */
  161. u32 app2; /* Tx csum seed */
  162. u32 app3;
  163. u32 app4;
  164. u32 sw_id_offset;
  165. u32 reserved2;
  166. u32 reserved3;
  167. u32 reserved4[16];
  168. };
  169. #endif /* __XILINX_AXI_MRMAC_H */