uli526x.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
  6. *
  7. * Description:
  8. * ULI 526x Ethernet port driver.
  9. * Based on the Linux driver: drivers/net/tulip/uli526x.c
  10. */
  11. #include <common.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <asm/io.h>
  16. #include <pci.h>
  17. #include <miiphy.h>
  18. #include <linux/delay.h>
  19. /* some kernel function compatible define */
  20. #undef DEBUG
  21. /* Board/System/Debug information/definition */
  22. #define ULI_VENDOR_ID 0x10B9
  23. #define ULI5261_DEVICE_ID 0x5261
  24. #define ULI5263_DEVICE_ID 0x5263
  25. /* ULi M5261 ID*/
  26. #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
  27. /* ULi M5263 ID*/
  28. #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
  29. #define ULI526X_IO_SIZE 0x100
  30. #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
  31. #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
  32. #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
  33. #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
  34. #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
  35. #define TX_BUF_ALLOC 0x300
  36. #define RX_ALLOC_SIZE PKTSIZE
  37. #define ULI526X_RESET 1
  38. #define CR0_DEFAULT 0
  39. #define CR6_DEFAULT 0x22200000
  40. #define CR7_DEFAULT 0x180c1
  41. #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
  42. #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
  43. #define MAX_PACKET_SIZE 1514
  44. #define ULI5261_MAX_MULTICAST 14
  45. #define RX_COPY_SIZE 100
  46. #define MAX_CHECK_PACKET 0x8000
  47. #define ULI526X_10MHF 0
  48. #define ULI526X_100MHF 1
  49. #define ULI526X_10MFD 4
  50. #define ULI526X_100MFD 5
  51. #define ULI526X_AUTO 8
  52. #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
  53. #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
  54. #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
  55. #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
  56. #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
  57. #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
  58. /* CR9 definition: SROM/MII */
  59. #define CR9_SROM_READ 0x4800
  60. #define CR9_SRCS 0x1
  61. #define CR9_SRCLK 0x2
  62. #define CR9_CRDOUT 0x8
  63. #define SROM_DATA_0 0x0
  64. #define SROM_DATA_1 0x4
  65. #define PHY_DATA_1 0x20000
  66. #define PHY_DATA_0 0x00000
  67. #define MDCLKH 0x10000
  68. #define PHY_POWER_DOWN 0x800
  69. #define SROM_V41_CODE 0x14
  70. #define SROM_CLK_WRITE(data, ioaddr) do { \
  71. outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
  72. udelay(5); \
  73. outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
  74. udelay(5); \
  75. outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
  76. udelay(5); \
  77. } while (0)
  78. /* Structure/enum declaration */
  79. struct tx_desc {
  80. u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
  81. char *tx_buf_ptr; /* Data for us */
  82. struct tx_desc *next_tx_desc;
  83. };
  84. struct rx_desc {
  85. u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
  86. char *rx_buf_ptr; /* Data for us */
  87. struct rx_desc *next_rx_desc;
  88. };
  89. struct uli526x_board_info {
  90. u32 chip_id; /* Chip vendor/Device ID */
  91. pci_dev_t pdev;
  92. long ioaddr; /* I/O base address */
  93. u32 cr0_data;
  94. u32 cr5_data;
  95. u32 cr6_data;
  96. u32 cr7_data;
  97. u32 cr15_data;
  98. /* pointer for memory physical address */
  99. dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
  100. dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
  101. dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
  102. dma_addr_t first_tx_desc_dma;
  103. dma_addr_t first_rx_desc_dma;
  104. /* descriptor pointer */
  105. unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
  106. unsigned char *buf_pool_start; /* Tx buffer pool align dword */
  107. unsigned char *desc_pool_ptr; /* descriptor pool memory */
  108. struct tx_desc *first_tx_desc;
  109. struct tx_desc *tx_insert_ptr;
  110. struct tx_desc *tx_remove_ptr;
  111. struct rx_desc *first_rx_desc;
  112. struct rx_desc *rx_ready_ptr; /* packet come pointer */
  113. unsigned long tx_packet_cnt; /* transmitted packet count */
  114. u16 PHY_reg4; /* Saved Phyxcer register 4 value */
  115. u8 media_mode; /* user specify media mode */
  116. u8 op_mode; /* real work dedia mode */
  117. u8 phy_addr;
  118. /* NIC SROM data */
  119. unsigned char srom[128];
  120. };
  121. enum uli526x_offsets {
  122. DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
  123. DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
  124. DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
  125. DCR15 = 0x78
  126. };
  127. enum uli526x_CR6_bits {
  128. CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
  129. CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
  130. CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
  131. };
  132. /* Global variable declaration -- */
  133. static unsigned char uli526x_media_mode = ULI526X_AUTO;
  134. static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
  135. __attribute__ ((aligned(32)));
  136. static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
  137. /* For module input parameter */
  138. static int mode = 8;
  139. /* function declaration -- */
  140. static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
  141. static u16 read_srom_word(long, int);
  142. static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
  143. static void allocate_rx_buffer(struct uli526x_board_info *);
  144. static void update_cr6(u32, unsigned long);
  145. static u16 uli_phy_read(unsigned long, u8, u8, u32);
  146. static u16 phy_readby_cr10(unsigned long, u8, u8);
  147. static void uli_phy_write(unsigned long, u8, u8, u16, u32);
  148. static void phy_writeby_cr10(unsigned long, u8, u8, u16);
  149. static void phy_write_1bit(unsigned long, u32, u32);
  150. static u16 phy_read_1bit(unsigned long, u32);
  151. static int uli526x_rx_packet(struct eth_device *);
  152. static void uli526x_free_tx_pkt(struct eth_device *,
  153. struct uli526x_board_info *);
  154. static void uli526x_reuse_buf(struct rx_desc *);
  155. static void uli526x_init(struct eth_device *);
  156. static void uli526x_set_phyxcer(struct uli526x_board_info *);
  157. static int uli526x_init_one(struct eth_device *, struct bd_info *);
  158. static void uli526x_disable(struct eth_device *);
  159. static void set_mac_addr(struct eth_device *);
  160. static struct pci_device_id uli526x_pci_tbl[] = {
  161. { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
  162. { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
  163. {}
  164. };
  165. /* ULI526X network board routine */
  166. /*
  167. * Search ULI526X board, register it
  168. */
  169. int uli526x_initialize(struct bd_info *bis)
  170. {
  171. pci_dev_t devno;
  172. int card_number = 0;
  173. struct eth_device *dev;
  174. struct uli526x_board_info *db; /* board information structure */
  175. u32 iobase;
  176. int idx = 0;
  177. while (1) {
  178. /* Find PCI device */
  179. devno = pci_find_devices(uli526x_pci_tbl, idx++);
  180. if (devno < 0)
  181. break;
  182. pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
  183. iobase &= ~0xf;
  184. dev = (struct eth_device *)malloc(sizeof *dev);
  185. if (!dev) {
  186. printf("uli526x: Can not allocate memory\n");
  187. break;
  188. }
  189. memset(dev, 0, sizeof(*dev));
  190. sprintf(dev->name, "uli526x#%d", card_number);
  191. db = (struct uli526x_board_info *)
  192. malloc(sizeof(struct uli526x_board_info));
  193. dev->priv = db;
  194. db->pdev = devno;
  195. dev->iobase = iobase;
  196. dev->init = uli526x_init_one;
  197. dev->halt = uli526x_disable;
  198. dev->send = uli526x_start_xmit;
  199. dev->recv = uli526x_rx_packet;
  200. /* init db */
  201. db->ioaddr = dev->iobase;
  202. /* get chip id */
  203. pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
  204. #ifdef DEBUG
  205. printf("uli526x: uli526x @0x%x\n", iobase);
  206. printf("uli526x: chip_id%x\n", db->chip_id);
  207. #endif
  208. eth_register(dev);
  209. card_number++;
  210. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  211. udelay(10 * 1000);
  212. }
  213. return card_number;
  214. }
  215. static int uli526x_init_one(struct eth_device *dev, struct bd_info *bis)
  216. {
  217. struct uli526x_board_info *db = dev->priv;
  218. int i;
  219. switch (mode) {
  220. case ULI526X_10MHF:
  221. case ULI526X_100MHF:
  222. case ULI526X_10MFD:
  223. case ULI526X_100MFD:
  224. uli526x_media_mode = mode;
  225. break;
  226. default:
  227. uli526x_media_mode = ULI526X_AUTO;
  228. break;
  229. }
  230. /* Allocate Tx/Rx descriptor memory */
  231. db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
  232. db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
  233. if (db->desc_pool_ptr == NULL)
  234. return -1;
  235. db->buf_pool_ptr = (uchar *)&buf_pool[0];
  236. db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
  237. if (db->buf_pool_ptr == NULL)
  238. return -1;
  239. db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
  240. db->first_tx_desc_dma = db->desc_pool_dma_ptr;
  241. db->buf_pool_start = db->buf_pool_ptr;
  242. db->buf_pool_dma_start = db->buf_pool_dma_ptr;
  243. #ifdef DEBUG
  244. printf("%s(): db->ioaddr= 0x%x\n",
  245. __FUNCTION__, db->ioaddr);
  246. printf("%s(): media_mode= 0x%x\n",
  247. __FUNCTION__, uli526x_media_mode);
  248. printf("%s(): db->desc_pool_ptr= 0x%x\n",
  249. __FUNCTION__, db->desc_pool_ptr);
  250. printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
  251. __FUNCTION__, db->desc_pool_dma_ptr);
  252. printf("%s(): db->buf_pool_ptr= 0x%x\n",
  253. __FUNCTION__, db->buf_pool_ptr);
  254. printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
  255. __FUNCTION__, db->buf_pool_dma_ptr);
  256. #endif
  257. /* read 64 word srom data */
  258. for (i = 0; i < 64; i++)
  259. ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
  260. i));
  261. /* Set Node address */
  262. if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
  263. ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
  264. /* SROM absent, so write MAC address to ID Table */
  265. set_mac_addr(dev);
  266. else { /*Exist SROM*/
  267. for (i = 0; i < 6; i++)
  268. dev->enetaddr[i] = db->srom[20 + i];
  269. }
  270. #ifdef DEBUG
  271. for (i = 0; i < 6; i++)
  272. printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
  273. #endif
  274. db->PHY_reg4 = 0x1e0;
  275. /* system variable init */
  276. db->cr6_data = CR6_DEFAULT ;
  277. db->cr6_data |= ULI526X_TXTH_256;
  278. db->cr0_data = CR0_DEFAULT;
  279. uli526x_init(dev);
  280. return 0;
  281. }
  282. static void uli526x_disable(struct eth_device *dev)
  283. {
  284. #ifdef DEBUG
  285. printf("uli526x_disable\n");
  286. #endif
  287. struct uli526x_board_info *db = dev->priv;
  288. if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
  289. /* Reset & stop ULI526X board */
  290. outl(ULI526X_RESET, db->ioaddr + DCR0);
  291. udelay(5);
  292. uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
  293. /* reset the board */
  294. db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
  295. update_cr6(db->cr6_data, dev->iobase);
  296. outl(0, dev->iobase + DCR7); /* Disable Interrupt */
  297. outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
  298. }
  299. }
  300. /* Initialize ULI526X board
  301. * Reset ULI526X board
  302. * Initialize TX/Rx descriptor chain structure
  303. * Send the set-up frame
  304. * Enable Tx/Rx machine
  305. */
  306. static void uli526x_init(struct eth_device *dev)
  307. {
  308. struct uli526x_board_info *db = dev->priv;
  309. u8 phy_tmp;
  310. u16 phy_value;
  311. u16 phy_reg_reset;
  312. /* Reset M526x MAC controller */
  313. outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
  314. udelay(100);
  315. outl(db->cr0_data, db->ioaddr + DCR0);
  316. udelay(5);
  317. /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
  318. db->phy_addr = 1;
  319. db->tx_packet_cnt = 0;
  320. for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
  321. /* peer add */
  322. phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
  323. if (phy_value != 0xffff && phy_value != 0) {
  324. db->phy_addr = phy_tmp;
  325. break;
  326. }
  327. }
  328. #ifdef DEBUG
  329. printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
  330. printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
  331. #endif
  332. if (phy_tmp == 32)
  333. printf("Can not find the phy address!!!");
  334. /* Parser SROM and media mode */
  335. db->media_mode = uli526x_media_mode;
  336. if (!(inl(db->ioaddr + DCR12) & 0x8)) {
  337. /* Phyxcer capability setting */
  338. phy_reg_reset = uli_phy_read(db->ioaddr,
  339. db->phy_addr, 0, db->chip_id);
  340. phy_reg_reset = (phy_reg_reset | 0x8000);
  341. uli_phy_write(db->ioaddr, db->phy_addr, 0,
  342. phy_reg_reset, db->chip_id);
  343. udelay(500);
  344. /* Process Phyxcer Media Mode */
  345. uli526x_set_phyxcer(db);
  346. }
  347. /* Media Mode Process */
  348. if (!(db->media_mode & ULI526X_AUTO))
  349. db->op_mode = db->media_mode; /* Force Mode */
  350. /* Initialize Transmit/Receive decriptor and CR3/4 */
  351. uli526x_descriptor_init(db, db->ioaddr);
  352. /* Init CR6 to program M526X operation */
  353. update_cr6(db->cr6_data, db->ioaddr);
  354. /* Init CR7, interrupt active bit */
  355. db->cr7_data = CR7_DEFAULT;
  356. outl(db->cr7_data, db->ioaddr + DCR7);
  357. /* Init CR15, Tx jabber and Rx watchdog timer */
  358. outl(db->cr15_data, db->ioaddr + DCR15);
  359. /* Enable ULI526X Tx/Rx function */
  360. db->cr6_data |= CR6_RXSC | CR6_TXSC;
  361. update_cr6(db->cr6_data, db->ioaddr);
  362. while (!(inl(db->ioaddr + DCR12) & 0x8))
  363. udelay(10);
  364. }
  365. /*
  366. * Hardware start transmission.
  367. * Send a packet to media from the upper layer.
  368. */
  369. static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
  370. {
  371. struct uli526x_board_info *db = dev->priv;
  372. struct tx_desc *txptr;
  373. unsigned int len = length;
  374. /* Too large packet check */
  375. if (len > MAX_PACKET_SIZE) {
  376. printf(": big packet = %d\n", len);
  377. return 0;
  378. }
  379. /* No Tx resource check, it never happen nromally */
  380. if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
  381. printf("No Tx resource %ld\n", db->tx_packet_cnt);
  382. return 0;
  383. }
  384. /* Disable NIC interrupt */
  385. outl(0, dev->iobase + DCR7);
  386. /* transmit this packet */
  387. txptr = db->tx_insert_ptr;
  388. memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
  389. txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
  390. /* Point to next transmit free descriptor */
  391. db->tx_insert_ptr = txptr->next_tx_desc;
  392. /* Transmit Packet Process */
  393. if ((db->tx_packet_cnt < TX_DESC_CNT)) {
  394. txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
  395. db->tx_packet_cnt++; /* Ready to send */
  396. outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
  397. }
  398. /* Got ULI526X status */
  399. db->cr5_data = inl(db->ioaddr + DCR5);
  400. outl(db->cr5_data, db->ioaddr + DCR5);
  401. #ifdef TX_DEBUG
  402. printf("%s(): length = 0x%x\n", __FUNCTION__, length);
  403. printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
  404. #endif
  405. outl(db->cr7_data, dev->iobase + DCR7);
  406. uli526x_free_tx_pkt(dev, db);
  407. return length;
  408. }
  409. /*
  410. * Free TX resource after TX complete
  411. */
  412. static void uli526x_free_tx_pkt(struct eth_device *dev,
  413. struct uli526x_board_info *db)
  414. {
  415. struct tx_desc *txptr;
  416. u32 tdes0;
  417. txptr = db->tx_remove_ptr;
  418. while (db->tx_packet_cnt) {
  419. tdes0 = le32_to_cpu(txptr->tdes0);
  420. /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
  421. if (tdes0 & 0x80000000)
  422. break;
  423. /* A packet sent completed */
  424. db->tx_packet_cnt--;
  425. if (tdes0 != 0x7fffffff) {
  426. #ifdef TX_DEBUG
  427. printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
  428. #endif
  429. if (tdes0 & TDES0_ERR_MASK) {
  430. if (tdes0 & 0x0002) { /* UnderRun */
  431. if (!(db->cr6_data & CR6_SFT)) {
  432. db->cr6_data = db->cr6_data |
  433. CR6_SFT;
  434. update_cr6(db->cr6_data,
  435. db->ioaddr);
  436. }
  437. }
  438. }
  439. }
  440. txptr = txptr->next_tx_desc;
  441. }/* End of while */
  442. /* Update TX remove pointer to next */
  443. db->tx_remove_ptr = txptr;
  444. }
  445. /*
  446. * Receive the come packet and pass to upper layer
  447. */
  448. static int uli526x_rx_packet(struct eth_device *dev)
  449. {
  450. struct uli526x_board_info *db = dev->priv;
  451. struct rx_desc *rxptr;
  452. int rxlen = 0;
  453. u32 rdes0;
  454. rxptr = db->rx_ready_ptr;
  455. rdes0 = le32_to_cpu(rxptr->rdes0);
  456. #ifdef RX_DEBUG
  457. printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
  458. #endif
  459. if (!(rdes0 & 0x80000000)) { /* packet owner check */
  460. if ((rdes0 & 0x300) != 0x300) {
  461. /* A packet without First/Last flag */
  462. /* reuse this buf */
  463. printf("A packet without First/Last flag");
  464. uli526x_reuse_buf(rxptr);
  465. } else {
  466. /* A packet with First/Last flag */
  467. rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
  468. #ifdef RX_DEBUG
  469. printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
  470. #endif
  471. /* error summary bit check */
  472. if (rdes0 & 0x8000) {
  473. /* This is a error packet */
  474. printf("Error: rdes0: %x\n", rdes0);
  475. }
  476. if (!(rdes0 & 0x8000) ||
  477. ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
  478. #ifdef RX_DEBUG
  479. printf("%s(): rx_skb_ptr =%x\n",
  480. __FUNCTION__, rxptr->rx_buf_ptr);
  481. printf("%s(): rxlen =%x\n",
  482. __FUNCTION__, rxlen);
  483. printf("%s(): buf addr =%x\n",
  484. __FUNCTION__, rxptr->rx_buf_ptr);
  485. printf("%s(): rxlen =%x\n",
  486. __FUNCTION__, rxlen);
  487. int i;
  488. for (i = 0; i < 0x20; i++)
  489. printf("%s(): data[%x] =%x\n",
  490. __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
  491. #endif
  492. net_process_received_packet(
  493. (uchar *)rxptr->rx_buf_ptr, rxlen);
  494. uli526x_reuse_buf(rxptr);
  495. } else {
  496. /* Reuse SKB buffer when the packet is error */
  497. printf("Reuse buffer, rdes0");
  498. uli526x_reuse_buf(rxptr);
  499. }
  500. }
  501. rxptr = rxptr->next_rx_desc;
  502. }
  503. db->rx_ready_ptr = rxptr;
  504. return rxlen;
  505. }
  506. /*
  507. * Reuse the RX buffer
  508. */
  509. static void uli526x_reuse_buf(struct rx_desc *rxptr)
  510. {
  511. if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
  512. rxptr->rdes0 = cpu_to_le32(0x80000000);
  513. else
  514. printf("Buffer reuse method error");
  515. }
  516. /*
  517. * Initialize transmit/Receive descriptor
  518. * Using Chain structure, and allocate Tx/Rx buffer
  519. */
  520. static void uli526x_descriptor_init(struct uli526x_board_info *db,
  521. unsigned long ioaddr)
  522. {
  523. struct tx_desc *tmp_tx;
  524. struct rx_desc *tmp_rx;
  525. unsigned char *tmp_buf;
  526. dma_addr_t tmp_tx_dma, tmp_rx_dma;
  527. dma_addr_t tmp_buf_dma;
  528. int i;
  529. /* tx descriptor start pointer */
  530. db->tx_insert_ptr = db->first_tx_desc;
  531. db->tx_remove_ptr = db->first_tx_desc;
  532. outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
  533. /* rx descriptor start pointer */
  534. db->first_rx_desc = (void *)db->first_tx_desc +
  535. sizeof(struct tx_desc) * TX_DESC_CNT;
  536. db->first_rx_desc_dma = db->first_tx_desc_dma +
  537. sizeof(struct tx_desc) * TX_DESC_CNT;
  538. db->rx_ready_ptr = db->first_rx_desc;
  539. outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
  540. #ifdef DEBUG
  541. printf("%s(): db->first_tx_desc= 0x%x\n",
  542. __FUNCTION__, db->first_tx_desc);
  543. printf("%s(): db->first_rx_desc_dma= 0x%x\n",
  544. __FUNCTION__, db->first_rx_desc_dma);
  545. #endif
  546. /* Init Transmit chain */
  547. tmp_buf = db->buf_pool_start;
  548. tmp_buf_dma = db->buf_pool_dma_start;
  549. tmp_tx_dma = db->first_tx_desc_dma;
  550. for (tmp_tx = db->first_tx_desc, i = 0;
  551. i < TX_DESC_CNT; i++, tmp_tx++) {
  552. tmp_tx->tx_buf_ptr = (char *)tmp_buf;
  553. tmp_tx->tdes0 = cpu_to_le32(0);
  554. tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
  555. tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
  556. tmp_tx_dma += sizeof(struct tx_desc);
  557. tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
  558. tmp_tx->next_tx_desc = tmp_tx + 1;
  559. tmp_buf = tmp_buf + TX_BUF_ALLOC;
  560. tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
  561. }
  562. (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
  563. tmp_tx->next_tx_desc = db->first_tx_desc;
  564. /* Init Receive descriptor chain */
  565. tmp_rx_dma = db->first_rx_desc_dma;
  566. for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
  567. i++, tmp_rx++) {
  568. tmp_rx->rdes0 = cpu_to_le32(0);
  569. tmp_rx->rdes1 = cpu_to_le32(0x01000600);
  570. tmp_rx_dma += sizeof(struct rx_desc);
  571. tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
  572. tmp_rx->next_rx_desc = tmp_rx + 1;
  573. }
  574. (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
  575. tmp_rx->next_rx_desc = db->first_rx_desc;
  576. /* pre-allocate Rx buffer */
  577. allocate_rx_buffer(db);
  578. }
  579. /*
  580. * Update CR6 value
  581. * Firstly stop ULI526X, then written value and start
  582. */
  583. static void update_cr6(u32 cr6_data, unsigned long ioaddr)
  584. {
  585. outl(cr6_data, ioaddr + DCR6);
  586. udelay(5);
  587. }
  588. /*
  589. * Allocate rx buffer,
  590. */
  591. static void allocate_rx_buffer(struct uli526x_board_info *db)
  592. {
  593. int index;
  594. struct rx_desc *rxptr;
  595. rxptr = db->first_rx_desc;
  596. u32 addr;
  597. for (index = 0; index < RX_DESC_CNT; index++) {
  598. addr = (u32)net_rx_packets[index];
  599. addr += (16 - (addr & 15));
  600. rxptr->rx_buf_ptr = (char *) addr;
  601. rxptr->rdes2 = cpu_to_le32(addr);
  602. rxptr->rdes0 = cpu_to_le32(0x80000000);
  603. #ifdef DEBUG
  604. printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
  605. printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
  606. printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
  607. printf("%s(): rxptr buf address = 0x%x\n", \
  608. __FUNCTION__, rxptr->rx_buf_ptr);
  609. printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
  610. #endif
  611. rxptr = rxptr->next_rx_desc;
  612. }
  613. }
  614. /*
  615. * Read one word data from the serial ROM
  616. */
  617. static u16 read_srom_word(long ioaddr, int offset)
  618. {
  619. int i;
  620. u16 srom_data = 0;
  621. long cr9_ioaddr = ioaddr + DCR9;
  622. outl(CR9_SROM_READ, cr9_ioaddr);
  623. outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
  624. /* Send the Read Command 110b */
  625. SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
  626. SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
  627. SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
  628. /* Send the offset */
  629. for (i = 5; i >= 0; i--) {
  630. srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
  631. SROM_CLK_WRITE(srom_data, cr9_ioaddr);
  632. }
  633. outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
  634. for (i = 16; i > 0; i--) {
  635. outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
  636. udelay(5);
  637. srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
  638. ? 1 : 0);
  639. outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
  640. udelay(5);
  641. }
  642. outl(CR9_SROM_READ, cr9_ioaddr);
  643. return srom_data;
  644. }
  645. /*
  646. * Set 10/100 phyxcer capability
  647. * AUTO mode : phyxcer register4 is NIC capability
  648. * Force mode: phyxcer register4 is the force media
  649. */
  650. static void uli526x_set_phyxcer(struct uli526x_board_info *db)
  651. {
  652. u16 phy_reg;
  653. /* Phyxcer capability setting */
  654. phy_reg = uli_phy_read(db->ioaddr,
  655. db->phy_addr, 4, db->chip_id) & ~0x01e0;
  656. if (db->media_mode & ULI526X_AUTO) {
  657. /* AUTO Mode */
  658. phy_reg |= db->PHY_reg4;
  659. } else {
  660. /* Force Mode */
  661. switch (db->media_mode) {
  662. case ULI526X_10MHF: phy_reg |= 0x20; break;
  663. case ULI526X_10MFD: phy_reg |= 0x40; break;
  664. case ULI526X_100MHF: phy_reg |= 0x80; break;
  665. case ULI526X_100MFD: phy_reg |= 0x100; break;
  666. }
  667. }
  668. /* Write new capability to Phyxcer Reg4 */
  669. if (!(phy_reg & 0x01e0)) {
  670. phy_reg |= db->PHY_reg4;
  671. db->media_mode |= ULI526X_AUTO;
  672. }
  673. uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
  674. /* Restart Auto-Negotiation */
  675. uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
  676. udelay(50);
  677. }
  678. /*
  679. * Write a word to Phy register
  680. */
  681. static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
  682. u16 phy_data, u32 chip_id)
  683. {
  684. u16 i;
  685. unsigned long ioaddr;
  686. if (chip_id == PCI_ULI5263_ID) {
  687. phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
  688. return;
  689. }
  690. /* M5261/M5263 Chip */
  691. ioaddr = iobase + DCR9;
  692. /* Send 33 synchronization clock to Phy controller */
  693. for (i = 0; i < 35; i++)
  694. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  695. /* Send start command(01) to Phy */
  696. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  697. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  698. /* Send write command(01) to Phy */
  699. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  700. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  701. /* Send Phy address */
  702. for (i = 0x10; i > 0; i = i >> 1)
  703. phy_write_1bit(ioaddr, phy_addr & i ?
  704. PHY_DATA_1 : PHY_DATA_0, chip_id);
  705. /* Send register address */
  706. for (i = 0x10; i > 0; i = i >> 1)
  707. phy_write_1bit(ioaddr, offset & i ?
  708. PHY_DATA_1 : PHY_DATA_0, chip_id);
  709. /* written trasnition */
  710. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  711. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  712. /* Write a word data to PHY controller */
  713. for (i = 0x8000; i > 0; i >>= 1)
  714. phy_write_1bit(ioaddr, phy_data & i ?
  715. PHY_DATA_1 : PHY_DATA_0, chip_id);
  716. }
  717. /*
  718. * Read a word data from phy register
  719. */
  720. static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
  721. u32 chip_id)
  722. {
  723. int i;
  724. u16 phy_data;
  725. unsigned long ioaddr;
  726. if (chip_id == PCI_ULI5263_ID)
  727. return phy_readby_cr10(iobase, phy_addr, offset);
  728. /* M5261/M5263 Chip */
  729. ioaddr = iobase + DCR9;
  730. /* Send 33 synchronization clock to Phy controller */
  731. for (i = 0; i < 35; i++)
  732. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  733. /* Send start command(01) to Phy */
  734. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  735. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  736. /* Send read command(10) to Phy */
  737. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  738. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  739. /* Send Phy address */
  740. for (i = 0x10; i > 0; i = i >> 1)
  741. phy_write_1bit(ioaddr, phy_addr & i ?
  742. PHY_DATA_1 : PHY_DATA_0, chip_id);
  743. /* Send register address */
  744. for (i = 0x10; i > 0; i = i >> 1)
  745. phy_write_1bit(ioaddr, offset & i ?
  746. PHY_DATA_1 : PHY_DATA_0, chip_id);
  747. /* Skip transition state */
  748. phy_read_1bit(ioaddr, chip_id);
  749. /* read 16bit data */
  750. for (phy_data = 0, i = 0; i < 16; i++) {
  751. phy_data <<= 1;
  752. phy_data |= phy_read_1bit(ioaddr, chip_id);
  753. }
  754. return phy_data;
  755. }
  756. static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
  757. {
  758. unsigned long ioaddr, cr10_value;
  759. ioaddr = iobase + DCR10;
  760. cr10_value = phy_addr;
  761. cr10_value = (cr10_value<<5) + offset;
  762. cr10_value = (cr10_value<<16) + 0x08000000;
  763. outl(cr10_value, ioaddr);
  764. udelay(1);
  765. while (1) {
  766. cr10_value = inl(ioaddr);
  767. if (cr10_value & 0x10000000)
  768. break;
  769. }
  770. return (cr10_value&0x0ffff);
  771. }
  772. static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
  773. u8 offset, u16 phy_data)
  774. {
  775. unsigned long ioaddr, cr10_value;
  776. ioaddr = iobase + DCR10;
  777. cr10_value = phy_addr;
  778. cr10_value = (cr10_value<<5) + offset;
  779. cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
  780. outl(cr10_value, ioaddr);
  781. udelay(1);
  782. }
  783. /*
  784. * Write one bit data to Phy Controller
  785. */
  786. static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
  787. {
  788. outl(phy_data , ioaddr); /* MII Clock Low */
  789. udelay(1);
  790. outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
  791. udelay(1);
  792. outl(phy_data , ioaddr); /* MII Clock Low */
  793. udelay(1);
  794. }
  795. /*
  796. * Read one bit phy data from PHY controller
  797. */
  798. static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
  799. {
  800. u16 phy_data;
  801. outl(0x50000 , ioaddr);
  802. udelay(1);
  803. phy_data = (inl(ioaddr) >> 19) & 0x1;
  804. outl(0x40000 , ioaddr);
  805. udelay(1);
  806. return phy_data;
  807. }
  808. /*
  809. * Set MAC address to ID Table
  810. */
  811. static void set_mac_addr(struct eth_device *dev)
  812. {
  813. int i;
  814. u16 addr;
  815. struct uli526x_board_info *db = dev->priv;
  816. outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
  817. /* Reset dianostic pointer port */
  818. outl(0x1c0, db->ioaddr + DCR13);
  819. outl(0, db->ioaddr + DCR14); /* Clear reset port */
  820. outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
  821. outl(0, db->ioaddr + DCR14); /* Clear reset port */
  822. outl(0, db->ioaddr + DCR13); /* Clear CR13 */
  823. /* Select ID Table access port */
  824. outl(0x1b0, db->ioaddr + DCR13);
  825. /* Read MAC address from CR14 */
  826. for (i = 0; i < 3; i++) {
  827. addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
  828. outl(addr, db->ioaddr + DCR14);
  829. }
  830. /* write end */
  831. outl(0, db->ioaddr + DCR13); /* Clear CR13 */
  832. outl(0, db->ioaddr + DCR0); /* Clear CR0 */
  833. udelay(10);
  834. return;
  835. }