davinci_emac.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
  4. *
  5. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6. *
  7. * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
  8. * follows:
  9. *
  10. * ----------------------------------------------------------------------------
  11. *
  12. * dm644x_emac.c
  13. *
  14. * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
  15. *
  16. * Copyright (C) 2005 Texas Instruments.
  17. *
  18. * ----------------------------------------------------------------------------
  19. *
  20. * Modifications:
  21. * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
  22. * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
  23. */
  24. #include <common.h>
  25. #include <command.h>
  26. #include <cpu_func.h>
  27. #include <log.h>
  28. #include <net.h>
  29. #include <miiphy.h>
  30. #include <malloc.h>
  31. #include <asm/cache.h>
  32. #include <linux/compiler.h>
  33. #include <asm/arch/emac_defs.h>
  34. #include <asm/io.h>
  35. #include <linux/delay.h>
  36. #include "davinci_emac.h"
  37. unsigned int emac_dbg = 0;
  38. #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
  39. #ifdef EMAC_HW_RAM_ADDR
  40. static inline unsigned long BD_TO_HW(unsigned long x)
  41. {
  42. if (x == 0)
  43. return 0;
  44. return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
  45. }
  46. static inline unsigned long HW_TO_BD(unsigned long x)
  47. {
  48. if (x == 0)
  49. return 0;
  50. return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
  51. }
  52. #else
  53. #define BD_TO_HW(x) (x)
  54. #define HW_TO_BD(x) (x)
  55. #endif
  56. #ifdef DAVINCI_EMAC_GIG_ENABLE
  57. #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
  58. #else
  59. #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
  60. #endif
  61. #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
  62. #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
  63. EMAC_MDIO_CLOCK_FREQ) - 1)
  64. #endif
  65. static void davinci_eth_mdio_enable(void);
  66. static int gen_init_phy(int phy_addr);
  67. static int gen_is_phy_connected(int phy_addr);
  68. static int gen_get_link_speed(int phy_addr);
  69. static int gen_auto_negotiate(int phy_addr);
  70. void eth_mdio_enable(void)
  71. {
  72. davinci_eth_mdio_enable();
  73. }
  74. /* EMAC Addresses */
  75. static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
  76. static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
  77. static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
  78. /* EMAC descriptors */
  79. static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
  80. static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  81. static volatile emac_desc *emac_rx_active_head = 0;
  82. static volatile emac_desc *emac_rx_active_tail = 0;
  83. static int emac_rx_queue_active = 0;
  84. /* Receive packet buffers */
  85. static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
  86. __aligned(ARCH_DMA_MINALIGN);
  87. #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
  88. #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
  89. #endif
  90. /* PHY address for a discovered PHY (0xff - not found) */
  91. static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
  92. /* number of PHY found active */
  93. static u_int8_t num_phy;
  94. phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
  95. static int davinci_emac_write_hwaddr(struct udevice *dev)
  96. {
  97. struct eth_pdata *pdata = dev_get_plat(dev);
  98. unsigned long mac_hi;
  99. unsigned long mac_lo;
  100. /*
  101. * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
  102. * receive)
  103. * Using channel 0 only - other channels are disabled
  104. * */
  105. writel(0, &adap_emac->MACINDEX);
  106. mac_hi = (pdata->enetaddr[3] << 24) |
  107. (pdata->enetaddr[2] << 16) |
  108. (pdata->enetaddr[1] << 8) |
  109. (pdata->enetaddr[0]);
  110. mac_lo = (pdata->enetaddr[5] << 8) |
  111. (pdata->enetaddr[4]);
  112. writel(mac_hi, &adap_emac->MACADDRHI);
  113. #if defined(DAVINCI_EMAC_VERSION2)
  114. writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
  115. &adap_emac->MACADDRLO);
  116. #else
  117. writel(mac_lo, &adap_emac->MACADDRLO);
  118. #endif
  119. writel(0, &adap_emac->MACHASH1);
  120. writel(0, &adap_emac->MACHASH2);
  121. /* Set source MAC address - REQUIRED */
  122. writel(mac_hi, &adap_emac->MACSRCADDRHI);
  123. writel(mac_lo, &adap_emac->MACSRCADDRLO);
  124. return 0;
  125. }
  126. static void davinci_eth_mdio_enable(void)
  127. {
  128. u_int32_t clkdiv;
  129. clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
  130. writel((clkdiv & 0xff) |
  131. MDIO_CONTROL_ENABLE |
  132. MDIO_CONTROL_FAULT |
  133. MDIO_CONTROL_FAULT_ENABLE,
  134. &adap_mdio->CONTROL);
  135. while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
  136. ;
  137. }
  138. /*
  139. * Tries to find an active connected PHY. Returns 1 if address if found.
  140. * If no active PHY (or more than one PHY) found returns 0.
  141. * Sets active_phy_addr variable.
  142. */
  143. static int davinci_eth_phy_detect(void)
  144. {
  145. u_int32_t phy_act_state;
  146. int i;
  147. int j;
  148. unsigned int count = 0;
  149. for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
  150. active_phy_addr[i] = 0xff;
  151. udelay(1000);
  152. phy_act_state = readl(&adap_mdio->ALIVE);
  153. if (phy_act_state == 0)
  154. return 0; /* No active PHYs */
  155. debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
  156. for (i = 0, j = 0; i < 32; i++)
  157. if (phy_act_state & (1 << i)) {
  158. count++;
  159. if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
  160. active_phy_addr[j++] = i;
  161. } else {
  162. printf("%s: to many PHYs detected.\n",
  163. __func__);
  164. count = 0;
  165. break;
  166. }
  167. }
  168. num_phy = count;
  169. return count;
  170. }
  171. /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
  172. int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
  173. {
  174. int tmp;
  175. while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
  176. ;
  177. writel(MDIO_USERACCESS0_GO |
  178. MDIO_USERACCESS0_WRITE_READ |
  179. ((reg_num & 0x1f) << 21) |
  180. ((phy_addr & 0x1f) << 16),
  181. &adap_mdio->USERACCESS0);
  182. /* Wait for command to complete */
  183. while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
  184. ;
  185. if (tmp & MDIO_USERACCESS0_ACK) {
  186. *data = tmp & 0xffff;
  187. return 1;
  188. }
  189. return 0;
  190. }
  191. /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
  192. int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
  193. {
  194. while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
  195. ;
  196. writel(MDIO_USERACCESS0_GO |
  197. MDIO_USERACCESS0_WRITE_WRITE |
  198. ((reg_num & 0x1f) << 21) |
  199. ((phy_addr & 0x1f) << 16) |
  200. (data & 0xffff),
  201. &adap_mdio->USERACCESS0);
  202. /* Wait for command to complete */
  203. while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
  204. ;
  205. return 1;
  206. }
  207. /* PHY functions for a generic PHY */
  208. static int gen_init_phy(int phy_addr)
  209. {
  210. int ret = 1;
  211. if (gen_get_link_speed(phy_addr)) {
  212. /* Try another time */
  213. ret = gen_get_link_speed(phy_addr);
  214. }
  215. return(ret);
  216. }
  217. static int gen_is_phy_connected(int phy_addr)
  218. {
  219. u_int16_t dummy;
  220. return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
  221. }
  222. static int get_active_phy(void)
  223. {
  224. int i;
  225. for (i = 0; i < num_phy; i++)
  226. if (phy[i].get_link_speed(active_phy_addr[i]))
  227. return i;
  228. return -1; /* Return error if no link */
  229. }
  230. static int gen_get_link_speed(int phy_addr)
  231. {
  232. u_int16_t tmp;
  233. if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
  234. (tmp & 0x04)) {
  235. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  236. defined(CONFIG_MACH_DAVINCI_DA850_EVM)
  237. davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
  238. /* Speed doesn't matter, there is no setting for it in EMAC. */
  239. if (tmp & (LPA_100FULL | LPA_10FULL)) {
  240. /* set EMAC for Full Duplex */
  241. writel(EMAC_MACCONTROL_MIIEN_ENABLE |
  242. EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
  243. &adap_emac->MACCONTROL);
  244. } else {
  245. /*set EMAC for Half Duplex */
  246. writel(EMAC_MACCONTROL_MIIEN_ENABLE,
  247. &adap_emac->MACCONTROL);
  248. }
  249. if (tmp & (LPA_100FULL | LPA_100HALF))
  250. writel(readl(&adap_emac->MACCONTROL) |
  251. EMAC_MACCONTROL_RMIISPEED_100,
  252. &adap_emac->MACCONTROL);
  253. else
  254. writel(readl(&adap_emac->MACCONTROL) &
  255. ~EMAC_MACCONTROL_RMIISPEED_100,
  256. &adap_emac->MACCONTROL);
  257. #endif
  258. return(1);
  259. }
  260. return(0);
  261. }
  262. static int gen_auto_negotiate(int phy_addr)
  263. {
  264. u_int16_t tmp;
  265. u_int16_t val;
  266. unsigned long cntr = 0;
  267. if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
  268. return 0;
  269. val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
  270. BMCR_SPEED100;
  271. davinci_eth_phy_write(phy_addr, MII_BMCR, val);
  272. if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
  273. return 0;
  274. val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
  275. ADVERTISE_10HALF);
  276. davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
  277. if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
  278. return(0);
  279. #ifdef DAVINCI_EMAC_GIG_ENABLE
  280. davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
  281. val |= PHY_1000BTCR_1000FD;
  282. val &= ~PHY_1000BTCR_1000HD;
  283. davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
  284. davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
  285. #endif
  286. /* Restart Auto_negotiation */
  287. tmp |= BMCR_ANRESTART;
  288. davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
  289. /*check AutoNegotiate complete */
  290. do {
  291. udelay(40000);
  292. if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
  293. return 0;
  294. if (tmp & BMSR_ANEGCOMPLETE)
  295. break;
  296. cntr++;
  297. } while (cntr < 200);
  298. if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
  299. return(0);
  300. if (!(tmp & BMSR_ANEGCOMPLETE))
  301. return(0);
  302. return(gen_get_link_speed(phy_addr));
  303. }
  304. /* End of generic PHY functions */
  305. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  306. static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
  307. int reg)
  308. {
  309. unsigned short value = 0;
  310. int retval = davinci_eth_phy_read(addr, reg, &value);
  311. return retval ? value : -EIO;
  312. }
  313. static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
  314. int reg, u16 value)
  315. {
  316. return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
  317. }
  318. #endif
  319. static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
  320. {
  321. u_int16_t data;
  322. if (davinci_eth_phy_read(phy_addr, 0, &data)) {
  323. if (data & (1 << 6)) { /* speed selection MSB */
  324. /*
  325. * Check if link detected is giga-bit
  326. * If Gigabit mode detected, enable gigbit in MAC
  327. */
  328. writel(readl(&adap_emac->MACCONTROL) |
  329. EMAC_MACCONTROL_GIGFORCE |
  330. EMAC_MACCONTROL_GIGABIT_ENABLE,
  331. &adap_emac->MACCONTROL);
  332. }
  333. }
  334. }
  335. /* Eth device open */
  336. static int davinci_emac_start(struct udevice *dev)
  337. {
  338. dv_reg_p addr;
  339. u_int32_t clkdiv, cnt, mac_control;
  340. uint16_t __maybe_unused lpa_val;
  341. volatile emac_desc *rx_desc;
  342. int index;
  343. debug_emac("+ emac_open\n");
  344. /* Reset EMAC module and disable interrupts in wrapper */
  345. writel(1, &adap_emac->SOFTRESET);
  346. while (readl(&adap_emac->SOFTRESET) != 0)
  347. ;
  348. #if defined(DAVINCI_EMAC_VERSION2)
  349. writel(1, &adap_ewrap->softrst);
  350. while (readl(&adap_ewrap->softrst) != 0)
  351. ;
  352. #else
  353. writel(0, &adap_ewrap->EWCTL);
  354. for (cnt = 0; cnt < 5; cnt++) {
  355. clkdiv = readl(&adap_ewrap->EWCTL);
  356. }
  357. #endif
  358. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  359. defined(CONFIG_MACH_DAVINCI_DA850_EVM)
  360. adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
  361. adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
  362. adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
  363. #endif
  364. rx_desc = emac_rx_desc;
  365. writel(1, &adap_emac->TXCONTROL);
  366. writel(1, &adap_emac->RXCONTROL);
  367. davinci_emac_write_hwaddr(dev);
  368. /* Set DMA 8 TX / 8 RX Head pointers to 0 */
  369. addr = &adap_emac->TX0HDP;
  370. for (cnt = 0; cnt < 8; cnt++)
  371. writel(0, addr++);
  372. addr = &adap_emac->RX0HDP;
  373. for (cnt = 0; cnt < 8; cnt++)
  374. writel(0, addr++);
  375. /* Clear Statistics (do this before setting MacControl register) */
  376. addr = &adap_emac->RXGOODFRAMES;
  377. for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
  378. writel(0, addr++);
  379. /* No multicast addressing */
  380. writel(0, &adap_emac->MACHASH1);
  381. writel(0, &adap_emac->MACHASH2);
  382. /* Create RX queue and set receive process in place */
  383. emac_rx_active_head = emac_rx_desc;
  384. for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
  385. rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
  386. rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
  387. rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
  388. rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
  389. rx_desc++;
  390. }
  391. /* Finalize the rx desc list */
  392. rx_desc--;
  393. rx_desc->next = 0;
  394. emac_rx_active_tail = rx_desc;
  395. emac_rx_queue_active = 1;
  396. /* Enable TX/RX */
  397. writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
  398. writel(0, &adap_emac->RXBUFFEROFFSET);
  399. /*
  400. * No fancy configs - Use this for promiscous debug
  401. * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
  402. */
  403. writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
  404. /* Enable ch 0 only */
  405. writel(1, &adap_emac->RXUNICASTSET);
  406. /* Init MDIO & get link state */
  407. clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
  408. writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
  409. &adap_mdio->CONTROL);
  410. /* We need to wait for MDIO to start */
  411. udelay(1000);
  412. index = get_active_phy();
  413. if (index == -1)
  414. return(0);
  415. /* Enable MII interface */
  416. mac_control = EMAC_MACCONTROL_MIIEN_ENABLE;
  417. #ifdef DAVINCI_EMAC_GIG_ENABLE
  418. davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val);
  419. if (lpa_val & PHY_1000BTSR_1000FD) {
  420. debug_emac("eth_open : gigabit negotiated\n");
  421. mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
  422. mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE;
  423. }
  424. #endif
  425. davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val);
  426. if (lpa_val & (LPA_100FULL | LPA_10FULL))
  427. /* set EMAC for Full Duplex */
  428. mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
  429. #if defined(CONFIG_SOC_DA8XX) || \
  430. (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
  431. mac_control |= EMAC_MACCONTROL_RMIISPEED_100;
  432. #endif
  433. writel(mac_control, &adap_emac->MACCONTROL);
  434. /* Start receive process */
  435. writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
  436. debug_emac("- emac_open\n");
  437. return(1);
  438. }
  439. /* EMAC Channel Teardown */
  440. static void davinci_eth_ch_teardown(int ch)
  441. {
  442. dv_reg dly = 0xff;
  443. dv_reg cnt;
  444. debug_emac("+ emac_ch_teardown\n");
  445. if (ch == EMAC_CH_TX) {
  446. /* Init TX channel teardown */
  447. writel(0, &adap_emac->TXTEARDOWN);
  448. do {
  449. /*
  450. * Wait here for Tx teardown completion interrupt to
  451. * occur. Note: A task delay can be called here to pend
  452. * rather than occupying CPU cycles - anyway it has
  453. * been found that teardown takes very few cpu cycles
  454. * and does not affect functionality
  455. */
  456. dly--;
  457. udelay(1);
  458. if (dly == 0)
  459. break;
  460. cnt = readl(&adap_emac->TX0CP);
  461. } while (cnt != 0xfffffffc);
  462. writel(cnt, &adap_emac->TX0CP);
  463. writel(0, &adap_emac->TX0HDP);
  464. } else {
  465. /* Init RX channel teardown */
  466. writel(0, &adap_emac->RXTEARDOWN);
  467. do {
  468. /*
  469. * Wait here for Rx teardown completion interrupt to
  470. * occur. Note: A task delay can be called here to pend
  471. * rather than occupying CPU cycles - anyway it has
  472. * been found that teardown takes very few cpu cycles
  473. * and does not affect functionality
  474. */
  475. dly--;
  476. udelay(1);
  477. if (dly == 0)
  478. break;
  479. cnt = readl(&adap_emac->RX0CP);
  480. } while (cnt != 0xfffffffc);
  481. writel(cnt, &adap_emac->RX0CP);
  482. writel(0, &adap_emac->RX0HDP);
  483. }
  484. debug_emac("- emac_ch_teardown\n");
  485. }
  486. /* Eth device close */
  487. static void davinci_emac_stop(struct udevice *dev)
  488. {
  489. debug_emac("+ emac_close\n");
  490. davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
  491. if (readl(&adap_emac->RXCONTROL) & 1)
  492. davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
  493. /* Reset EMAC module and disable interrupts in wrapper */
  494. writel(1, &adap_emac->SOFTRESET);
  495. #if defined(DAVINCI_EMAC_VERSION2)
  496. writel(1, &adap_ewrap->softrst);
  497. #else
  498. writel(0, &adap_ewrap->EWCTL);
  499. #endif
  500. #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  501. defined(CONFIG_MACH_DAVINCI_DA850_EVM)
  502. adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
  503. adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
  504. adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
  505. #endif
  506. debug_emac("- emac_close\n");
  507. }
  508. static int tx_send_loop = 0;
  509. /*
  510. * This function sends a single packet on the network and returns
  511. * positive number (number of bytes transmitted) or negative for error
  512. */
  513. static int davinci_emac_send(struct udevice *dev,
  514. void *packet, int length)
  515. {
  516. int ret_status = -1;
  517. int index;
  518. tx_send_loop = 0;
  519. index = get_active_phy();
  520. if (index == -1) {
  521. printf(" WARN: emac_send_packet: No link\n");
  522. return (ret_status);
  523. }
  524. /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
  525. if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
  526. length = EMAC_MIN_ETHERNET_PKT_SIZE;
  527. }
  528. /* Populate the TX descriptor */
  529. emac_tx_desc->next = 0;
  530. emac_tx_desc->buffer = (u_int8_t *) packet;
  531. emac_tx_desc->buff_off_len = (length & 0xffff);
  532. emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
  533. EMAC_CPPI_SOP_BIT |
  534. EMAC_CPPI_OWNERSHIP_BIT |
  535. EMAC_CPPI_EOP_BIT);
  536. flush_dcache_range((unsigned long)packet,
  537. (unsigned long)packet + ALIGN(length, PKTALIGN));
  538. /* Send the packet */
  539. writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
  540. /* Wait for packet to complete or link down */
  541. while (1) {
  542. if (!phy[index].get_link_speed(active_phy_addr[index])) {
  543. davinci_eth_ch_teardown (EMAC_CH_TX);
  544. return (ret_status);
  545. }
  546. if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
  547. ret_status = length;
  548. break;
  549. }
  550. tx_send_loop++;
  551. }
  552. return (ret_status);
  553. }
  554. /*
  555. * This function handles receipt of a packet from the network
  556. */
  557. static int davinci_emac_recv(struct udevice *dev, int flags, uchar **packetp)
  558. {
  559. volatile emac_desc *rx_curr_desc;
  560. volatile emac_desc *curr_desc;
  561. volatile emac_desc *tail_desc;
  562. int status, ret = -1;
  563. rx_curr_desc = emac_rx_active_head;
  564. if (!rx_curr_desc)
  565. return 0;
  566. *packetp = rx_curr_desc->buffer;
  567. status = rx_curr_desc->pkt_flag_len;
  568. if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
  569. if (status & EMAC_CPPI_RX_ERROR_FRAME) {
  570. /* Error in packet - discard it and requeue desc */
  571. printf ("WARN: emac_rcv_pkt: Error in packet\n");
  572. } else {
  573. unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
  574. unsigned short len =
  575. rx_curr_desc->buff_off_len & 0xffff;
  576. invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
  577. ret = len;
  578. }
  579. /* Ack received packet descriptor */
  580. writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
  581. curr_desc = rx_curr_desc;
  582. emac_rx_active_head =
  583. (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
  584. if (status & EMAC_CPPI_EOQ_BIT) {
  585. if (emac_rx_active_head) {
  586. writel(BD_TO_HW((ulong)emac_rx_active_head),
  587. &adap_emac->RX0HDP);
  588. } else {
  589. emac_rx_queue_active = 0;
  590. printf ("INFO:emac_rcv_packet: RX Queue not active\n");
  591. }
  592. }
  593. /* Recycle RX descriptor */
  594. rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
  595. rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
  596. rx_curr_desc->next = 0;
  597. if (emac_rx_active_head == 0) {
  598. printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
  599. emac_rx_active_head = curr_desc;
  600. emac_rx_active_tail = curr_desc;
  601. if (emac_rx_queue_active != 0) {
  602. writel(BD_TO_HW((ulong)emac_rx_active_head),
  603. &adap_emac->RX0HDP);
  604. printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
  605. emac_rx_queue_active = 1;
  606. }
  607. } else {
  608. tail_desc = emac_rx_active_tail;
  609. emac_rx_active_tail = curr_desc;
  610. tail_desc->next = BD_TO_HW((ulong) curr_desc);
  611. status = tail_desc->pkt_flag_len;
  612. if (status & EMAC_CPPI_EOQ_BIT) {
  613. writel(BD_TO_HW((ulong)curr_desc),
  614. &adap_emac->RX0HDP);
  615. status &= ~EMAC_CPPI_EOQ_BIT;
  616. tail_desc->pkt_flag_len = status;
  617. }
  618. }
  619. return (ret);
  620. }
  621. return (0);
  622. }
  623. /*
  624. * This function initializes the emac hardware. It does NOT initialize
  625. * EMAC modules power or pin multiplexors, that is done by board_init()
  626. * much earlier in bootup process. Returns 1 on success, 0 otherwise.
  627. */
  628. static int davinci_emac_probe(struct udevice *dev)
  629. {
  630. u_int32_t phy_id;
  631. u_int16_t tmp;
  632. int i;
  633. int ret;
  634. davinci_eth_mdio_enable();
  635. /* let the EMAC detect the PHYs */
  636. udelay(5000);
  637. for (i = 0; i < 256; i++) {
  638. if (readl(&adap_mdio->ALIVE))
  639. break;
  640. udelay(1000);
  641. }
  642. if (i >= 256) {
  643. printf("No ETH PHY detected!!!\n");
  644. return(0);
  645. }
  646. /* Find if PHY(s) is/are connected */
  647. ret = davinci_eth_phy_detect();
  648. if (!ret)
  649. return(0);
  650. else
  651. debug_emac(" %d ETH PHY detected\n", ret);
  652. /* Get PHY ID and initialize phy_ops for a detected PHY */
  653. for (i = 0; i < num_phy; i++) {
  654. if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
  655. &tmp)) {
  656. active_phy_addr[i] = 0xff;
  657. continue;
  658. }
  659. phy_id = (tmp << 16) & 0xffff0000;
  660. if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
  661. &tmp)) {
  662. active_phy_addr[i] = 0xff;
  663. continue;
  664. }
  665. phy_id |= tmp & 0x0000ffff;
  666. sprintf(phy[i].name, "GENERIC @ 0x%02x",
  667. active_phy_addr[i]);
  668. phy[i].init = gen_init_phy;
  669. phy[i].is_phy_connected = gen_is_phy_connected;
  670. phy[i].get_link_speed = gen_get_link_speed;
  671. phy[i].auto_negotiate = gen_auto_negotiate;
  672. debug("Ethernet PHY: %s\n", phy[i].name);
  673. int retval;
  674. struct mii_dev *mdiodev = mdio_alloc();
  675. if (!mdiodev)
  676. return -ENOMEM;
  677. strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
  678. mdiodev->read = davinci_mii_phy_read;
  679. mdiodev->write = davinci_mii_phy_write;
  680. retval = mdio_register(mdiodev);
  681. if (retval < 0)
  682. return retval;
  683. #ifdef DAVINCI_EMAC_GIG_ENABLE
  684. #define PHY_CONF_REG 22
  685. /* Enable PHY to clock out TX_CLK */
  686. davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
  687. tmp |= PHY_CONF_TXCLKEN;
  688. davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
  689. davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
  690. #endif
  691. }
  692. #if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
  693. defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
  694. !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
  695. for (i = 0; i < num_phy; i++) {
  696. if (phy[i].is_phy_connected(i))
  697. phy[i].auto_negotiate(i);
  698. }
  699. #endif
  700. return 0;
  701. }
  702. static const struct eth_ops davinci_emac_ops = {
  703. .start = davinci_emac_start,
  704. .send = davinci_emac_send,
  705. .recv = davinci_emac_recv,
  706. .stop = davinci_emac_stop,
  707. .write_hwaddr = davinci_emac_write_hwaddr,
  708. };
  709. static const struct udevice_id davinci_emac_ids[] = {
  710. { .compatible = "ti,davinci-dm6467-emac" },
  711. { .compatible = "ti,am3517-emac", },
  712. { .compatible = "ti,dm816-emac", },
  713. { }
  714. };
  715. U_BOOT_DRIVER(davinci_emac) = {
  716. .name = "davinci_emac",
  717. .id = UCLASS_ETH,
  718. .of_match = davinci_emac_ids,
  719. .probe = davinci_emac_probe,
  720. .ops = &davinci_emac_ops,
  721. .plat_auto = sizeof(struct eth_pdata),
  722. };