cpsw.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * CPSW Ethernet Switch Driver
  4. *
  5. * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <cpu_func.h>
  10. #include <log.h>
  11. #include <net.h>
  12. #include <miiphy.h>
  13. #include <malloc.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <cpsw.h>
  17. #include <dm/device_compat.h>
  18. #include <linux/bitops.h>
  19. #include <linux/compiler.h>
  20. #include <linux/errno.h>
  21. #include <asm/gpio.h>
  22. #include <asm/io.h>
  23. #include <phy.h>
  24. #include <asm/arch/cpu.h>
  25. #include <dm.h>
  26. #include "cpsw_mdio.h"
  27. #define BITMASK(bits) (BIT(bits) - 1)
  28. #define NUM_DESCS (PKTBUFSRX * 2)
  29. #define PKT_MIN 60
  30. #define PKT_MAX (1500 + 14 + 4 + 4)
  31. #define CLEAR_BIT 1
  32. #define GIGABITEN BIT(7)
  33. #define FULLDUPLEXEN BIT(0)
  34. #define MIIEN BIT(15)
  35. #define CTL_EXT_EN BIT(18)
  36. /* DMA Registers */
  37. #define CPDMA_TXCONTROL 0x004
  38. #define CPDMA_RXCONTROL 0x014
  39. #define CPDMA_SOFTRESET 0x01c
  40. #define CPDMA_RXFREE 0x0e0
  41. #define CPDMA_TXHDP_VER1 0x100
  42. #define CPDMA_TXHDP_VER2 0x200
  43. #define CPDMA_RXHDP_VER1 0x120
  44. #define CPDMA_RXHDP_VER2 0x220
  45. #define CPDMA_TXCP_VER1 0x140
  46. #define CPDMA_TXCP_VER2 0x240
  47. #define CPDMA_RXCP_VER1 0x160
  48. #define CPDMA_RXCP_VER2 0x260
  49. /* Descriptor mode bits */
  50. #define CPDMA_DESC_SOP BIT(31)
  51. #define CPDMA_DESC_EOP BIT(30)
  52. #define CPDMA_DESC_OWNER BIT(29)
  53. #define CPDMA_DESC_EOQ BIT(28)
  54. /*
  55. * This timeout definition is a worst-case ultra defensive measure against
  56. * unexpected controller lock ups. Ideally, we should never ever hit this
  57. * scenario in practice.
  58. */
  59. #define CPDMA_TIMEOUT 100 /* msecs */
  60. struct cpsw_regs {
  61. u32 id_ver;
  62. u32 control;
  63. u32 soft_reset;
  64. u32 stat_port_en;
  65. u32 ptype;
  66. };
  67. struct cpsw_slave_regs {
  68. u32 max_blks;
  69. u32 blk_cnt;
  70. u32 flow_thresh;
  71. u32 port_vlan;
  72. u32 tx_pri_map;
  73. #ifdef CONFIG_AM33XX
  74. u32 gap_thresh;
  75. #elif defined(CONFIG_TI814X)
  76. u32 ts_ctl;
  77. u32 ts_seq_ltype;
  78. u32 ts_vlan;
  79. #endif
  80. u32 sa_lo;
  81. u32 sa_hi;
  82. };
  83. struct cpsw_host_regs {
  84. u32 max_blks;
  85. u32 blk_cnt;
  86. u32 flow_thresh;
  87. u32 port_vlan;
  88. u32 tx_pri_map;
  89. u32 cpdma_tx_pri_map;
  90. u32 cpdma_rx_chan_map;
  91. };
  92. struct cpsw_sliver_regs {
  93. u32 id_ver;
  94. u32 mac_control;
  95. u32 mac_status;
  96. u32 soft_reset;
  97. u32 rx_maxlen;
  98. u32 __reserved_0;
  99. u32 rx_pause;
  100. u32 tx_pause;
  101. u32 __reserved_1;
  102. u32 rx_pri_map;
  103. };
  104. #define ALE_ENTRY_BITS 68
  105. #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
  106. /* ALE Registers */
  107. #define ALE_CONTROL 0x08
  108. #define ALE_UNKNOWNVLAN 0x18
  109. #define ALE_TABLE_CONTROL 0x20
  110. #define ALE_TABLE 0x34
  111. #define ALE_PORTCTL 0x40
  112. #define ALE_TABLE_WRITE BIT(31)
  113. #define ALE_TYPE_FREE 0
  114. #define ALE_TYPE_ADDR 1
  115. #define ALE_TYPE_VLAN 2
  116. #define ALE_TYPE_VLAN_ADDR 3
  117. #define ALE_UCAST_PERSISTANT 0
  118. #define ALE_UCAST_UNTOUCHED 1
  119. #define ALE_UCAST_OUI 2
  120. #define ALE_UCAST_TOUCHED 3
  121. #define ALE_MCAST_FWD 0
  122. #define ALE_MCAST_BLOCK_LEARN_FWD 1
  123. #define ALE_MCAST_FWD_LEARN 2
  124. #define ALE_MCAST_FWD_2 3
  125. enum cpsw_ale_port_state {
  126. ALE_PORT_STATE_DISABLE = 0x00,
  127. ALE_PORT_STATE_BLOCK = 0x01,
  128. ALE_PORT_STATE_LEARN = 0x02,
  129. ALE_PORT_STATE_FORWARD = 0x03,
  130. };
  131. /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
  132. #define ALE_SECURE 1
  133. #define ALE_BLOCKED 2
  134. struct cpsw_slave {
  135. struct cpsw_slave_regs *regs;
  136. struct cpsw_sliver_regs *sliver;
  137. int slave_num;
  138. u32 mac_control;
  139. struct cpsw_slave_data *data;
  140. };
  141. struct cpdma_desc {
  142. /* hardware fields */
  143. u32 hw_next;
  144. u32 hw_buffer;
  145. u32 hw_len;
  146. u32 hw_mode;
  147. /* software fields */
  148. u32 sw_buffer;
  149. u32 sw_len;
  150. };
  151. struct cpdma_chan {
  152. struct cpdma_desc *head, *tail;
  153. void *hdp, *cp, *rxfree;
  154. };
  155. /* AM33xx SoC specific definitions for the CONTROL port */
  156. #define AM33XX_GMII_SEL_MODE_MII 0
  157. #define AM33XX_GMII_SEL_MODE_RMII 1
  158. #define AM33XX_GMII_SEL_MODE_RGMII 2
  159. #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
  160. #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
  161. #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
  162. #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
  163. #define GMII_SEL_MODE_MASK 0x3
  164. #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
  165. #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
  166. #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
  167. #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
  168. #define chan_read(chan, fld) __raw_readl((chan)->fld)
  169. #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
  170. #define for_active_slave(slave, priv) \
  171. slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
  172. #define for_each_slave(slave, priv) \
  173. for (slave = (priv)->slaves; slave != (priv)->slaves + \
  174. ((priv)->data)->slaves; slave++)
  175. struct cpsw_priv {
  176. #ifdef CONFIG_DM_ETH
  177. struct udevice *dev;
  178. #else
  179. struct eth_device *dev;
  180. #endif
  181. struct cpsw_platform_data *data;
  182. int host_port;
  183. struct cpsw_regs *regs;
  184. void *dma_regs;
  185. struct cpsw_host_regs *host_port_regs;
  186. void *ale_regs;
  187. struct cpdma_desc *descs;
  188. struct cpdma_desc *desc_free;
  189. struct cpdma_chan rx_chan, tx_chan;
  190. struct cpsw_slave *slaves;
  191. struct phy_device *phydev;
  192. struct mii_dev *bus;
  193. u32 phy_mask;
  194. };
  195. static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
  196. {
  197. int idx;
  198. idx = start / 32;
  199. start -= idx * 32;
  200. idx = 2 - idx; /* flip */
  201. return (ale_entry[idx] >> start) & BITMASK(bits);
  202. }
  203. static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
  204. u32 value)
  205. {
  206. int idx;
  207. value &= BITMASK(bits);
  208. idx = start / 32;
  209. start -= idx * 32;
  210. idx = 2 - idx; /* flip */
  211. ale_entry[idx] &= ~(BITMASK(bits) << start);
  212. ale_entry[idx] |= (value << start);
  213. }
  214. #define DEFINE_ALE_FIELD(name, start, bits) \
  215. static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry) \
  216. { \
  217. return cpsw_ale_get_field(ale_entry, start, bits); \
  218. } \
  219. static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
  220. { \
  221. cpsw_ale_set_field(ale_entry, start, bits, value); \
  222. }
  223. DEFINE_ALE_FIELD(entry_type, 60, 2)
  224. DEFINE_ALE_FIELD(mcast_state, 62, 2)
  225. DEFINE_ALE_FIELD(port_mask, 66, 3)
  226. DEFINE_ALE_FIELD(ucast_type, 62, 2)
  227. DEFINE_ALE_FIELD(port_num, 66, 2)
  228. DEFINE_ALE_FIELD(blocked, 65, 1)
  229. DEFINE_ALE_FIELD(secure, 64, 1)
  230. DEFINE_ALE_FIELD(mcast, 40, 1)
  231. /* The MAC address field in the ALE entry cannot be macroized as above */
  232. static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
  233. {
  234. int i;
  235. for (i = 0; i < 6; i++)
  236. addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
  237. }
  238. static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
  239. {
  240. int i;
  241. for (i = 0; i < 6; i++)
  242. cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
  243. }
  244. static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
  245. {
  246. int i;
  247. __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
  248. for (i = 0; i < ALE_ENTRY_WORDS; i++)
  249. ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
  250. return idx;
  251. }
  252. static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
  253. {
  254. int i;
  255. for (i = 0; i < ALE_ENTRY_WORDS; i++)
  256. __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
  257. __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
  258. return idx;
  259. }
  260. static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
  261. {
  262. u32 ale_entry[ALE_ENTRY_WORDS];
  263. int type, idx;
  264. for (idx = 0; idx < priv->data->ale_entries; idx++) {
  265. u8 entry_addr[6];
  266. cpsw_ale_read(priv, idx, ale_entry);
  267. type = cpsw_ale_get_entry_type(ale_entry);
  268. if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
  269. continue;
  270. cpsw_ale_get_addr(ale_entry, entry_addr);
  271. if (memcmp(entry_addr, addr, 6) == 0)
  272. return idx;
  273. }
  274. return -ENOENT;
  275. }
  276. static int cpsw_ale_match_free(struct cpsw_priv *priv)
  277. {
  278. u32 ale_entry[ALE_ENTRY_WORDS];
  279. int type, idx;
  280. for (idx = 0; idx < priv->data->ale_entries; idx++) {
  281. cpsw_ale_read(priv, idx, ale_entry);
  282. type = cpsw_ale_get_entry_type(ale_entry);
  283. if (type == ALE_TYPE_FREE)
  284. return idx;
  285. }
  286. return -ENOENT;
  287. }
  288. static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
  289. {
  290. u32 ale_entry[ALE_ENTRY_WORDS];
  291. int type, idx;
  292. for (idx = 0; idx < priv->data->ale_entries; idx++) {
  293. cpsw_ale_read(priv, idx, ale_entry);
  294. type = cpsw_ale_get_entry_type(ale_entry);
  295. if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
  296. continue;
  297. if (cpsw_ale_get_mcast(ale_entry))
  298. continue;
  299. type = cpsw_ale_get_ucast_type(ale_entry);
  300. if (type != ALE_UCAST_PERSISTANT &&
  301. type != ALE_UCAST_OUI)
  302. return idx;
  303. }
  304. return -ENOENT;
  305. }
  306. static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
  307. int port, int flags)
  308. {
  309. u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
  310. int idx;
  311. cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
  312. cpsw_ale_set_addr(ale_entry, addr);
  313. cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
  314. cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
  315. cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
  316. cpsw_ale_set_port_num(ale_entry, port);
  317. idx = cpsw_ale_match_addr(priv, addr);
  318. if (idx < 0)
  319. idx = cpsw_ale_match_free(priv);
  320. if (idx < 0)
  321. idx = cpsw_ale_find_ageable(priv);
  322. if (idx < 0)
  323. return -ENOMEM;
  324. cpsw_ale_write(priv, idx, ale_entry);
  325. return 0;
  326. }
  327. static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
  328. int port_mask)
  329. {
  330. u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
  331. int idx, mask;
  332. idx = cpsw_ale_match_addr(priv, addr);
  333. if (idx >= 0)
  334. cpsw_ale_read(priv, idx, ale_entry);
  335. cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
  336. cpsw_ale_set_addr(ale_entry, addr);
  337. cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
  338. mask = cpsw_ale_get_port_mask(ale_entry);
  339. port_mask |= mask;
  340. cpsw_ale_set_port_mask(ale_entry, port_mask);
  341. if (idx < 0)
  342. idx = cpsw_ale_match_free(priv);
  343. if (idx < 0)
  344. idx = cpsw_ale_find_ageable(priv);
  345. if (idx < 0)
  346. return -ENOMEM;
  347. cpsw_ale_write(priv, idx, ale_entry);
  348. return 0;
  349. }
  350. static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
  351. {
  352. u32 tmp, mask = BIT(bit);
  353. tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
  354. tmp &= ~mask;
  355. tmp |= val ? mask : 0;
  356. __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
  357. }
  358. #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
  359. #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
  360. #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
  361. static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
  362. int val)
  363. {
  364. int offset = ALE_PORTCTL + 4 * port;
  365. u32 tmp, mask = 0x3;
  366. tmp = __raw_readl(priv->ale_regs + offset);
  367. tmp &= ~mask;
  368. tmp |= val & mask;
  369. __raw_writel(tmp, priv->ale_regs + offset);
  370. }
  371. /* Set a self-clearing bit in a register, and wait for it to clear */
  372. static inline void setbit_and_wait_for_clear32(void *addr)
  373. {
  374. __raw_writel(CLEAR_BIT, addr);
  375. while (__raw_readl(addr) & CLEAR_BIT)
  376. ;
  377. }
  378. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  379. ((mac)[2] << 16) | ((mac)[3] << 24))
  380. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  381. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  382. struct cpsw_priv *priv)
  383. {
  384. #ifdef CONFIG_DM_ETH
  385. struct eth_pdata *pdata = dev_get_plat(priv->dev);
  386. writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
  387. writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
  388. #else
  389. __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
  390. __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
  391. #endif
  392. }
  393. static int cpsw_slave_update_link(struct cpsw_slave *slave,
  394. struct cpsw_priv *priv, int *link)
  395. {
  396. struct phy_device *phy;
  397. u32 mac_control = 0;
  398. int ret = -ENODEV;
  399. phy = priv->phydev;
  400. if (!phy)
  401. goto out;
  402. ret = phy_startup(phy);
  403. if (ret)
  404. goto out;
  405. if (link)
  406. *link = phy->link;
  407. if (phy->link) { /* link up */
  408. mac_control = priv->data->mac_control;
  409. if (phy->speed == 1000)
  410. mac_control |= GIGABITEN;
  411. if (phy->duplex == DUPLEX_FULL)
  412. mac_control |= FULLDUPLEXEN;
  413. if (phy->speed == 100)
  414. mac_control |= MIIEN;
  415. if (phy->speed == 10 && phy_interface_is_rgmii(phy))
  416. mac_control |= CTL_EXT_EN;
  417. }
  418. if (mac_control == slave->mac_control)
  419. goto out;
  420. if (mac_control) {
  421. printf("link up on port %d, speed %d, %s duplex\n",
  422. slave->slave_num, phy->speed,
  423. (phy->duplex == DUPLEX_FULL) ? "full" : "half");
  424. } else {
  425. printf("link down on port %d\n", slave->slave_num);
  426. }
  427. __raw_writel(mac_control, &slave->sliver->mac_control);
  428. slave->mac_control = mac_control;
  429. out:
  430. return ret;
  431. }
  432. static int cpsw_update_link(struct cpsw_priv *priv)
  433. {
  434. int ret = -ENODEV;
  435. struct cpsw_slave *slave;
  436. for_active_slave(slave, priv)
  437. ret = cpsw_slave_update_link(slave, priv, NULL);
  438. return ret;
  439. }
  440. static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  441. {
  442. if (priv->host_port == 0)
  443. return slave_num + 1;
  444. else
  445. return slave_num;
  446. }
  447. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  448. {
  449. u32 slave_port;
  450. setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
  451. /* setup priority mapping */
  452. __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
  453. __raw_writel(0x33221100, &slave->regs->tx_pri_map);
  454. /* setup max packet size, and mac address */
  455. __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
  456. cpsw_set_slave_mac(slave, priv);
  457. slave->mac_control = 0; /* no link yet */
  458. /* enable forwarding */
  459. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  460. cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
  461. cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
  462. priv->phy_mask |= 1 << slave->data->phy_addr;
  463. }
  464. static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
  465. {
  466. struct cpdma_desc *desc = priv->desc_free;
  467. if (desc)
  468. priv->desc_free = desc_read_ptr(desc, hw_next);
  469. return desc;
  470. }
  471. static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
  472. {
  473. if (desc) {
  474. desc_write(desc, hw_next, priv->desc_free);
  475. priv->desc_free = desc;
  476. }
  477. }
  478. static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
  479. void *buffer, int len)
  480. {
  481. struct cpdma_desc *desc, *prev;
  482. u32 mode;
  483. desc = cpdma_desc_alloc(priv);
  484. if (!desc)
  485. return -ENOMEM;
  486. if (len < PKT_MIN)
  487. len = PKT_MIN;
  488. mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
  489. desc_write(desc, hw_next, 0);
  490. desc_write(desc, hw_buffer, buffer);
  491. desc_write(desc, hw_len, len);
  492. desc_write(desc, hw_mode, mode | len);
  493. desc_write(desc, sw_buffer, buffer);
  494. desc_write(desc, sw_len, len);
  495. if (!chan->head) {
  496. /* simple case - first packet enqueued */
  497. chan->head = desc;
  498. chan->tail = desc;
  499. chan_write(chan, hdp, desc);
  500. goto done;
  501. }
  502. /* not the first packet - enqueue at the tail */
  503. prev = chan->tail;
  504. desc_write(prev, hw_next, desc);
  505. chan->tail = desc;
  506. /* next check if EOQ has been triggered already */
  507. if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
  508. chan_write(chan, hdp, desc);
  509. done:
  510. if (chan->rxfree)
  511. chan_write(chan, rxfree, 1);
  512. return 0;
  513. }
  514. static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
  515. void **buffer, int *len)
  516. {
  517. struct cpdma_desc *desc = chan->head;
  518. u32 status;
  519. if (!desc)
  520. return -ENOENT;
  521. status = desc_read(desc, hw_mode);
  522. if (len)
  523. *len = status & 0x7ff;
  524. if (buffer)
  525. *buffer = desc_read_ptr(desc, sw_buffer);
  526. if (status & CPDMA_DESC_OWNER) {
  527. if (chan_read(chan, hdp) == 0) {
  528. if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
  529. chan_write(chan, hdp, desc);
  530. }
  531. return -EBUSY;
  532. }
  533. chan->head = desc_read_ptr(desc, hw_next);
  534. chan_write(chan, cp, desc);
  535. cpdma_desc_free(priv, desc);
  536. return 0;
  537. }
  538. static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
  539. {
  540. struct cpsw_slave *slave;
  541. int i, ret;
  542. /* soft reset the controller and initialize priv */
  543. setbit_and_wait_for_clear32(&priv->regs->soft_reset);
  544. /* initialize and reset the address lookup engine */
  545. cpsw_ale_enable(priv, 1);
  546. cpsw_ale_clear(priv, 1);
  547. cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
  548. /* setup host port priority mapping */
  549. __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
  550. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  551. /* disable priority elevation and enable statistics on all ports */
  552. __raw_writel(0, &priv->regs->ptype);
  553. /* enable statistics collection only on the host port */
  554. __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
  555. __raw_writel(0x7, &priv->regs->stat_port_en);
  556. cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
  557. cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
  558. cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
  559. for_active_slave(slave, priv)
  560. cpsw_slave_init(slave, priv);
  561. ret = cpsw_update_link(priv);
  562. if (ret)
  563. goto out;
  564. /* init descriptor pool */
  565. for (i = 0; i < NUM_DESCS; i++) {
  566. desc_write(&priv->descs[i], hw_next,
  567. (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
  568. }
  569. priv->desc_free = &priv->descs[0];
  570. /* initialize channels */
  571. if (priv->data->version == CPSW_CTRL_VERSION_2) {
  572. memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
  573. priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
  574. priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
  575. priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
  576. memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
  577. priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
  578. priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
  579. } else {
  580. memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
  581. priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
  582. priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
  583. priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
  584. memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
  585. priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
  586. priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
  587. }
  588. /* clear dma state */
  589. setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
  590. if (priv->data->version == CPSW_CTRL_VERSION_2) {
  591. for (i = 0; i < priv->data->channels; i++) {
  592. __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
  593. * i);
  594. __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
  595. * i);
  596. __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
  597. * i);
  598. __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
  599. * i);
  600. __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
  601. * i);
  602. }
  603. } else {
  604. for (i = 0; i < priv->data->channels; i++) {
  605. __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
  606. * i);
  607. __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
  608. * i);
  609. __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
  610. * i);
  611. __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
  612. * i);
  613. __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
  614. * i);
  615. }
  616. }
  617. __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
  618. __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
  619. /* submit rx descs */
  620. for (i = 0; i < PKTBUFSRX; i++) {
  621. ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
  622. PKTSIZE);
  623. if (ret < 0) {
  624. printf("error %d submitting rx desc\n", ret);
  625. break;
  626. }
  627. }
  628. out:
  629. return ret;
  630. }
  631. static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
  632. {
  633. int timeout = CPDMA_TIMEOUT;
  634. /* reap completed packets */
  635. while (timeout-- &&
  636. (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
  637. ;
  638. return timeout;
  639. }
  640. static void _cpsw_halt(struct cpsw_priv *priv)
  641. {
  642. cpsw_reap_completed_packets(priv);
  643. writel(0, priv->dma_regs + CPDMA_TXCONTROL);
  644. writel(0, priv->dma_regs + CPDMA_RXCONTROL);
  645. /* soft reset the controller and initialize priv */
  646. setbit_and_wait_for_clear32(&priv->regs->soft_reset);
  647. /* clear dma state */
  648. setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
  649. }
  650. static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
  651. {
  652. int timeout;
  653. flush_dcache_range((unsigned long)packet,
  654. (unsigned long)packet + ALIGN(length, PKTALIGN));
  655. timeout = cpsw_reap_completed_packets(priv);
  656. if (timeout == -1) {
  657. printf("cpdma_process timeout\n");
  658. return -ETIMEDOUT;
  659. }
  660. return cpdma_submit(priv, &priv->tx_chan, packet, length);
  661. }
  662. static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
  663. {
  664. void *buffer;
  665. int len;
  666. int ret;
  667. ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
  668. if (ret < 0)
  669. return ret;
  670. invalidate_dcache_range((unsigned long)buffer,
  671. (unsigned long)buffer + PKTSIZE_ALIGN);
  672. *pkt = buffer;
  673. return len;
  674. }
  675. static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
  676. struct cpsw_priv *priv)
  677. {
  678. void *regs = priv->regs;
  679. struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
  680. slave->slave_num = slave_num;
  681. slave->data = data;
  682. slave->regs = regs + data->slave_reg_ofs;
  683. slave->sliver = regs + data->sliver_reg_ofs;
  684. }
  685. static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
  686. {
  687. struct phy_device *phydev;
  688. u32 supported = PHY_GBIT_FEATURES;
  689. int ret;
  690. phydev = phy_connect(priv->bus,
  691. slave->data->phy_addr,
  692. priv->dev,
  693. slave->data->phy_if);
  694. if (!phydev)
  695. return -1;
  696. phydev->supported &= supported;
  697. if (slave->data->max_speed) {
  698. ret = phy_set_supported(phydev, slave->data->max_speed);
  699. if (ret)
  700. return ret;
  701. #if CONFIG_IS_ENABLED(DM_ETH)
  702. dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
  703. slave->slave_num + 1, slave->data->max_speed);
  704. #else
  705. log_debug("%s: Port %u speed forced to %uMbit\n",
  706. priv->dev->name, slave->slave_num + 1,
  707. slave->data->max_speed);
  708. #endif
  709. }
  710. phydev->advertising = phydev->supported;
  711. #ifdef CONFIG_DM_ETH
  712. if (ofnode_valid(slave->data->phy_of_handle))
  713. phydev->node = slave->data->phy_of_handle;
  714. #endif
  715. priv->phydev = phydev;
  716. phy_config(phydev);
  717. return 1;
  718. }
  719. static void cpsw_phy_addr_update(struct cpsw_priv *priv)
  720. {
  721. struct cpsw_platform_data *data = priv->data;
  722. u16 alive = cpsw_mdio_get_alive(priv->bus);
  723. int active = data->active_slave;
  724. int new_addr = ffs(alive) - 1;
  725. /*
  726. * If there is only one phy alive and its address does not match
  727. * that of active slave, then phy address can safely be updated.
  728. */
  729. if (hweight16(alive) == 1 &&
  730. data->slave_data[active].phy_addr != new_addr) {
  731. printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
  732. active, data->slave_data[active].phy_addr, new_addr);
  733. data->slave_data[active].phy_addr = new_addr;
  734. }
  735. }
  736. int _cpsw_register(struct cpsw_priv *priv)
  737. {
  738. struct cpsw_slave *slave;
  739. struct cpsw_platform_data *data = priv->data;
  740. void *regs = (void *)data->cpsw_base;
  741. priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
  742. if (!priv->slaves) {
  743. return -ENOMEM;
  744. }
  745. priv->host_port = data->host_port_num;
  746. priv->regs = regs;
  747. priv->host_port_regs = regs + data->host_port_reg_ofs;
  748. priv->dma_regs = regs + data->cpdma_reg_ofs;
  749. priv->ale_regs = regs + data->ale_reg_ofs;
  750. priv->descs = (void *)regs + data->bd_ram_ofs;
  751. int idx = 0;
  752. for_each_slave(slave, priv) {
  753. cpsw_slave_setup(slave, idx, priv);
  754. idx = idx + 1;
  755. }
  756. priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
  757. if (!priv->bus)
  758. return -EFAULT;
  759. cpsw_phy_addr_update(priv);
  760. for_active_slave(slave, priv)
  761. cpsw_phy_init(priv, slave);
  762. return 0;
  763. }
  764. #ifndef CONFIG_DM_ETH
  765. static int cpsw_init(struct eth_device *dev, struct bd_info *bis)
  766. {
  767. struct cpsw_priv *priv = dev->priv;
  768. return _cpsw_init(priv, dev->enetaddr);
  769. }
  770. static void cpsw_halt(struct eth_device *dev)
  771. {
  772. struct cpsw_priv *priv = dev->priv;
  773. return _cpsw_halt(priv);
  774. }
  775. static int cpsw_send(struct eth_device *dev, void *packet, int length)
  776. {
  777. struct cpsw_priv *priv = dev->priv;
  778. return _cpsw_send(priv, packet, length);
  779. }
  780. static int cpsw_recv(struct eth_device *dev)
  781. {
  782. struct cpsw_priv *priv = dev->priv;
  783. uchar *pkt = NULL;
  784. int len;
  785. len = _cpsw_recv(priv, &pkt);
  786. if (len > 0) {
  787. net_process_received_packet(pkt, len);
  788. cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
  789. }
  790. return len;
  791. }
  792. int cpsw_register(struct cpsw_platform_data *data)
  793. {
  794. struct cpsw_priv *priv;
  795. struct eth_device *dev;
  796. int ret;
  797. dev = calloc(sizeof(*dev), 1);
  798. if (!dev)
  799. return -ENOMEM;
  800. priv = calloc(sizeof(*priv), 1);
  801. if (!priv) {
  802. free(dev);
  803. return -ENOMEM;
  804. }
  805. priv->dev = dev;
  806. priv->data = data;
  807. strcpy(dev->name, "cpsw");
  808. dev->iobase = 0;
  809. dev->init = cpsw_init;
  810. dev->halt = cpsw_halt;
  811. dev->send = cpsw_send;
  812. dev->recv = cpsw_recv;
  813. dev->priv = priv;
  814. eth_register(dev);
  815. ret = _cpsw_register(priv);
  816. if (ret < 0) {
  817. eth_unregister(dev);
  818. free(dev);
  819. free(priv);
  820. return ret;
  821. }
  822. return 1;
  823. }
  824. #else
  825. static int cpsw_eth_start(struct udevice *dev)
  826. {
  827. struct eth_pdata *pdata = dev_get_plat(dev);
  828. struct cpsw_priv *priv = dev_get_priv(dev);
  829. return _cpsw_init(priv, pdata->enetaddr);
  830. }
  831. static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
  832. {
  833. struct cpsw_priv *priv = dev_get_priv(dev);
  834. return _cpsw_send(priv, packet, length);
  835. }
  836. static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  837. {
  838. struct cpsw_priv *priv = dev_get_priv(dev);
  839. return _cpsw_recv(priv, packetp);
  840. }
  841. static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
  842. int length)
  843. {
  844. struct cpsw_priv *priv = dev_get_priv(dev);
  845. return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
  846. }
  847. static void cpsw_eth_stop(struct udevice *dev)
  848. {
  849. struct cpsw_priv *priv = dev_get_priv(dev);
  850. return _cpsw_halt(priv);
  851. }
  852. static const struct eth_ops cpsw_eth_ops = {
  853. .start = cpsw_eth_start,
  854. .send = cpsw_eth_send,
  855. .recv = cpsw_eth_recv,
  856. .free_pkt = cpsw_eth_free_pkt,
  857. .stop = cpsw_eth_stop,
  858. };
  859. static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
  860. phy_interface_t phy_mode)
  861. {
  862. u32 reg;
  863. u32 mask;
  864. u32 mode = 0;
  865. bool rgmii_id = false;
  866. int slave = priv->data->active_slave;
  867. reg = readl(priv->data->gmii_sel);
  868. switch (phy_mode) {
  869. case PHY_INTERFACE_MODE_RMII:
  870. mode = AM33XX_GMII_SEL_MODE_RMII;
  871. break;
  872. case PHY_INTERFACE_MODE_RGMII:
  873. case PHY_INTERFACE_MODE_RGMII_RXID:
  874. mode = AM33XX_GMII_SEL_MODE_RGMII;
  875. break;
  876. case PHY_INTERFACE_MODE_RGMII_ID:
  877. case PHY_INTERFACE_MODE_RGMII_TXID:
  878. mode = AM33XX_GMII_SEL_MODE_RGMII;
  879. rgmii_id = true;
  880. break;
  881. case PHY_INTERFACE_MODE_MII:
  882. default:
  883. mode = AM33XX_GMII_SEL_MODE_MII;
  884. break;
  885. };
  886. mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
  887. mode <<= slave * 2;
  888. if (priv->data->rmii_clock_external) {
  889. if (slave == 0)
  890. mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
  891. else
  892. mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
  893. }
  894. if (rgmii_id) {
  895. if (slave == 0)
  896. mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
  897. else
  898. mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
  899. }
  900. reg &= ~mask;
  901. reg |= mode;
  902. writel(reg, priv->data->gmii_sel);
  903. }
  904. static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
  905. phy_interface_t phy_mode)
  906. {
  907. u32 reg;
  908. u32 mask;
  909. u32 mode = 0;
  910. int slave = priv->data->active_slave;
  911. reg = readl(priv->data->gmii_sel);
  912. switch (phy_mode) {
  913. case PHY_INTERFACE_MODE_RMII:
  914. mode = AM33XX_GMII_SEL_MODE_RMII;
  915. break;
  916. case PHY_INTERFACE_MODE_RGMII:
  917. case PHY_INTERFACE_MODE_RGMII_ID:
  918. case PHY_INTERFACE_MODE_RGMII_RXID:
  919. case PHY_INTERFACE_MODE_RGMII_TXID:
  920. mode = AM33XX_GMII_SEL_MODE_RGMII;
  921. break;
  922. case PHY_INTERFACE_MODE_MII:
  923. default:
  924. mode = AM33XX_GMII_SEL_MODE_MII;
  925. break;
  926. };
  927. switch (slave) {
  928. case 0:
  929. mask = GMII_SEL_MODE_MASK;
  930. break;
  931. case 1:
  932. mask = GMII_SEL_MODE_MASK << 4;
  933. mode <<= 4;
  934. break;
  935. default:
  936. dev_err(priv->dev, "invalid slave number...\n");
  937. return;
  938. }
  939. if (priv->data->rmii_clock_external)
  940. dev_err(priv->dev, "RMII External clock is not supported\n");
  941. reg &= ~mask;
  942. reg |= mode;
  943. writel(reg, priv->data->gmii_sel);
  944. }
  945. static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
  946. phy_interface_t phy_mode)
  947. {
  948. if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
  949. cpsw_gmii_sel_am3352(priv, phy_mode);
  950. if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
  951. cpsw_gmii_sel_am3352(priv, phy_mode);
  952. else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
  953. cpsw_gmii_sel_dra7xx(priv, phy_mode);
  954. }
  955. static int cpsw_eth_probe(struct udevice *dev)
  956. {
  957. struct cpsw_priv *priv = dev_get_priv(dev);
  958. struct eth_pdata *pdata = dev_get_plat(dev);
  959. priv->dev = dev;
  960. priv->data = pdata->priv_pdata;
  961. ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
  962. /* Select phy interface in control module */
  963. cpsw_phy_sel(priv, priv->data->phy_sel_compat,
  964. pdata->phy_interface);
  965. return _cpsw_register(priv);
  966. }
  967. #if CONFIG_IS_ENABLED(OF_CONTROL)
  968. static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
  969. int slave_index, ofnode subnode)
  970. {
  971. struct ofnode_phandle_args out_args;
  972. struct cpsw_slave_data *slave_data;
  973. const char *phy_mode;
  974. u32 phy_id[2];
  975. int ret;
  976. slave_data = &data->slave_data[slave_index];
  977. phy_mode = ofnode_read_string(subnode, "phy-mode");
  978. if (phy_mode)
  979. slave_data->phy_if = phy_get_interface_by_name(phy_mode);
  980. ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
  981. NULL, 0, 0, &out_args);
  982. if (!ret) {
  983. slave_data->phy_of_handle = out_args.node;
  984. ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
  985. &slave_data->phy_addr);
  986. if (ret)
  987. printf("error: phy addr not found in dt\n");
  988. } else {
  989. ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
  990. if (ret)
  991. printf("error: phy_id read failed\n");
  992. }
  993. slave_data->max_speed = ofnode_read_s32_default(subnode,
  994. "max-speed", 0);
  995. }
  996. static int cpsw_eth_of_to_plat(struct udevice *dev)
  997. {
  998. struct eth_pdata *pdata = dev_get_plat(dev);
  999. struct cpsw_platform_data *data;
  1000. struct gpio_desc *mode_gpios;
  1001. int slave_index = 0;
  1002. int num_mode_gpios;
  1003. ofnode subnode;
  1004. int ret;
  1005. data = calloc(1, sizeof(struct cpsw_platform_data));
  1006. if (!data)
  1007. return -ENOMEM;
  1008. pdata->priv_pdata = data;
  1009. pdata->iobase = dev_read_addr(dev);
  1010. data->version = CPSW_CTRL_VERSION_2;
  1011. data->bd_ram_ofs = CPSW_BD_OFFSET;
  1012. data->ale_reg_ofs = CPSW_ALE_OFFSET;
  1013. data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
  1014. data->mdio_div = CPSW_MDIO_DIV;
  1015. data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
  1016. pdata->phy_interface = -1;
  1017. data->cpsw_base = pdata->iobase;
  1018. ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
  1019. if (ret) {
  1020. printf("error: cpdma_channels not found in dt\n");
  1021. return ret;
  1022. }
  1023. ret = dev_read_s32(dev, "slaves", &data->slaves);
  1024. if (ret) {
  1025. printf("error: slaves not found in dt\n");
  1026. return ret;
  1027. }
  1028. data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
  1029. data->slaves);
  1030. ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
  1031. if (ret) {
  1032. printf("error: ale_entries not found in dt\n");
  1033. return ret;
  1034. }
  1035. ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
  1036. if (ret) {
  1037. printf("error: bd_ram_size not found in dt\n");
  1038. return ret;
  1039. }
  1040. ret = dev_read_u32(dev, "mac_control", &data->mac_control);
  1041. if (ret) {
  1042. printf("error: ale_entries not found in dt\n");
  1043. return ret;
  1044. }
  1045. num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
  1046. if (num_mode_gpios > 0) {
  1047. mode_gpios = malloc(sizeof(struct gpio_desc) *
  1048. num_mode_gpios);
  1049. gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
  1050. num_mode_gpios, GPIOD_IS_OUT);
  1051. free(mode_gpios);
  1052. }
  1053. data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
  1054. ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
  1055. const char *name;
  1056. name = ofnode_get_name(subnode);
  1057. if (!strncmp(name, "mdio", 4)) {
  1058. data->mdio_base = ofnode_get_addr(subnode);
  1059. if (data->mdio_base == FDT_ADDR_T_NONE) {
  1060. pr_err("Not able to get MDIO address space\n");
  1061. return -ENOENT;
  1062. }
  1063. }
  1064. if (!strncmp(name, "slave", 5)) {
  1065. if (slave_index >= data->slaves)
  1066. continue;
  1067. cpsw_eth_of_parse_slave(data, slave_index, subnode);
  1068. slave_index++;
  1069. }
  1070. if (!strncmp(name, "cpsw-phy-sel", 12)) {
  1071. data->gmii_sel = ofnode_get_addr(subnode);
  1072. if (data->gmii_sel == FDT_ADDR_T_NONE) {
  1073. pr_err("Not able to get gmii_sel reg address\n");
  1074. return -ENOENT;
  1075. }
  1076. if (ofnode_read_bool(subnode, "rmii-clock-ext"))
  1077. data->rmii_clock_external = true;
  1078. data->phy_sel_compat = ofnode_read_string(subnode,
  1079. "compatible");
  1080. if (!data->phy_sel_compat) {
  1081. pr_err("Not able to get gmii_sel compatible\n");
  1082. return -ENOENT;
  1083. }
  1084. }
  1085. }
  1086. data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
  1087. data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
  1088. if (data->slaves == 2) {
  1089. data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
  1090. data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
  1091. }
  1092. ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
  1093. if (ret < 0) {
  1094. pr_err("cpsw read efuse mac failed\n");
  1095. return ret;
  1096. }
  1097. pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
  1098. if (pdata->phy_interface == -1) {
  1099. debug("%s: Invalid PHY interface '%s'\n", __func__,
  1100. phy_string_for_interface(pdata->phy_interface));
  1101. return -EINVAL;
  1102. }
  1103. return 0;
  1104. }
  1105. static const struct udevice_id cpsw_eth_ids[] = {
  1106. { .compatible = "ti,cpsw" },
  1107. { .compatible = "ti,am335x-cpsw" },
  1108. { }
  1109. };
  1110. #endif
  1111. int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
  1112. {
  1113. struct cpsw_priv *priv = dev_get_priv(dev);
  1114. struct cpsw_platform_data *data = priv->data;
  1115. return data->slave_data[slave].phy_addr;
  1116. }
  1117. U_BOOT_DRIVER(eth_cpsw) = {
  1118. .name = "eth_cpsw",
  1119. .id = UCLASS_ETH,
  1120. #if CONFIG_IS_ENABLED(OF_CONTROL)
  1121. .of_match = cpsw_eth_ids,
  1122. .of_to_plat = cpsw_eth_of_to_plat,
  1123. .plat_auto = sizeof(struct eth_pdata),
  1124. #endif
  1125. .probe = cpsw_eth_probe,
  1126. .ops = &cpsw_eth_ops,
  1127. .priv_auto = sizeof(struct cpsw_priv),
  1128. .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
  1129. };
  1130. #endif /* CONFIG_DM_ETH */