sun8i_emac.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Author: Amit Singh Tomar, amittomer25@gmail.com
  5. *
  6. * Ethernet driver for H3/A64/A83T based SoC's
  7. *
  8. * It is derived from the work done by
  9. * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  10. *
  11. */
  12. #include <cpu_func.h>
  13. #include <log.h>
  14. #include <asm/cache.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/gpio.h>
  19. #include <common.h>
  20. #include <clk.h>
  21. #include <dm.h>
  22. #include <fdt_support.h>
  23. #include <dm/device_compat.h>
  24. #include <linux/bitops.h>
  25. #include <linux/delay.h>
  26. #include <linux/err.h>
  27. #include <malloc.h>
  28. #include <miiphy.h>
  29. #include <net.h>
  30. #include <reset.h>
  31. #include <dt-bindings/pinctrl/sun4i-a10.h>
  32. #include <wait_bit.h>
  33. #if CONFIG_IS_ENABLED(DM_GPIO)
  34. #include <asm-generic/gpio.h>
  35. #endif
  36. #define MDIO_CMD_MII_BUSY BIT(0)
  37. #define MDIO_CMD_MII_WRITE BIT(1)
  38. #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
  39. #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
  40. #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
  41. #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
  42. #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
  43. #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
  44. #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
  45. #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
  46. #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
  47. #define CONFIG_TX_DESCR_NUM 32
  48. #define CONFIG_RX_DESCR_NUM 32
  49. #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
  50. /*
  51. * The datasheet says that each descriptor can transfers up to 4096 bytes
  52. * But later, the register documentation reduces that value to 2048,
  53. * using 2048 cause strange behaviours and even BSP driver use 2047
  54. */
  55. #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
  56. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  57. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  58. #define H3_EPHY_DEFAULT_VALUE 0x58000
  59. #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
  60. #define H3_EPHY_ADDR_SHIFT 20
  61. #define REG_PHY_ADDR_MASK GENMASK(4, 0)
  62. #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
  63. #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
  64. #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
  65. #define SC_RMII_EN BIT(13)
  66. #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
  67. #define SC_ETCS_MASK GENMASK(1, 0)
  68. #define SC_ETCS_EXT_GMII 0x1
  69. #define SC_ETCS_INT_GMII 0x2
  70. #define SC_ETXDC_MASK GENMASK(12, 10)
  71. #define SC_ETXDC_OFFSET 10
  72. #define SC_ERXDC_MASK GENMASK(9, 5)
  73. #define SC_ERXDC_OFFSET 5
  74. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  75. #define AHB_GATE_OFFSET_EPHY 0
  76. /* IO mux settings */
  77. #define SUN8I_IOMUX_H3 2
  78. #define SUN8I_IOMUX_R40 5
  79. #define SUN8I_IOMUX_H6 5
  80. #define SUN8I_IOMUX_H616 2
  81. #define SUN8I_IOMUX 4
  82. /* H3/A64 EMAC Register's offset */
  83. #define EMAC_CTL0 0x00
  84. #define EMAC_CTL0_FULL_DUPLEX BIT(0)
  85. #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
  86. #define EMAC_CTL0_SPEED_10 (0x2 << 2)
  87. #define EMAC_CTL0_SPEED_100 (0x3 << 2)
  88. #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
  89. #define EMAC_CTL1 0x04
  90. #define EMAC_CTL1_SOFT_RST BIT(0)
  91. #define EMAC_CTL1_BURST_LEN_SHIFT 24
  92. #define EMAC_INT_STA 0x08
  93. #define EMAC_INT_EN 0x0c
  94. #define EMAC_TX_CTL0 0x10
  95. #define EMAC_TX_CTL0_TX_EN BIT(31)
  96. #define EMAC_TX_CTL1 0x14
  97. #define EMAC_TX_CTL1_TX_MD BIT(1)
  98. #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
  99. #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
  100. #define EMAC_TX_FLOW_CTL 0x1c
  101. #define EMAC_TX_DMA_DESC 0x20
  102. #define EMAC_RX_CTL0 0x24
  103. #define EMAC_RX_CTL0_RX_EN BIT(31)
  104. #define EMAC_RX_CTL1 0x28
  105. #define EMAC_RX_CTL1_RX_MD BIT(1)
  106. #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
  107. #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
  108. #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
  109. #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
  110. #define EMAC_RX_DMA_DESC 0x34
  111. #define EMAC_MII_CMD 0x48
  112. #define EMAC_MII_DATA 0x4c
  113. #define EMAC_ADDR0_HIGH 0x50
  114. #define EMAC_ADDR0_LOW 0x54
  115. #define EMAC_TX_DMA_STA 0xb0
  116. #define EMAC_TX_CUR_DESC 0xb4
  117. #define EMAC_TX_CUR_BUF 0xb8
  118. #define EMAC_RX_DMA_STA 0xc0
  119. #define EMAC_RX_CUR_DESC 0xc4
  120. #define EMAC_DESC_OWN_DMA BIT(31)
  121. #define EMAC_DESC_LAST_DESC BIT(30)
  122. #define EMAC_DESC_FIRST_DESC BIT(29)
  123. #define EMAC_DESC_CHAIN_SECOND BIT(24)
  124. #define EMAC_DESC_RX_ERROR_MASK 0x400068db
  125. DECLARE_GLOBAL_DATA_PTR;
  126. enum emac_variant {
  127. A83T_EMAC = 1,
  128. H3_EMAC,
  129. A64_EMAC,
  130. R40_GMAC,
  131. H6_EMAC,
  132. };
  133. struct emac_dma_desc {
  134. u32 status;
  135. u32 ctl_size;
  136. u32 buf_addr;
  137. u32 next;
  138. } __aligned(ARCH_DMA_MINALIGN);
  139. struct emac_eth_dev {
  140. struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
  141. struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
  142. char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  143. char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  144. u32 interface;
  145. u32 phyaddr;
  146. u32 link;
  147. u32 speed;
  148. u32 duplex;
  149. u32 phy_configured;
  150. u32 tx_currdescnum;
  151. u32 rx_currdescnum;
  152. u32 addr;
  153. u32 tx_slot;
  154. bool use_internal_phy;
  155. enum emac_variant variant;
  156. void *mac_reg;
  157. phys_addr_t sysctl_reg;
  158. struct phy_device *phydev;
  159. struct mii_dev *bus;
  160. struct clk tx_clk;
  161. struct clk ephy_clk;
  162. struct reset_ctl tx_rst;
  163. struct reset_ctl ephy_rst;
  164. #if CONFIG_IS_ENABLED(DM_GPIO)
  165. struct gpio_desc reset_gpio;
  166. #endif
  167. };
  168. struct sun8i_eth_pdata {
  169. struct eth_pdata eth_pdata;
  170. u32 reset_delays[3];
  171. int tx_delay_ps;
  172. int rx_delay_ps;
  173. };
  174. static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  175. {
  176. struct udevice *dev = bus->priv;
  177. struct emac_eth_dev *priv = dev_get_priv(dev);
  178. u32 mii_cmd;
  179. int ret;
  180. mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  181. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  182. mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  183. MDIO_CMD_MII_PHY_ADDR_MASK;
  184. /*
  185. * The EMAC clock is either 200 or 300 MHz, so we need a divider
  186. * of 128 to get the MDIO frequency below the required 2.5 MHz.
  187. */
  188. if (!priv->use_internal_phy)
  189. mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
  190. MDIO_CMD_MII_CLK_CSR_SHIFT;
  191. mii_cmd |= MDIO_CMD_MII_BUSY;
  192. writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
  193. ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
  194. MDIO_CMD_MII_BUSY, false,
  195. CONFIG_MDIO_TIMEOUT, true);
  196. if (ret < 0)
  197. return ret;
  198. return readl(priv->mac_reg + EMAC_MII_DATA);
  199. }
  200. static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  201. u16 val)
  202. {
  203. struct udevice *dev = bus->priv;
  204. struct emac_eth_dev *priv = dev_get_priv(dev);
  205. u32 mii_cmd;
  206. mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  207. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  208. mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  209. MDIO_CMD_MII_PHY_ADDR_MASK;
  210. /*
  211. * The EMAC clock is either 200 or 300 MHz, so we need a divider
  212. * of 128 to get the MDIO frequency below the required 2.5 MHz.
  213. */
  214. if (!priv->use_internal_phy)
  215. mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
  216. MDIO_CMD_MII_CLK_CSR_SHIFT;
  217. mii_cmd |= MDIO_CMD_MII_WRITE;
  218. mii_cmd |= MDIO_CMD_MII_BUSY;
  219. writel(val, priv->mac_reg + EMAC_MII_DATA);
  220. writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
  221. return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
  222. MDIO_CMD_MII_BUSY, false,
  223. CONFIG_MDIO_TIMEOUT, true);
  224. }
  225. static int sun8i_eth_write_hwaddr(struct udevice *dev)
  226. {
  227. struct emac_eth_dev *priv = dev_get_priv(dev);
  228. struct eth_pdata *pdata = dev_get_plat(dev);
  229. uchar *mac_id = pdata->enetaddr;
  230. u32 macid_lo, macid_hi;
  231. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  232. (mac_id[3] << 24);
  233. macid_hi = mac_id[4] + (mac_id[5] << 8);
  234. writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
  235. writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
  236. return 0;
  237. }
  238. static void sun8i_adjust_link(struct emac_eth_dev *priv,
  239. struct phy_device *phydev)
  240. {
  241. u32 v;
  242. v = readl(priv->mac_reg + EMAC_CTL0);
  243. if (phydev->duplex)
  244. v |= EMAC_CTL0_FULL_DUPLEX;
  245. else
  246. v &= ~EMAC_CTL0_FULL_DUPLEX;
  247. v &= ~EMAC_CTL0_SPEED_MASK;
  248. switch (phydev->speed) {
  249. case 1000:
  250. v |= EMAC_CTL0_SPEED_1000;
  251. break;
  252. case 100:
  253. v |= EMAC_CTL0_SPEED_100;
  254. break;
  255. case 10:
  256. v |= EMAC_CTL0_SPEED_10;
  257. break;
  258. }
  259. writel(v, priv->mac_reg + EMAC_CTL0);
  260. }
  261. static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
  262. {
  263. if (priv->use_internal_phy) {
  264. /* H3 based SoC's that has an Internal 100MBit PHY
  265. * needs to be configured and powered up before use
  266. */
  267. reg &= ~H3_EPHY_DEFAULT_MASK;
  268. reg |= H3_EPHY_DEFAULT_VALUE;
  269. reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
  270. reg &= ~H3_EPHY_SHUTDOWN;
  271. return reg | H3_EPHY_SELECT;
  272. }
  273. /* This is to select External Gigabit PHY on those boards with
  274. * an internal PHY. Does not hurt on other SoCs. Linux does
  275. * it as well.
  276. */
  277. return reg & ~H3_EPHY_SELECT;
  278. }
  279. static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
  280. struct emac_eth_dev *priv)
  281. {
  282. u32 reg;
  283. if (priv->variant == R40_GMAC) {
  284. /* Select RGMII for R40 */
  285. reg = readl(priv->sysctl_reg + 0x164);
  286. reg |= SC_ETCS_INT_GMII |
  287. SC_EPIT |
  288. (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
  289. writel(reg, priv->sysctl_reg + 0x164);
  290. return 0;
  291. }
  292. reg = readl(priv->sysctl_reg + 0x30);
  293. reg = sun8i_emac_set_syscon_ephy(priv, reg);
  294. reg &= ~(SC_ETCS_MASK | SC_EPIT);
  295. if (priv->variant == H3_EMAC ||
  296. priv->variant == A64_EMAC ||
  297. priv->variant == H6_EMAC)
  298. reg &= ~SC_RMII_EN;
  299. switch (priv->interface) {
  300. case PHY_INTERFACE_MODE_MII:
  301. /* default */
  302. break;
  303. case PHY_INTERFACE_MODE_RGMII:
  304. case PHY_INTERFACE_MODE_RGMII_ID:
  305. case PHY_INTERFACE_MODE_RGMII_RXID:
  306. case PHY_INTERFACE_MODE_RGMII_TXID:
  307. reg |= SC_EPIT | SC_ETCS_INT_GMII;
  308. break;
  309. case PHY_INTERFACE_MODE_RMII:
  310. if (priv->variant == H3_EMAC ||
  311. priv->variant == A64_EMAC ||
  312. priv->variant == H6_EMAC) {
  313. reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
  314. break;
  315. }
  316. /* RMII not supported on A83T */
  317. default:
  318. debug("%s: Invalid PHY interface\n", __func__);
  319. return -EINVAL;
  320. }
  321. if (pdata->tx_delay_ps)
  322. reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
  323. & SC_ETXDC_MASK;
  324. if (pdata->rx_delay_ps)
  325. reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
  326. & SC_ERXDC_MASK;
  327. writel(reg, priv->sysctl_reg + 0x30);
  328. return 0;
  329. }
  330. static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
  331. {
  332. struct phy_device *phydev;
  333. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  334. if (!phydev)
  335. return -ENODEV;
  336. phy_connect_dev(phydev, dev);
  337. priv->phydev = phydev;
  338. phy_config(priv->phydev);
  339. return 0;
  340. }
  341. #define cache_clean_descriptor(desc) \
  342. flush_dcache_range((uintptr_t)(desc), \
  343. (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
  344. #define cache_inv_descriptor(desc) \
  345. invalidate_dcache_range((uintptr_t)(desc), \
  346. (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
  347. static void rx_descs_init(struct emac_eth_dev *priv)
  348. {
  349. struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
  350. char *rxbuffs = &priv->rxbuffer[0];
  351. struct emac_dma_desc *desc_p;
  352. int i;
  353. /*
  354. * Make sure we don't have dirty cache lines around, which could
  355. * be cleaned to DRAM *after* the MAC has already written data to it.
  356. */
  357. invalidate_dcache_range((uintptr_t)desc_table_p,
  358. (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
  359. invalidate_dcache_range((uintptr_t)rxbuffs,
  360. (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
  361. for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
  362. desc_p = &desc_table_p[i];
  363. desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
  364. desc_p->next = (uintptr_t)&desc_table_p[i + 1];
  365. desc_p->ctl_size = CONFIG_ETH_RXSIZE;
  366. desc_p->status = EMAC_DESC_OWN_DMA;
  367. }
  368. /* Correcting the last pointer of the chain */
  369. desc_p->next = (uintptr_t)&desc_table_p[0];
  370. flush_dcache_range((uintptr_t)priv->rx_chain,
  371. (uintptr_t)priv->rx_chain +
  372. sizeof(priv->rx_chain));
  373. writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
  374. priv->rx_currdescnum = 0;
  375. }
  376. static void tx_descs_init(struct emac_eth_dev *priv)
  377. {
  378. struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
  379. char *txbuffs = &priv->txbuffer[0];
  380. struct emac_dma_desc *desc_p;
  381. int i;
  382. for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
  383. desc_p = &desc_table_p[i];
  384. desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
  385. desc_p->next = (uintptr_t)&desc_table_p[i + 1];
  386. desc_p->ctl_size = 0;
  387. desc_p->status = 0;
  388. }
  389. /* Correcting the last pointer of the chain */
  390. desc_p->next = (uintptr_t)&desc_table_p[0];
  391. /* Flush the first TX buffer descriptor we will tell the MAC about. */
  392. cache_clean_descriptor(desc_table_p);
  393. writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
  394. priv->tx_currdescnum = 0;
  395. }
  396. static int sun8i_emac_eth_start(struct udevice *dev)
  397. {
  398. struct emac_eth_dev *priv = dev_get_priv(dev);
  399. int ret;
  400. /* Soft reset MAC */
  401. writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
  402. ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
  403. EMAC_CTL1_SOFT_RST, false, 10, true);
  404. if (ret) {
  405. printf("%s: Timeout\n", __func__);
  406. return ret;
  407. }
  408. /* Rewrite mac address after reset */
  409. sun8i_eth_write_hwaddr(dev);
  410. /* transmission starts after the full frame arrived in TX DMA FIFO */
  411. setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
  412. /*
  413. * RX DMA reads data from RX DMA FIFO to host memory after a
  414. * complete frame has been written to RX DMA FIFO
  415. */
  416. setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
  417. /* DMA burst length */
  418. writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
  419. /* Initialize rx/tx descriptors */
  420. rx_descs_init(priv);
  421. tx_descs_init(priv);
  422. /* PHY Start Up */
  423. ret = phy_startup(priv->phydev);
  424. if (ret)
  425. return ret;
  426. sun8i_adjust_link(priv, priv->phydev);
  427. /* Start RX/TX DMA */
  428. setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
  429. EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
  430. setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
  431. /* Enable RX/TX */
  432. setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
  433. setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
  434. return 0;
  435. }
  436. static int parse_phy_pins(struct udevice *dev)
  437. {
  438. int offset;
  439. const char *pin_name;
  440. int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
  441. u32 iomux;
  442. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  443. "pinctrl-0");
  444. if (offset < 0) {
  445. printf("WARNING: emac: cannot find pinctrl-0 node\n");
  446. return offset;
  447. }
  448. drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
  449. "drive-strength", ~0);
  450. if (drive != ~0) {
  451. if (drive <= 10)
  452. drive = SUN4I_PINCTRL_10_MA;
  453. else if (drive <= 20)
  454. drive = SUN4I_PINCTRL_20_MA;
  455. else if (drive <= 30)
  456. drive = SUN4I_PINCTRL_30_MA;
  457. else
  458. drive = SUN4I_PINCTRL_40_MA;
  459. }
  460. if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
  461. pull = SUN4I_PINCTRL_PULL_UP;
  462. else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
  463. pull = SUN4I_PINCTRL_PULL_DOWN;
  464. /*
  465. * The GPIO pinmux value is an integration choice, so depends on the
  466. * SoC, not the EMAC variant.
  467. */
  468. if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
  469. iomux = SUN8I_IOMUX_H3;
  470. else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
  471. iomux = SUN8I_IOMUX_R40;
  472. else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  473. iomux = SUN8I_IOMUX_H6;
  474. else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
  475. iomux = SUN8I_IOMUX_H616;
  476. else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
  477. iomux = SUN8I_IOMUX;
  478. else if (IS_ENABLED(CONFIG_MACH_SUN50I))
  479. iomux = SUN8I_IOMUX;
  480. else
  481. BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
  482. for (i = 0; ; i++) {
  483. int pin;
  484. pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
  485. "pins", i, NULL);
  486. if (!pin_name)
  487. break;
  488. pin = sunxi_name_to_gpio(pin_name);
  489. if (pin < 0)
  490. continue;
  491. sunxi_gpio_set_cfgpin(pin, iomux);
  492. if (drive != ~0)
  493. sunxi_gpio_set_drv(pin, drive);
  494. if (pull != ~0)
  495. sunxi_gpio_set_pull(pin, pull);
  496. }
  497. if (!i) {
  498. printf("WARNING: emac: cannot find pins property\n");
  499. return -2;
  500. }
  501. return 0;
  502. }
  503. static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  504. {
  505. struct emac_eth_dev *priv = dev_get_priv(dev);
  506. u32 status, desc_num = priv->rx_currdescnum;
  507. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  508. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  509. int length;
  510. /* Invalidate entire buffer descriptor */
  511. cache_inv_descriptor(desc_p);
  512. status = desc_p->status;
  513. /* Check for DMA own bit */
  514. if (status & EMAC_DESC_OWN_DMA)
  515. return -EAGAIN;
  516. length = (status >> 16) & 0x3fff;
  517. /* make sure we read from DRAM, not our cache */
  518. invalidate_dcache_range(data_start,
  519. data_start + roundup(length, ARCH_DMA_MINALIGN));
  520. if (status & EMAC_DESC_RX_ERROR_MASK) {
  521. debug("RX: packet error: 0x%x\n",
  522. status & EMAC_DESC_RX_ERROR_MASK);
  523. return 0;
  524. }
  525. if (length < 0x40) {
  526. debug("RX: Bad Packet (runt)\n");
  527. return 0;
  528. }
  529. if (length > CONFIG_ETH_RXSIZE) {
  530. debug("RX: Too large packet (%d bytes)\n", length);
  531. return 0;
  532. }
  533. *packetp = (uchar *)(ulong)desc_p->buf_addr;
  534. return length;
  535. }
  536. static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
  537. {
  538. struct emac_eth_dev *priv = dev_get_priv(dev);
  539. u32 desc_num = priv->tx_currdescnum;
  540. struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
  541. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  542. uintptr_t data_end = data_start +
  543. roundup(length, ARCH_DMA_MINALIGN);
  544. desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
  545. memcpy((void *)data_start, packet, length);
  546. /* Flush data to be sent */
  547. flush_dcache_range(data_start, data_end);
  548. /* frame begin and end */
  549. desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
  550. desc_p->status = EMAC_DESC_OWN_DMA;
  551. /* make sure the MAC reads the actual data from DRAM */
  552. cache_clean_descriptor(desc_p);
  553. /* Move to next Descriptor and wrap around */
  554. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  555. desc_num = 0;
  556. priv->tx_currdescnum = desc_num;
  557. /* Start the DMA */
  558. setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
  559. /*
  560. * Since we copied the data above, we return here without waiting
  561. * for the packet to be actually send out.
  562. */
  563. return 0;
  564. }
  565. static int sun8i_emac_board_setup(struct udevice *dev,
  566. struct emac_eth_dev *priv)
  567. {
  568. int ret;
  569. ret = clk_enable(&priv->tx_clk);
  570. if (ret) {
  571. dev_err(dev, "failed to enable TX clock\n");
  572. return ret;
  573. }
  574. if (reset_valid(&priv->tx_rst)) {
  575. ret = reset_deassert(&priv->tx_rst);
  576. if (ret) {
  577. dev_err(dev, "failed to deassert TX reset\n");
  578. goto err_tx_clk;
  579. }
  580. }
  581. /* Only H3/H5 have clock controls for internal EPHY */
  582. if (clk_valid(&priv->ephy_clk)) {
  583. ret = clk_enable(&priv->ephy_clk);
  584. if (ret) {
  585. dev_err(dev, "failed to enable EPHY TX clock\n");
  586. return ret;
  587. }
  588. }
  589. if (reset_valid(&priv->ephy_rst)) {
  590. ret = reset_deassert(&priv->ephy_rst);
  591. if (ret) {
  592. dev_err(dev, "failed to deassert EPHY TX clock\n");
  593. return ret;
  594. }
  595. }
  596. return 0;
  597. err_tx_clk:
  598. clk_disable(&priv->tx_clk);
  599. return ret;
  600. }
  601. #if CONFIG_IS_ENABLED(DM_GPIO)
  602. static int sun8i_mdio_reset(struct mii_dev *bus)
  603. {
  604. struct udevice *dev = bus->priv;
  605. struct emac_eth_dev *priv = dev_get_priv(dev);
  606. struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
  607. int ret;
  608. if (!dm_gpio_is_valid(&priv->reset_gpio))
  609. return 0;
  610. /* reset the phy */
  611. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  612. if (ret)
  613. return ret;
  614. udelay(pdata->reset_delays[0]);
  615. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  616. if (ret)
  617. return ret;
  618. udelay(pdata->reset_delays[1]);
  619. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  620. if (ret)
  621. return ret;
  622. udelay(pdata->reset_delays[2]);
  623. return 0;
  624. }
  625. #endif
  626. static int sun8i_mdio_init(const char *name, struct udevice *priv)
  627. {
  628. struct mii_dev *bus = mdio_alloc();
  629. if (!bus) {
  630. debug("Failed to allocate MDIO bus\n");
  631. return -ENOMEM;
  632. }
  633. bus->read = sun8i_mdio_read;
  634. bus->write = sun8i_mdio_write;
  635. snprintf(bus->name, sizeof(bus->name), name);
  636. bus->priv = (void *)priv;
  637. #if CONFIG_IS_ENABLED(DM_GPIO)
  638. bus->reset = sun8i_mdio_reset;
  639. #endif
  640. return mdio_register(bus);
  641. }
  642. static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
  643. int length)
  644. {
  645. struct emac_eth_dev *priv = dev_get_priv(dev);
  646. u32 desc_num = priv->rx_currdescnum;
  647. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  648. /* give the current descriptor back to the MAC */
  649. desc_p->status |= EMAC_DESC_OWN_DMA;
  650. /* Flush Status field of descriptor */
  651. cache_clean_descriptor(desc_p);
  652. /* Move to next desc and wrap-around condition. */
  653. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  654. desc_num = 0;
  655. priv->rx_currdescnum = desc_num;
  656. return 0;
  657. }
  658. static void sun8i_emac_eth_stop(struct udevice *dev)
  659. {
  660. struct emac_eth_dev *priv = dev_get_priv(dev);
  661. /* Stop Rx/Tx transmitter */
  662. clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
  663. clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
  664. /* Stop RX/TX DMA */
  665. clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
  666. clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
  667. phy_shutdown(priv->phydev);
  668. }
  669. static int sun8i_emac_eth_probe(struct udevice *dev)
  670. {
  671. struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
  672. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  673. struct emac_eth_dev *priv = dev_get_priv(dev);
  674. int ret;
  675. priv->mac_reg = (void *)pdata->iobase;
  676. ret = sun8i_emac_board_setup(dev, priv);
  677. if (ret)
  678. return ret;
  679. sun8i_emac_set_syscon(sun8i_pdata, priv);
  680. sun8i_mdio_init(dev->name, dev);
  681. priv->bus = miiphy_get_dev_by_name(dev->name);
  682. return sun8i_phy_init(priv, dev);
  683. }
  684. static const struct eth_ops sun8i_emac_eth_ops = {
  685. .start = sun8i_emac_eth_start,
  686. .write_hwaddr = sun8i_eth_write_hwaddr,
  687. .send = sun8i_emac_eth_send,
  688. .recv = sun8i_emac_eth_recv,
  689. .free_pkt = sun8i_eth_free_pkt,
  690. .stop = sun8i_emac_eth_stop,
  691. };
  692. static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
  693. {
  694. struct ofnode_phandle_args phandle;
  695. int ret;
  696. ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
  697. NULL, 0, 0, &phandle);
  698. if (ret)
  699. return ret;
  700. /* If the PHY node is not a child of the internal MDIO bus, we are
  701. * using some external PHY.
  702. */
  703. if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
  704. "allwinner,sun8i-h3-mdio-internal"))
  705. return 0;
  706. ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
  707. if (ret) {
  708. dev_err(dev, "failed to get EPHY TX clock\n");
  709. return ret;
  710. }
  711. ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
  712. if (ret) {
  713. dev_err(dev, "failed to get EPHY TX reset\n");
  714. return ret;
  715. }
  716. priv->use_internal_phy = true;
  717. return 0;
  718. }
  719. static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
  720. {
  721. struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
  722. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  723. struct emac_eth_dev *priv = dev_get_priv(dev);
  724. const char *phy_mode;
  725. const fdt32_t *reg;
  726. int node = dev_of_offset(dev);
  727. int offset = 0;
  728. #if CONFIG_IS_ENABLED(DM_GPIO)
  729. int reset_flags = GPIOD_IS_OUT;
  730. #endif
  731. int ret;
  732. pdata->iobase = dev_read_addr(dev);
  733. if (pdata->iobase == FDT_ADDR_T_NONE) {
  734. debug("%s: Cannot find MAC base address\n", __func__);
  735. return -EINVAL;
  736. }
  737. priv->variant = dev_get_driver_data(dev);
  738. if (!priv->variant) {
  739. printf("%s: Missing variant\n", __func__);
  740. return -EINVAL;
  741. }
  742. ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
  743. if (ret) {
  744. dev_err(dev, "failed to get TX clock\n");
  745. return ret;
  746. }
  747. ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
  748. if (ret && ret != -ENOENT) {
  749. dev_err(dev, "failed to get TX reset\n");
  750. return ret;
  751. }
  752. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
  753. if (offset < 0) {
  754. debug("%s: cannot find syscon node\n", __func__);
  755. return -EINVAL;
  756. }
  757. reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
  758. if (!reg) {
  759. debug("%s: cannot find reg property in syscon node\n",
  760. __func__);
  761. return -EINVAL;
  762. }
  763. priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
  764. offset, reg);
  765. if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
  766. debug("%s: Cannot find syscon base address\n", __func__);
  767. return -EINVAL;
  768. }
  769. pdata->phy_interface = -1;
  770. priv->phyaddr = -1;
  771. priv->use_internal_phy = false;
  772. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
  773. if (offset < 0) {
  774. debug("%s: Cannot find PHY address\n", __func__);
  775. return -EINVAL;
  776. }
  777. priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  778. phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
  779. if (phy_mode)
  780. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  781. printf("phy interface%d\n", pdata->phy_interface);
  782. if (pdata->phy_interface == -1) {
  783. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  784. return -EINVAL;
  785. }
  786. if (priv->variant == H3_EMAC) {
  787. ret = sun8i_handle_internal_phy(dev, priv);
  788. if (ret)
  789. return ret;
  790. }
  791. priv->interface = pdata->phy_interface;
  792. if (!priv->use_internal_phy)
  793. parse_phy_pins(dev);
  794. sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  795. "allwinner,tx-delay-ps", 0);
  796. if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
  797. printf("%s: Invalid TX delay value %d\n", __func__,
  798. sun8i_pdata->tx_delay_ps);
  799. sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  800. "allwinner,rx-delay-ps", 0);
  801. if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
  802. printf("%s: Invalid RX delay value %d\n", __func__,
  803. sun8i_pdata->rx_delay_ps);
  804. #if CONFIG_IS_ENABLED(DM_GPIO)
  805. if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  806. "snps,reset-active-low"))
  807. reset_flags |= GPIOD_ACTIVE_LOW;
  808. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  809. &priv->reset_gpio, reset_flags);
  810. if (ret == 0) {
  811. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  812. "snps,reset-delays-us",
  813. sun8i_pdata->reset_delays, 3);
  814. } else if (ret == -ENOENT) {
  815. ret = 0;
  816. }
  817. #endif
  818. return 0;
  819. }
  820. static const struct udevice_id sun8i_emac_eth_ids[] = {
  821. {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
  822. {.compatible = "allwinner,sun50i-a64-emac",
  823. .data = (uintptr_t)A64_EMAC },
  824. {.compatible = "allwinner,sun8i-a83t-emac",
  825. .data = (uintptr_t)A83T_EMAC },
  826. {.compatible = "allwinner,sun8i-r40-gmac",
  827. .data = (uintptr_t)R40_GMAC },
  828. {.compatible = "allwinner,sun50i-h6-emac",
  829. .data = (uintptr_t)H6_EMAC },
  830. { }
  831. };
  832. U_BOOT_DRIVER(eth_sun8i_emac) = {
  833. .name = "eth_sun8i_emac",
  834. .id = UCLASS_ETH,
  835. .of_match = sun8i_emac_eth_ids,
  836. .of_to_plat = sun8i_emac_eth_of_to_plat,
  837. .probe = sun8i_emac_eth_probe,
  838. .ops = &sun8i_emac_eth_ops,
  839. .priv_auto = sizeof(struct emac_eth_dev),
  840. .plat_auto = sizeof(struct sun8i_eth_pdata),
  841. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  842. };