sni_netsec.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * netsec.c - Socionext Synquacer Netsec driver
  4. * Copyright 2021 Linaro Ltd.
  5. */
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdt_support.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <miiphy.h>
  13. #include <net.h>
  14. #include <regmap.h>
  15. #include <reset.h>
  16. #include <syscon.h>
  17. #include <asm/cache.h>
  18. #include <asm/global_data.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/io.h>
  24. #include <linux/iopoll.h>
  25. #include <spi.h>
  26. #include <spi_flash.h>
  27. #define NETSEC_REG_SOFT_RST 0x104
  28. #define NETSEC_REG_COM_INIT 0x120
  29. #define NETSEC_REG_TOP_STATUS 0x200
  30. #define NETSEC_IRQ_RX BIT(1)
  31. #define NETSEC_IRQ_TX BIT(0)
  32. #define NETSEC_REG_TOP_INTEN 0x204
  33. #define NETSEC_REG_INTEN_SET 0x234
  34. #define NETSEC_REG_INTEN_CLR 0x238
  35. #define NETSEC_REG_NRM_TX_STATUS 0x400
  36. #define NETSEC_REG_NRM_TX_INTEN 0x404
  37. #define NETSEC_REG_NRM_TX_INTEN_SET 0x428
  38. #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
  39. #define NRM_TX_ST_NTOWNR BIT(17)
  40. #define NRM_TX_ST_TR_ERR BIT(16)
  41. #define NRM_TX_ST_TXDONE BIT(15)
  42. #define NRM_TX_ST_TMREXP BIT(14)
  43. #define NETSEC_REG_NRM_RX_STATUS 0x440
  44. #define NETSEC_REG_NRM_RX_INTEN 0x444
  45. #define NETSEC_REG_NRM_RX_INTEN_SET 0x468
  46. #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
  47. #define NRM_RX_ST_RC_ERR BIT(16)
  48. #define NRM_RX_ST_PKTCNT BIT(15)
  49. #define NRM_RX_ST_TMREXP BIT(14)
  50. #define NETSEC_REG_PKT_CMD_BUF 0xd0
  51. #define NETSEC_REG_CLK_EN 0x100
  52. #define NETSEC_REG_PKT_CTRL 0x140
  53. #define NETSEC_REG_DMA_TMR_CTRL 0x20c
  54. #define NETSEC_REG_F_TAIKI_MC_VER 0x22c
  55. #define NETSEC_REG_F_TAIKI_VER 0x230
  56. #define NETSEC_REG_DMA_HM_CTRL 0x214
  57. #define NETSEC_REG_DMA_MH_CTRL 0x220
  58. #define NETSEC_REG_ADDR_DIS_CORE 0x218
  59. #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
  60. #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
  61. #define NETSEC_REG_NRM_TX_PKTCNT 0x410
  62. #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
  63. #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
  64. #define NETSEC_REG_NRM_TX_TMR 0x41c
  65. #define NETSEC_REG_NRM_RX_PKTCNT 0x454
  66. #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
  67. #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
  68. #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
  69. #define NETSEC_REG_NRM_RX_TMR 0x45c
  70. #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
  71. #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
  72. #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
  73. #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
  74. #define NETSEC_REG_NRM_TX_CONFIG 0x430
  75. #define NETSEC_REG_NRM_RX_CONFIG 0x470
  76. #define MAC_REG_STATUS 0x1024
  77. #define MAC_REG_DATA 0x11c0
  78. #define MAC_REG_CMD 0x11c4
  79. #define MAC_REG_FLOW_TH 0x11cc
  80. #define MAC_REG_INTF_SEL 0x11d4
  81. #define MAC_REG_DESC_INIT 0x11fc
  82. #define MAC_REG_DESC_SOFT_RST 0x1204
  83. #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
  84. #define GMAC_REG_MCR 0x0000
  85. #define GMAC_REG_MFFR 0x0004
  86. #define GMAC_REG_GAR 0x0010
  87. #define GMAC_REG_GDR 0x0014
  88. #define GMAC_REG_FCR 0x0018
  89. #define GMAC_REG_BMR 0x1000
  90. #define GMAC_REG_RDLAR 0x100c
  91. #define GMAC_REG_TDLAR 0x1010
  92. #define GMAC_REG_OMR 0x1018
  93. #define MHZ(n) ((n) * 1000 * 1000)
  94. #define NETSEC_TX_SHIFT_OWN_FIELD 31
  95. #define NETSEC_TX_SHIFT_LD_FIELD 30
  96. #define NETSEC_TX_SHIFT_DRID_FIELD 24
  97. #define NETSEC_TX_SHIFT_PT_FIELD 21
  98. #define NETSEC_TX_SHIFT_TDRID_FIELD 16
  99. #define NETSEC_TX_SHIFT_CC_FIELD 15
  100. #define NETSEC_TX_SHIFT_FS_FIELD 9
  101. #define NETSEC_TX_LAST 8
  102. #define NETSEC_TX_SHIFT_CO 7
  103. #define NETSEC_TX_SHIFT_SO 6
  104. #define NETSEC_TX_SHIFT_TRS_FIELD 4
  105. #define NETSEC_RX_PKT_OWN_FIELD 31
  106. #define NETSEC_RX_PKT_LD_FIELD 30
  107. #define NETSEC_RX_PKT_SDRID_FIELD 24
  108. #define NETSEC_RX_PKT_FR_FIELD 23
  109. #define NETSEC_RX_PKT_ER_FIELD 21
  110. #define NETSEC_RX_PKT_ERR_FIELD 16
  111. #define NETSEC_RX_PKT_TDRID_FIELD 12
  112. #define NETSEC_RX_PKT_FS_FIELD 9
  113. #define NETSEC_RX_PKT_LS_FIELD 8
  114. #define NETSEC_RX_PKT_CO_FIELD 6
  115. #define NETSEC_RX_PKT_ERR_MASK 3
  116. #define NETSEC_MAX_TX_PKT_LEN 1518
  117. #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
  118. #define NETSEC_RING_GMAC 15
  119. #define NETSEC_RING_MAX 2
  120. #define NETSEC_TCP_SEG_LEN_MAX 1460
  121. #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
  122. #define NETSEC_RX_CKSUM_NOTAVAIL 0
  123. #define NETSEC_RX_CKSUM_OK 1
  124. #define NETSEC_RX_CKSUM_NG 2
  125. #define NETSEC_TOP_IRQ_REG_ME_START BIT(20)
  126. #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
  127. #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
  128. #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
  129. #define NETSEC_INT_PKTCNT_MAX 2047
  130. #define NETSEC_FLOW_START_TH_MAX 95
  131. #define NETSEC_FLOW_STOP_TH_MAX 95
  132. #define NETSEC_FLOW_PAUSE_TIME_MIN 5
  133. #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
  134. #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
  135. #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
  136. #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
  137. #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
  138. #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
  139. #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
  140. #define NETSEC_CLK_EN_REG_DOM_G BIT(5)
  141. #define NETSEC_CLK_EN_REG_DOM_C BIT(1)
  142. #define NETSEC_CLK_EN_REG_DOM_D BIT(0)
  143. #define NETSEC_COM_INIT_REG_DB BIT(2)
  144. #define NETSEC_COM_INIT_REG_CLS BIT(1)
  145. #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
  146. NETSEC_COM_INIT_REG_DB)
  147. #define NETSEC_SOFT_RST_REG_RESET 0
  148. #define NETSEC_SOFT_RST_REG_RUN BIT(31)
  149. #define NETSEC_DMA_CTRL_REG_STOP 1
  150. #define MH_CTRL__MODE_TRANS BIT(20)
  151. #define NETSEC_GMAC_CMD_ST_READ 0
  152. #define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
  153. #define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
  154. #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
  155. #define NETSEC_GMAC_BMR_REG_RESET 0x00020181
  156. #define NETSEC_GMAC_BMR_REG_SWR 0x00000001
  157. #define NETSEC_GMAC_OMR_REG_ST BIT(13)
  158. #define NETSEC_GMAC_OMR_REG_SR BIT(1)
  159. #define NETSEC_GMAC_MCR_REG_IBN BIT(30)
  160. #define NETSEC_GMAC_MCR_REG_CST BIT(25)
  161. #define NETSEC_GMAC_MCR_REG_JE BIT(20)
  162. #define NETSEC_MCR_PS BIT(15)
  163. #define NETSEC_GMAC_MCR_REG_FES BIT(14)
  164. #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
  165. #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
  166. #define NETSEC_FCR_RFE BIT(2)
  167. #define NETSEC_FCR_TFE BIT(1)
  168. #define NETSEC_GMAC_GAR_REG_GW BIT(1)
  169. #define NETSEC_GMAC_GAR_REG_GB BIT(0)
  170. #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
  171. #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
  172. #define GMAC_REG_SHIFT_CR_GAR 2
  173. #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
  174. #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
  175. #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
  176. #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
  177. #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
  178. #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
  179. #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
  180. #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
  181. #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
  182. #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
  183. #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
  184. #define NETSEC_REG_DESC_TMR_MODE 4
  185. #define NETSEC_REG_DESC_ENDIAN 0
  186. #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
  187. #define NETSEC_MAC_DESC_INIT_REG_INIT 1
  188. #define NETSEC_EEPROM_MAC_ADDRESS 0x00
  189. #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
  190. #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
  191. #define NETSEC_EEPROM_HM_ME_SIZE 0x10
  192. #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
  193. #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
  194. #define NETSEC_EEPROM_MH_ME_SIZE 0x1C
  195. #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
  196. #define NETSEC_EEPROM_PKT_ME_SIZE 0x24
  197. #define DESC_SZ sizeof(struct netsec_de)
  198. #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
  199. #define EERPROM_MAP_OFFSET 0x8000000
  200. #define NOR_BLOCK 1024
  201. struct netsec_de { /* Netsec Descriptor layout */
  202. u32 attr;
  203. u32 data_buf_addr_up;
  204. u32 data_buf_addr_lw;
  205. u32 buf_len_info;
  206. };
  207. struct netsec_priv {
  208. struct netsec_de rxde[PKTBUFSRX];
  209. struct netsec_de txde[1];
  210. u16 rxat;
  211. phys_addr_t eeprom_base;
  212. phys_addr_t ioaddr;
  213. struct mii_dev *bus;
  214. struct phy_device *phydev;
  215. u32 phy_addr, freq;
  216. int phy_mode;
  217. int max_speed;
  218. };
  219. struct netsec_tx_pkt_ctrl {
  220. u16 tcp_seg_len;
  221. bool tcp_seg_offload_flag;
  222. bool cksum_offload_flag;
  223. };
  224. struct netsec_rx_pkt_info {
  225. int rx_cksum_result;
  226. int err_code;
  227. bool err_flag;
  228. };
  229. static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
  230. {
  231. writel(val, priv->ioaddr + reg_addr);
  232. }
  233. static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
  234. {
  235. return readl(priv->ioaddr + reg_addr);
  236. }
  237. /************* MDIO BUS OPS FOLLOW *************/
  238. #define TIMEOUT_SPINS_MAC 1000
  239. #define TIMEOUT_SECONDARY_MS_MAC 100
  240. static u32 netsec_clk_type(u32 freq)
  241. {
  242. if (freq < MHZ(35))
  243. return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
  244. if (freq < MHZ(60))
  245. return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
  246. if (freq < MHZ(100))
  247. return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
  248. if (freq < MHZ(150))
  249. return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
  250. if (freq < MHZ(250))
  251. return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
  252. return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
  253. }
  254. static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
  255. {
  256. u32 timeout = TIMEOUT_SPINS_MAC;
  257. while (--timeout && netsec_read_reg(priv, addr) & mask)
  258. cpu_relax();
  259. if (timeout)
  260. return 0;
  261. timeout = TIMEOUT_SECONDARY_MS_MAC;
  262. while (--timeout && netsec_read_reg(priv, addr) & mask)
  263. udelay(2000);
  264. if (timeout)
  265. return 0;
  266. pr_err("%s: timeout\n", __func__);
  267. return -ETIMEDOUT;
  268. }
  269. static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
  270. {
  271. netsec_write_reg(priv, MAC_REG_DATA, value);
  272. netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
  273. return netsec_wait_while_busy(priv,
  274. MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
  275. }
  276. static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
  277. {
  278. int ret;
  279. netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
  280. ret = netsec_wait_while_busy(priv,
  281. MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
  282. if (ret)
  283. return ret;
  284. *read = netsec_read_reg(priv, MAC_REG_DATA);
  285. return 0;
  286. }
  287. static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
  288. u32 addr, u32 mask)
  289. {
  290. u32 timeout = TIMEOUT_SPINS_MAC;
  291. u32 data;
  292. int ret;
  293. do {
  294. ret = netsec_get_mac_reg(priv, addr, &data);
  295. if (ret)
  296. break;
  297. udelay(1);
  298. } while (--timeout && (data & mask));
  299. if (timeout)
  300. return 0;
  301. timeout = TIMEOUT_SECONDARY_MS_MAC;
  302. do {
  303. udelay(2000);
  304. ret = netsec_get_mac_reg(priv, addr, &data);
  305. if (ret)
  306. break;
  307. cpu_relax();
  308. } while (--timeout && (data & mask));
  309. if (timeout && !ret)
  310. return 0;
  311. return -ETIMEDOUT;
  312. }
  313. static void netsec_cache_invalidate(uintptr_t vaddr, int len)
  314. {
  315. invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  316. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  317. }
  318. static void netsec_cache_flush(uintptr_t vaddr, int len)
  319. {
  320. flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  321. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  322. }
  323. static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
  324. {
  325. struct netsec_de *de = &priv->rxde[idx];
  326. u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
  327. (1 << NETSEC_RX_PKT_FS_FIELD) |
  328. (1 << NETSEC_RX_PKT_LS_FIELD);
  329. if (idx == PKTBUFSRX - 1)
  330. attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
  331. de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
  332. de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
  333. de->buf_len_info = PKTSIZE;
  334. de->attr = attr;
  335. dmb();
  336. netsec_cache_flush((uintptr_t)de, sizeof(*de));
  337. }
  338. static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
  339. {
  340. struct netsec_de *de = &priv->txde[0];
  341. u32 attr;
  342. attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
  343. (1 << NETSEC_TX_SHIFT_PT_FIELD) |
  344. (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
  345. (1 << NETSEC_TX_SHIFT_FS_FIELD) |
  346. (1 << NETSEC_TX_LAST) |
  347. (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
  348. (1 << NETSEC_TX_SHIFT_LD_FIELD);
  349. de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
  350. de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
  351. de->buf_len_info = len;
  352. de->attr = attr;
  353. dmb();
  354. netsec_cache_flush((uintptr_t)de, sizeof(*de));
  355. }
  356. static int netsec_get_phy_reg(struct netsec_priv *priv,
  357. int phy_addr, int reg_addr)
  358. {
  359. u32 data;
  360. int ret;
  361. if (phy_addr != 7)
  362. return -EINVAL;
  363. if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
  364. phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
  365. reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
  366. (netsec_clk_type(priv->freq) <<
  367. GMAC_REG_SHIFT_CR_GAR)))
  368. return -ETIMEDOUT;
  369. ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
  370. NETSEC_GMAC_GAR_REG_GB);
  371. if (ret)
  372. return ret;
  373. ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
  374. if (ret)
  375. return ret;
  376. return data;
  377. }
  378. static int netsec_set_phy_reg(struct netsec_priv *priv,
  379. int phy_addr, int reg_addr, u16 val)
  380. {
  381. int ret;
  382. if (phy_addr != 7)
  383. return -EINVAL;
  384. if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
  385. return -ETIMEDOUT;
  386. if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
  387. phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
  388. reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
  389. NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
  390. (netsec_clk_type(priv->freq) <<
  391. GMAC_REG_SHIFT_CR_GAR)))
  392. return -ETIMEDOUT;
  393. ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
  394. NETSEC_GMAC_GAR_REG_GB);
  395. /* Developerbox implements RTL8211E PHY and there is
  396. * a compatibility problem with F_GMAC4.
  397. * RTL8211E expects MDC clock must be kept toggling for several
  398. * clock cycle with MDIO high before entering the IDLE state.
  399. * To meet this requirement, netsec driver needs to issue dummy
  400. * read(e.g. read PHYID1(offset 0x2) register) right after write.
  401. */
  402. netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
  403. return ret;
  404. }
  405. static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
  406. {
  407. struct phy_device *phydev = priv->phydev;
  408. u32 value = 0;
  409. value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
  410. NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
  411. if (phydev->speed != SPEED_1000)
  412. value |= NETSEC_MCR_PS;
  413. if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
  414. phydev->speed == SPEED_100)
  415. value |= NETSEC_GMAC_MCR_REG_FES;
  416. value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
  417. if (phy_interface_is_rgmii(phydev))
  418. value |= NETSEC_GMAC_MCR_REG_IBN;
  419. if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
  420. return -ETIMEDOUT;
  421. return 0;
  422. }
  423. static int netsec_start_gmac(struct netsec_priv *priv)
  424. {
  425. u32 value = 0;
  426. int ret;
  427. if (priv->max_speed != SPEED_1000)
  428. value = (NETSEC_GMAC_MCR_REG_CST |
  429. NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
  430. if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
  431. return -ETIMEDOUT;
  432. if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
  433. NETSEC_GMAC_BMR_REG_RESET))
  434. return -ETIMEDOUT;
  435. /* Wait soft reset */
  436. mdelay(5);
  437. ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
  438. if (ret)
  439. return ret;
  440. if (value & NETSEC_GMAC_BMR_REG_SWR)
  441. return -EAGAIN;
  442. netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
  443. if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
  444. return -ETIMEDOUT;
  445. netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
  446. if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
  447. return -ETIMEDOUT;
  448. if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
  449. NETSEC_GMAC_BMR_REG_COMMON))
  450. return -ETIMEDOUT;
  451. if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
  452. NETSEC_GMAC_RDLAR_REG_COMMON))
  453. return -ETIMEDOUT;
  454. if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
  455. NETSEC_GMAC_TDLAR_REG_COMMON))
  456. return -ETIMEDOUT;
  457. if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
  458. return -ETIMEDOUT;
  459. ret = netsec_mac_update_to_phy_state(priv);
  460. if (ret)
  461. return ret;
  462. ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
  463. if (ret)
  464. return ret;
  465. value |= NETSEC_GMAC_OMR_REG_SR;
  466. value |= NETSEC_GMAC_OMR_REG_ST;
  467. netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
  468. netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
  469. if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
  470. return -ETIMEDOUT;
  471. return 0;
  472. }
  473. static int netsec_stop_gmac(struct netsec_priv *priv)
  474. {
  475. u32 value;
  476. int ret;
  477. ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
  478. if (ret)
  479. return ret;
  480. value &= ~NETSEC_GMAC_OMR_REG_SR;
  481. value &= ~NETSEC_GMAC_OMR_REG_ST;
  482. /* disable all interrupts */
  483. netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
  484. netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
  485. return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
  486. }
  487. static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
  488. {
  489. struct udevice *new;
  490. struct spi_flash *flash;
  491. spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
  492. CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new);
  493. flash = dev_get_uclass_priv(new);
  494. spi_flash_read(flash, offset, len, buf);
  495. }
  496. static int netsec_read_rom_hwaddr(struct udevice *dev)
  497. {
  498. struct netsec_priv *priv = dev_get_priv(dev);
  499. struct eth_pdata *pdata = dev_get_plat(dev);
  500. char macp[NOR_BLOCK];
  501. netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
  502. pdata->enetaddr[0] = readb(macp + 3);
  503. pdata->enetaddr[1] = readb(macp + 2);
  504. pdata->enetaddr[2] = readb(macp + 1);
  505. pdata->enetaddr[3] = readb(macp + 0);
  506. pdata->enetaddr[4] = readb(macp + 7);
  507. pdata->enetaddr[5] = readb(macp + 6);
  508. return 0;
  509. }
  510. static int netsec_send(struct udevice *dev, void *packet, int length)
  511. {
  512. struct netsec_priv *priv = dev_get_priv(dev);
  513. u32 val, tout;
  514. val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
  515. netsec_cache_flush((uintptr_t)packet, length);
  516. netsec_set_tx_de(priv, packet, length);
  517. netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
  518. val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
  519. tout = 10000;
  520. do {
  521. val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
  522. udelay(2);
  523. } while (--tout && !val);
  524. if (!tout) {
  525. val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
  526. pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val);
  527. return -ETIMEDOUT;
  528. }
  529. return 0;
  530. }
  531. static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
  532. {
  533. struct netsec_priv *priv = dev_get_priv(dev);
  534. netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
  535. priv->rxat++;
  536. if (priv->rxat == PKTBUFSRX)
  537. priv->rxat = 0;
  538. return 0;
  539. }
  540. static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
  541. {
  542. struct netsec_priv *priv = dev_get_priv(dev);
  543. int idx = priv->rxat;
  544. uchar *ptr = net_rx_packets[idx];
  545. struct netsec_de *de = &priv->rxde[idx];
  546. int length = 0;
  547. netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
  548. if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
  549. return -EAGAIN;
  550. length = de->buf_len_info >> 16;
  551. /* invalidate after DMA is done */
  552. netsec_cache_invalidate((uintptr_t)ptr, length);
  553. *packetp = ptr;
  554. return length;
  555. }
  556. static int _netsec_get_phy_reg(struct mii_dev *bus,
  557. int phy_addr, int devad, int reg_addr)
  558. {
  559. return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
  560. }
  561. static int _netsec_set_phy_reg(struct mii_dev *bus,
  562. int phy_addr, int devad, int reg_addr, u16 val)
  563. {
  564. return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
  565. }
  566. static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
  567. {
  568. struct mii_dev *bus = mdio_alloc();
  569. if (!bus)
  570. return -ENOMEM;
  571. bus->read = _netsec_get_phy_reg;
  572. bus->write = _netsec_set_phy_reg;
  573. snprintf(bus->name, sizeof(bus->name), "%s", name);
  574. bus->priv = priv;
  575. return mdio_register(bus);
  576. }
  577. static int netsec_phy_init(struct netsec_priv *priv, void *dev)
  578. {
  579. struct phy_device *phydev;
  580. int ret;
  581. phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
  582. phydev->supported &= PHY_GBIT_FEATURES;
  583. if (priv->max_speed) {
  584. ret = phy_set_supported(phydev, priv->max_speed);
  585. if (ret)
  586. return ret;
  587. }
  588. phydev->advertising = phydev->supported;
  589. priv->phydev = phydev;
  590. phy_config(phydev);
  591. return 0;
  592. }
  593. static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
  594. u32 addr_h, u32 addr_l, u32 size)
  595. {
  596. u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
  597. while (size > 0) {
  598. char buf[NOR_BLOCK];
  599. u32 *ucode = (u32 *)buf;
  600. u64 off;
  601. int i;
  602. off = base % NOR_BLOCK;
  603. base -= off;
  604. netsec_spi_read(buf, sizeof(buf), base);
  605. for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
  606. netsec_write_reg(priv, reg, ucode[i]);
  607. base += NOR_BLOCK;
  608. }
  609. return 0;
  610. }
  611. static int netsec_netdev_load_microcode(struct netsec_priv *priv)
  612. {
  613. u32 addr_h, addr_l, size;
  614. char buf[NOR_BLOCK];
  615. u32 *ucinfo = (u32 *)buf;
  616. int err;
  617. netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
  618. addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
  619. addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
  620. size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
  621. err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
  622. addr_h, addr_l, size);
  623. if (err)
  624. return err;
  625. addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
  626. addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
  627. size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
  628. err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
  629. addr_h, addr_l, size);
  630. if (err)
  631. return err;
  632. addr_h = 0;
  633. addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
  634. size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
  635. err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
  636. addr_h, addr_l, size);
  637. if (err)
  638. return err;
  639. return 0;
  640. }
  641. void netsec_pre_init_microengine(struct netsec_priv *priv)
  642. {
  643. u32 data;
  644. /* Remove dormant settings */
  645. data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
  646. data &= ~BMCR_PDOWN;
  647. data |= BMCR_ISOLATE;
  648. netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
  649. mdelay(100);
  650. /* Put phy in loopback mode to guarantee RXCLK input */
  651. data |= BMCR_LOOPBACK;
  652. netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
  653. mdelay(100);
  654. }
  655. void netsec_post_init_microengine(struct netsec_priv *priv)
  656. {
  657. u32 data;
  658. /* Get phy back to normal operation */
  659. data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
  660. data &= ~BMCR_LOOPBACK;
  661. netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
  662. mdelay(100);
  663. /* Apply software reset */
  664. data |= BMCR_RESET;
  665. netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
  666. mdelay(100);
  667. }
  668. static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
  669. {
  670. u32 value;
  671. int err;
  672. netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
  673. /* stop DMA engines */
  674. if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
  675. netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
  676. NETSEC_DMA_CTRL_REG_STOP);
  677. netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
  678. NETSEC_DMA_CTRL_REG_STOP);
  679. value = 100;
  680. while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
  681. NETSEC_DMA_CTRL_REG_STOP) {
  682. udelay(1000);
  683. if (--value == 0) {
  684. pr_err("%s:%d timeout!\n", __func__, __LINE__);
  685. break;
  686. }
  687. }
  688. value = 100;
  689. while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
  690. NETSEC_DMA_CTRL_REG_STOP) {
  691. udelay(1000);
  692. if (--value == 0) {
  693. pr_err("%s:%d timeout!\n", __func__, __LINE__);
  694. break;
  695. }
  696. }
  697. }
  698. netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
  699. netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
  700. netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
  701. netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
  702. value = 100;
  703. while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
  704. udelay(1000);
  705. if (--value == 0) {
  706. pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
  707. break;
  708. }
  709. }
  710. /* MAC desc init */
  711. netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
  712. netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
  713. /* set MAC_INTF_SEL */
  714. netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
  715. netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
  716. /* set desc_start addr */
  717. netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
  718. upper_32_bits((dma_addr_t)priv->rxde));
  719. netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
  720. lower_32_bits((dma_addr_t)priv->rxde));
  721. netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
  722. upper_32_bits((dma_addr_t)priv->txde));
  723. netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
  724. lower_32_bits((dma_addr_t)priv->txde));
  725. /* set normal tx dring ring config */
  726. netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
  727. 1 << NETSEC_REG_DESC_ENDIAN);
  728. netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
  729. 1 << NETSEC_REG_DESC_ENDIAN);
  730. if (load_ucode) {
  731. err = netsec_netdev_load_microcode(priv);
  732. if (err) {
  733. pr_err("%s: failed to load microcode (%d)\n",
  734. __func__, err);
  735. return err;
  736. }
  737. }
  738. /* set desc_start addr */
  739. netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
  740. upper_32_bits((dma_addr_t)priv->rxde));
  741. netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
  742. lower_32_bits((dma_addr_t)priv->rxde));
  743. netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
  744. upper_32_bits((dma_addr_t)priv->txde));
  745. netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
  746. lower_32_bits((dma_addr_t)priv->txde));
  747. netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
  748. /* start DMA engines */
  749. netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
  750. netsec_pre_init_microengine(priv);
  751. netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
  752. mdelay(100);
  753. if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
  754. NETSEC_TOP_IRQ_REG_ME_START)) {
  755. pr_err("microengine start failed\n");
  756. return -ENXIO;
  757. }
  758. netsec_post_init_microengine(priv);
  759. /* clear microcode load end status */
  760. netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
  761. NETSEC_TOP_IRQ_REG_ME_START);
  762. netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
  763. value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
  764. value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
  765. /* change to normal mode */
  766. netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
  767. netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
  768. value = 100;
  769. while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
  770. NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
  771. udelay(1000);
  772. if (--value == 0) {
  773. value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
  774. pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
  775. break;
  776. }
  777. }
  778. /* clear any pending EMPTY/ERR irq status */
  779. netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
  780. /* Disable TX & RX intr */
  781. netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
  782. return 0;
  783. }
  784. static void netsec_stop(struct udevice *dev)
  785. {
  786. struct netsec_priv *priv = dev_get_priv(dev);
  787. netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
  788. netsec_stop_gmac(priv);
  789. phy_shutdown(priv->phydev);
  790. netsec_reset_hardware(priv, false);
  791. }
  792. static int netsec_start(struct udevice *dev)
  793. {
  794. struct netsec_priv *priv = dev_get_priv(dev);
  795. int i;
  796. phy_startup(priv->phydev);
  797. netsec_start_gmac(priv);
  798. priv->rxat = 0;
  799. for (i = 0; i < PKTBUFSRX; i++)
  800. netsec_set_rx_de(priv, i, net_rx_packets[i]);
  801. return 0;
  802. }
  803. static int netsec_of_to_plat(struct udevice *dev)
  804. {
  805. struct eth_pdata *pdata = dev_get_plat(dev);
  806. struct netsec_priv *priv = dev_get_priv(dev);
  807. struct ofnode_phandle_args phandle_args;
  808. const char *phy_mode;
  809. pdata->iobase = dev_read_addr_index(dev, 0);
  810. priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
  811. pdata->phy_interface = -1;
  812. phy_mode = dev_read_prop(dev, "phy-mode", NULL);
  813. if (phy_mode)
  814. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  815. if (pdata->phy_interface == -1) {
  816. pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  817. return -EINVAL;
  818. }
  819. if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  820. &phandle_args))
  821. priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
  822. else
  823. priv->phy_addr = 7;
  824. pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
  825. priv->ioaddr = pdata->iobase;
  826. priv->phy_mode = pdata->phy_interface;
  827. priv->max_speed = pdata->max_speed;
  828. priv->freq = 250000000UL;
  829. return 0;
  830. }
  831. static int netsec_probe(struct udevice *dev)
  832. {
  833. struct netsec_priv *priv = dev_get_priv(dev);
  834. int ret;
  835. netsec_reset_hardware(priv, true);
  836. ret = netsec_mdiobus_init(priv, dev->name);
  837. if (ret) {
  838. pr_err("Failed to initialize mdiobus: %d\n", ret);
  839. return ret;
  840. }
  841. priv->bus = miiphy_get_dev_by_name(dev->name);
  842. ret = netsec_phy_init(priv, dev);
  843. if (ret) {
  844. pr_err("Failed to initialize phy: %d\n", ret);
  845. goto out_mdiobus_release;
  846. }
  847. return 0;
  848. out_mdiobus_release:
  849. mdio_unregister(priv->bus);
  850. mdio_free(priv->bus);
  851. return ret;
  852. }
  853. static int netsec_remove(struct udevice *dev)
  854. {
  855. struct netsec_priv *priv = dev_get_priv(dev);
  856. free(priv->phydev);
  857. mdio_unregister(priv->bus);
  858. mdio_free(priv->bus);
  859. return 0;
  860. }
  861. static const struct eth_ops netsec_ops = {
  862. .start = netsec_start,
  863. .stop = netsec_stop,
  864. .send = netsec_send,
  865. .recv = netsec_recv,
  866. .free_pkt = netsec_free_packet,
  867. .read_rom_hwaddr = netsec_read_rom_hwaddr,
  868. };
  869. static const struct udevice_id netsec_ids[] = {
  870. {
  871. .compatible = "socionext,synquacer-netsec",
  872. },
  873. {}
  874. };
  875. U_BOOT_DRIVER(ave) = {
  876. .name = "synquacer_netsec",
  877. .id = UCLASS_ETH,
  878. .of_match = netsec_ids,
  879. .probe = netsec_probe,
  880. .remove = netsec_remove,
  881. .of_to_plat = netsec_of_to_plat,
  882. .ops = &netsec_ops,
  883. .priv_auto = sizeof(struct netsec_priv),
  884. .plat_auto = sizeof(struct eth_pdata),
  885. };