sni_ave.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * sni_ave.c - Socionext UniPhier AVE ethernet driver
  4. * Copyright 2016-2018 Socionext inc.
  5. */
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdt_support.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <miiphy.h>
  13. #include <net.h>
  14. #include <regmap.h>
  15. #include <reset.h>
  16. #include <syscon.h>
  17. #include <asm/cache.h>
  18. #include <asm/global_data.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/io.h>
  24. #include <linux/iopoll.h>
  25. #define AVE_GRST_DELAY_MSEC 40
  26. #define AVE_MIN_XMITSIZE 60
  27. #define AVE_SEND_TIMEOUT_COUNT 1000
  28. #define AVE_MDIO_TIMEOUT_USEC 10000
  29. #define AVE_HALT_TIMEOUT_USEC 10000
  30. /* General Register Group */
  31. #define AVE_IDR 0x000 /* ID */
  32. #define AVE_VR 0x004 /* Version */
  33. #define AVE_GRR 0x008 /* Global Reset */
  34. #define AVE_CFGR 0x00c /* Configuration */
  35. /* Interrupt Register Group */
  36. #define AVE_GIMR 0x100 /* Global Interrupt Mask */
  37. #define AVE_GISR 0x104 /* Global Interrupt Status */
  38. /* MAC Register Group */
  39. #define AVE_TXCR 0x200 /* TX Setup */
  40. #define AVE_RXCR 0x204 /* RX Setup */
  41. #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
  42. #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
  43. #define AVE_MDIOCTR 0x214 /* MDIO Control */
  44. #define AVE_MDIOAR 0x218 /* MDIO Address */
  45. #define AVE_MDIOWDR 0x21c /* MDIO Data */
  46. #define AVE_MDIOSR 0x220 /* MDIO Status */
  47. #define AVE_MDIORDR 0x224 /* MDIO Rd Data */
  48. /* Descriptor Control Register Group */
  49. #define AVE_DESCC 0x300 /* Descriptor Control */
  50. #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
  51. #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
  52. #define AVE_IIRQC 0x34c /* Interval IRQ Control */
  53. /* 64bit descriptor memory */
  54. #define AVE_DESC_SIZE_64 12 /* Descriptor Size */
  55. #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
  56. #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
  57. /* 32bit descriptor memory */
  58. #define AVE_DESC_SIZE_32 8 /* Descriptor Size */
  59. #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
  60. #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
  61. /* RMII Bridge Register Group */
  62. #define AVE_RSTCTRL 0x8028 /* Reset control */
  63. #define AVE_RSTCTRL_RMIIRST BIT(16)
  64. #define AVE_LINKSEL 0x8034 /* Link speed setting */
  65. #define AVE_LINKSEL_100M BIT(0)
  66. /* AVE_GRR */
  67. #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
  68. #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
  69. /* AVE_CFGR */
  70. #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
  71. /* AVE_GISR (common with GIMR) */
  72. #define AVE_GIMR_CLR 0
  73. #define AVE_GISR_CLR GENMASK(31, 0)
  74. /* AVE_TXCR */
  75. #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
  76. #define AVE_TXCR_TXSPD_1G BIT(17)
  77. #define AVE_TXCR_TXSPD_100 BIT(16)
  78. /* AVE_RXCR */
  79. #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
  80. #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
  81. #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
  82. /* AVE_MDIOCTR */
  83. #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
  84. #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
  85. /* AVE_MDIOSR */
  86. #define AVE_MDIOSR_STS BIT(0) /* access status */
  87. /* AVE_DESCC */
  88. #define AVE_DESCC_RXDSTPSTS BIT(20)
  89. #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
  90. #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */
  91. #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
  92. /* AVE_TXDC/RXDC */
  93. #define AVE_DESC_SIZE(priv, num) \
  94. ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
  95. AVE_DESC_SIZE_32))
  96. /* Command status for descriptor */
  97. #define AVE_STS_OWN BIT(31) /* Descriptor ownership */
  98. #define AVE_STS_OK BIT(27) /* Normal transmit */
  99. #define AVE_STS_1ST BIT(26) /* Head of buffer chain */
  100. #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
  101. #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
  102. #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
  103. #define AVE_DESC_OFS_CMDSTS 0
  104. #define AVE_DESC_OFS_ADDRL 4
  105. #define AVE_DESC_OFS_ADDRU 8
  106. /* Parameter for ethernet frame */
  107. #define AVE_RXCR_MTU 1518
  108. /* SG */
  109. #define SG_ETPINMODE 0x540
  110. #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
  111. #define SG_ETPINMODE_RMII(ins) BIT(ins)
  112. #define AVE_MAX_CLKS 4
  113. #define AVE_MAX_RSTS 2
  114. enum desc_id {
  115. AVE_DESCID_TX,
  116. AVE_DESCID_RX,
  117. };
  118. struct ave_private {
  119. phys_addr_t iobase;
  120. unsigned int nclks;
  121. struct clk clk[AVE_MAX_CLKS];
  122. unsigned int nrsts;
  123. struct reset_ctl rst[AVE_MAX_RSTS];
  124. struct regmap *regmap;
  125. unsigned int regmap_arg;
  126. struct mii_dev *bus;
  127. struct phy_device *phydev;
  128. int phy_mode;
  129. int max_speed;
  130. int rx_pos;
  131. int rx_siz;
  132. int rx_off;
  133. int tx_num;
  134. u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
  135. void *tx_adj_buf;
  136. const struct ave_soc_data *data;
  137. };
  138. struct ave_soc_data {
  139. bool is_desc_64bit;
  140. const char *clock_names[AVE_MAX_CLKS];
  141. const char *reset_names[AVE_MAX_RSTS];
  142. int (*get_pinmode)(struct ave_private *priv);
  143. };
  144. static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
  145. int offset)
  146. {
  147. int desc_size;
  148. u32 addr;
  149. if (priv->data->is_desc_64bit) {
  150. desc_size = AVE_DESC_SIZE_64;
  151. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
  152. } else {
  153. desc_size = AVE_DESC_SIZE_32;
  154. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
  155. }
  156. addr += entry * desc_size + offset;
  157. return readl(priv->iobase + addr);
  158. }
  159. static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
  160. int entry)
  161. {
  162. return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
  163. }
  164. static void ave_desc_write(struct ave_private *priv, enum desc_id id,
  165. int entry, int offset, u32 val)
  166. {
  167. int desc_size;
  168. u32 addr;
  169. if (priv->data->is_desc_64bit) {
  170. desc_size = AVE_DESC_SIZE_64;
  171. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
  172. } else {
  173. desc_size = AVE_DESC_SIZE_32;
  174. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
  175. }
  176. addr += entry * desc_size + offset;
  177. writel(val, priv->iobase + addr);
  178. }
  179. static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
  180. int entry, u32 val)
  181. {
  182. ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
  183. }
  184. static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
  185. int entry, uintptr_t paddr)
  186. {
  187. ave_desc_write(priv, id, entry,
  188. AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
  189. if (priv->data->is_desc_64bit)
  190. ave_desc_write(priv, id, entry,
  191. AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
  192. }
  193. static void ave_cache_invalidate(uintptr_t vaddr, int len)
  194. {
  195. invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  196. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  197. }
  198. static void ave_cache_flush(uintptr_t vaddr, int len)
  199. {
  200. flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  201. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  202. }
  203. static int ave_mdiobus_read(struct mii_dev *bus,
  204. int phyid, int devad, int regnum)
  205. {
  206. struct ave_private *priv = bus->priv;
  207. u32 mdioctl, mdiosr;
  208. int ret;
  209. /* write address */
  210. writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
  211. /* read request */
  212. mdioctl = readl(priv->iobase + AVE_MDIOCTR);
  213. writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
  214. ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
  215. !(mdiosr & AVE_MDIOSR_STS),
  216. AVE_MDIO_TIMEOUT_USEC);
  217. if (ret) {
  218. pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
  219. priv->phydev->dev->name, phyid, regnum);
  220. return ret;
  221. }
  222. return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
  223. }
  224. static int ave_mdiobus_write(struct mii_dev *bus,
  225. int phyid, int devad, int regnum, u16 val)
  226. {
  227. struct ave_private *priv = bus->priv;
  228. u32 mdioctl, mdiosr;
  229. int ret;
  230. /* write address */
  231. writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
  232. /* write data */
  233. writel(val, priv->iobase + AVE_MDIOWDR);
  234. /* write request */
  235. mdioctl = readl(priv->iobase + AVE_MDIOCTR);
  236. writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
  237. priv->iobase + AVE_MDIOCTR);
  238. ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
  239. !(mdiosr & AVE_MDIOSR_STS),
  240. AVE_MDIO_TIMEOUT_USEC);
  241. if (ret)
  242. pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
  243. priv->phydev->dev->name, phyid, regnum);
  244. return ret;
  245. }
  246. static int ave_adjust_link(struct ave_private *priv)
  247. {
  248. struct phy_device *phydev = priv->phydev;
  249. struct eth_pdata *pdata = dev_get_plat(phydev->dev);
  250. u32 val, txcr, rxcr, rxcr_org;
  251. u16 rmt_adv = 0, lcl_adv = 0;
  252. u8 cap;
  253. /* set RGMII speed */
  254. val = readl(priv->iobase + AVE_TXCR);
  255. val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
  256. if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
  257. val |= AVE_TXCR_TXSPD_1G;
  258. else if (phydev->speed == SPEED_100)
  259. val |= AVE_TXCR_TXSPD_100;
  260. writel(val, priv->iobase + AVE_TXCR);
  261. /* set RMII speed (100M/10M only) */
  262. if (!phy_interface_is_rgmii(phydev)) {
  263. val = readl(priv->iobase + AVE_LINKSEL);
  264. if (phydev->speed == SPEED_10)
  265. val &= ~AVE_LINKSEL_100M;
  266. else
  267. val |= AVE_LINKSEL_100M;
  268. writel(val, priv->iobase + AVE_LINKSEL);
  269. }
  270. /* check current RXCR/TXCR */
  271. rxcr = readl(priv->iobase + AVE_RXCR);
  272. txcr = readl(priv->iobase + AVE_TXCR);
  273. rxcr_org = rxcr;
  274. if (phydev->duplex) {
  275. rxcr |= AVE_RXCR_FDUPEN;
  276. if (phydev->pause)
  277. rmt_adv |= LPA_PAUSE_CAP;
  278. if (phydev->asym_pause)
  279. rmt_adv |= LPA_PAUSE_ASYM;
  280. if (phydev->advertising & ADVERTISED_Pause)
  281. lcl_adv |= ADVERTISE_PAUSE_CAP;
  282. if (phydev->advertising & ADVERTISED_Asym_Pause)
  283. lcl_adv |= ADVERTISE_PAUSE_ASYM;
  284. cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  285. if (cap & FLOW_CTRL_TX)
  286. txcr |= AVE_TXCR_FLOCTR;
  287. else
  288. txcr &= ~AVE_TXCR_FLOCTR;
  289. if (cap & FLOW_CTRL_RX)
  290. rxcr |= AVE_RXCR_FLOCTR;
  291. else
  292. rxcr &= ~AVE_RXCR_FLOCTR;
  293. } else {
  294. rxcr &= ~AVE_RXCR_FDUPEN;
  295. rxcr &= ~AVE_RXCR_FLOCTR;
  296. txcr &= ~AVE_TXCR_FLOCTR;
  297. }
  298. if (rxcr_org != rxcr) {
  299. /* disable Rx mac */
  300. writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
  301. /* change and enable TX/Rx mac */
  302. writel(txcr, priv->iobase + AVE_TXCR);
  303. writel(rxcr, priv->iobase + AVE_RXCR);
  304. }
  305. pr_notice("%s: phy:%s speed:%d mac:%pM\n",
  306. phydev->dev->name, phydev->drv->name, phydev->speed,
  307. pdata->enetaddr);
  308. return phydev->link;
  309. }
  310. static int ave_mdiobus_init(struct ave_private *priv, const char *name)
  311. {
  312. struct mii_dev *bus = mdio_alloc();
  313. if (!bus)
  314. return -ENOMEM;
  315. bus->read = ave_mdiobus_read;
  316. bus->write = ave_mdiobus_write;
  317. snprintf(bus->name, sizeof(bus->name), "%s", name);
  318. bus->priv = priv;
  319. return mdio_register(bus);
  320. }
  321. static int ave_phy_init(struct ave_private *priv, void *dev)
  322. {
  323. struct phy_device *phydev;
  324. int mask = GENMASK(31, 0), ret;
  325. phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
  326. if (!phydev)
  327. return -ENODEV;
  328. phy_connect_dev(phydev, dev);
  329. phydev->supported &= PHY_GBIT_FEATURES;
  330. if (priv->max_speed) {
  331. ret = phy_set_supported(phydev, priv->max_speed);
  332. if (ret)
  333. return ret;
  334. }
  335. phydev->advertising = phydev->supported;
  336. priv->phydev = phydev;
  337. phy_config(phydev);
  338. return 0;
  339. }
  340. static void ave_stop(struct udevice *dev)
  341. {
  342. struct ave_private *priv = dev_get_priv(dev);
  343. u32 val;
  344. int ret;
  345. val = readl(priv->iobase + AVE_GRR);
  346. if (val)
  347. return;
  348. val = readl(priv->iobase + AVE_RXCR);
  349. val &= ~AVE_RXCR_RXEN;
  350. writel(val, priv->iobase + AVE_RXCR);
  351. writel(0, priv->iobase + AVE_DESCC);
  352. ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
  353. AVE_HALT_TIMEOUT_USEC);
  354. if (ret)
  355. pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
  356. writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
  357. phy_shutdown(priv->phydev);
  358. }
  359. static void ave_reset(struct ave_private *priv)
  360. {
  361. u32 val;
  362. /* reset RMII register */
  363. val = readl(priv->iobase + AVE_RSTCTRL);
  364. val &= ~AVE_RSTCTRL_RMIIRST;
  365. writel(val, priv->iobase + AVE_RSTCTRL);
  366. /* assert reset */
  367. writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
  368. mdelay(AVE_GRST_DELAY_MSEC);
  369. /* 1st, negate PHY reset only */
  370. writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
  371. mdelay(AVE_GRST_DELAY_MSEC);
  372. /* negate reset */
  373. writel(0, priv->iobase + AVE_GRR);
  374. mdelay(AVE_GRST_DELAY_MSEC);
  375. /* negate RMII register */
  376. val = readl(priv->iobase + AVE_RSTCTRL);
  377. val |= AVE_RSTCTRL_RMIIRST;
  378. writel(val, priv->iobase + AVE_RSTCTRL);
  379. }
  380. static int ave_start(struct udevice *dev)
  381. {
  382. struct ave_private *priv = dev_get_priv(dev);
  383. uintptr_t paddr;
  384. u32 val;
  385. int i;
  386. ave_reset(priv);
  387. priv->rx_pos = 0;
  388. priv->rx_off = 2; /* RX data has 2byte offsets */
  389. priv->tx_num = 0;
  390. priv->tx_adj_buf =
  391. (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
  392. PKTALIGN);
  393. priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
  394. val = 0;
  395. if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
  396. val |= AVE_CFGR_MII;
  397. writel(val, priv->iobase + AVE_CFGR);
  398. /* use one descriptor for Tx */
  399. writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
  400. ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
  401. ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
  402. /* use PKTBUFSRX descriptors for Rx */
  403. writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
  404. for (i = 0; i < PKTBUFSRX; i++) {
  405. paddr = (uintptr_t)net_rx_packets[i];
  406. ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
  407. ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
  408. ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
  409. }
  410. writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
  411. writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
  412. writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
  413. priv->iobase + AVE_RXCR);
  414. writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
  415. phy_startup(priv->phydev);
  416. ave_adjust_link(priv);
  417. return 0;
  418. }
  419. static int ave_write_hwaddr(struct udevice *dev)
  420. {
  421. struct ave_private *priv = dev_get_priv(dev);
  422. struct eth_pdata *pdata = dev_get_plat(dev);
  423. u8 *mac = pdata->enetaddr;
  424. writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
  425. priv->iobase + AVE_RXMAC1R);
  426. writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
  427. return 0;
  428. }
  429. static int ave_send(struct udevice *dev, void *packet, int length)
  430. {
  431. struct ave_private *priv = dev_get_priv(dev);
  432. u32 val;
  433. void *ptr = packet;
  434. int count;
  435. /* adjust alignment for descriptor */
  436. if ((uintptr_t)ptr & 0x3) {
  437. memcpy(priv->tx_adj_buf, (const void *)ptr, length);
  438. ptr = priv->tx_adj_buf;
  439. }
  440. /* padding for minimum length */
  441. if (length < AVE_MIN_XMITSIZE) {
  442. memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
  443. length = AVE_MIN_XMITSIZE;
  444. }
  445. /* check ownership and wait for previous xmit done */
  446. count = AVE_SEND_TIMEOUT_COUNT;
  447. do {
  448. val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
  449. } while ((val & AVE_STS_OWN) && --count);
  450. if (!count)
  451. return -ETIMEDOUT;
  452. ave_cache_flush((uintptr_t)ptr, length);
  453. ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
  454. val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
  455. (length & AVE_STS_PKTLEN_TX_MASK);
  456. ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
  457. priv->tx_num++;
  458. count = AVE_SEND_TIMEOUT_COUNT;
  459. do {
  460. val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
  461. } while ((val & AVE_STS_OWN) && --count);
  462. if (!count)
  463. return -ETIMEDOUT;
  464. if (!(val & AVE_STS_OK))
  465. pr_warn("%s: bad send packet status:%08x\n",
  466. priv->phydev->dev->name, le32_to_cpu(val));
  467. return 0;
  468. }
  469. static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
  470. {
  471. struct ave_private *priv = dev_get_priv(dev);
  472. uchar *ptr;
  473. int length = 0;
  474. u32 cmdsts;
  475. while (1) {
  476. cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
  477. priv->rx_pos);
  478. if (!(cmdsts & AVE_STS_OWN))
  479. /* hardware ownership, no received packets */
  480. return -EAGAIN;
  481. ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
  482. if (cmdsts & AVE_STS_OK)
  483. break;
  484. pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
  485. priv->phydev->dev->name, priv->rx_pos,
  486. le32_to_cpu(cmdsts), ptr);
  487. }
  488. length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
  489. /* invalidate after DMA is done */
  490. ave_cache_invalidate((uintptr_t)ptr, length);
  491. *packetp = ptr;
  492. return length;
  493. }
  494. static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
  495. {
  496. struct ave_private *priv = dev_get_priv(dev);
  497. ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
  498. priv->rx_siz + priv->rx_off);
  499. ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
  500. priv->rx_pos, priv->rx_siz);
  501. if (++priv->rx_pos >= PKTBUFSRX)
  502. priv->rx_pos = 0;
  503. return 0;
  504. }
  505. static int ave_pro4_get_pinmode(struct ave_private *priv)
  506. {
  507. u32 reg, mask, val = 0;
  508. if (priv->regmap_arg > 0)
  509. return -EINVAL;
  510. mask = SG_ETPINMODE_RMII(0);
  511. switch (priv->phy_mode) {
  512. case PHY_INTERFACE_MODE_RMII:
  513. val = SG_ETPINMODE_RMII(0);
  514. break;
  515. case PHY_INTERFACE_MODE_MII:
  516. case PHY_INTERFACE_MODE_RGMII:
  517. break;
  518. default:
  519. return -EINVAL;
  520. }
  521. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  522. reg &= ~mask;
  523. reg |= val;
  524. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  525. return 0;
  526. }
  527. static int ave_ld11_get_pinmode(struct ave_private *priv)
  528. {
  529. u32 reg, mask, val = 0;
  530. if (priv->regmap_arg > 0)
  531. return -EINVAL;
  532. mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
  533. switch (priv->phy_mode) {
  534. case PHY_INTERFACE_MODE_INTERNAL:
  535. break;
  536. case PHY_INTERFACE_MODE_RMII:
  537. val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
  538. break;
  539. default:
  540. return -EINVAL;
  541. }
  542. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  543. reg &= ~mask;
  544. reg |= val;
  545. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  546. return 0;
  547. }
  548. static int ave_ld20_get_pinmode(struct ave_private *priv)
  549. {
  550. u32 reg, mask, val = 0;
  551. if (priv->regmap_arg > 0)
  552. return -EINVAL;
  553. mask = SG_ETPINMODE_RMII(0);
  554. switch (priv->phy_mode) {
  555. case PHY_INTERFACE_MODE_RMII:
  556. val = SG_ETPINMODE_RMII(0);
  557. break;
  558. case PHY_INTERFACE_MODE_RGMII:
  559. break;
  560. default:
  561. return -EINVAL;
  562. }
  563. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  564. reg &= ~mask;
  565. reg |= val;
  566. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  567. return 0;
  568. }
  569. static int ave_pxs3_get_pinmode(struct ave_private *priv)
  570. {
  571. u32 reg, mask, val = 0;
  572. if (priv->regmap_arg > 1)
  573. return -EINVAL;
  574. mask = SG_ETPINMODE_RMII(priv->regmap_arg);
  575. switch (priv->phy_mode) {
  576. case PHY_INTERFACE_MODE_RMII:
  577. val = SG_ETPINMODE_RMII(priv->regmap_arg);
  578. break;
  579. case PHY_INTERFACE_MODE_RGMII:
  580. break;
  581. default:
  582. return -EINVAL;
  583. }
  584. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  585. reg &= ~mask;
  586. reg |= val;
  587. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  588. return 0;
  589. }
  590. static int ave_of_to_plat(struct udevice *dev)
  591. {
  592. struct eth_pdata *pdata = dev_get_plat(dev);
  593. struct ave_private *priv = dev_get_priv(dev);
  594. struct ofnode_phandle_args args;
  595. const char *phy_mode;
  596. const u32 *valp;
  597. int ret, nc, nr;
  598. const char *name;
  599. priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
  600. if (!priv->data)
  601. return -EINVAL;
  602. pdata->iobase = dev_read_addr(dev);
  603. pdata->phy_interface = -1;
  604. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  605. NULL);
  606. if (phy_mode)
  607. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  608. if (pdata->phy_interface == -1) {
  609. dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
  610. return -EINVAL;
  611. }
  612. pdata->max_speed = 0;
  613. valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
  614. NULL);
  615. if (valp)
  616. pdata->max_speed = fdt32_to_cpu(*valp);
  617. for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
  618. name = priv->data->clock_names[nc];
  619. if (!name)
  620. break;
  621. ret = clk_get_by_name(dev, name, &priv->clk[nc]);
  622. if (ret) {
  623. dev_err(dev, "Failed to get clocks property: %d\n",
  624. ret);
  625. goto out_clk_free;
  626. }
  627. priv->nclks++;
  628. }
  629. for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
  630. name = priv->data->reset_names[nr];
  631. if (!name)
  632. break;
  633. ret = reset_get_by_name(dev, name, &priv->rst[nr]);
  634. if (ret) {
  635. dev_err(dev, "Failed to get resets property: %d\n",
  636. ret);
  637. goto out_reset_free;
  638. }
  639. priv->nrsts++;
  640. }
  641. ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
  642. NULL, 1, 0, &args);
  643. if (ret) {
  644. dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
  645. ret);
  646. goto out_reset_free;
  647. }
  648. priv->regmap = syscon_node_to_regmap(args.node);
  649. if (IS_ERR(priv->regmap)) {
  650. ret = PTR_ERR(priv->regmap);
  651. dev_err(dev, "can't get syscon: %d\n", ret);
  652. goto out_reset_free;
  653. }
  654. if (args.args_count != 1) {
  655. ret = -EINVAL;
  656. dev_err(dev, "Invalid argument of syscon-phy-mode\n");
  657. goto out_reset_free;
  658. }
  659. priv->regmap_arg = args.args[0];
  660. return 0;
  661. out_reset_free:
  662. while (--nr >= 0)
  663. reset_free(&priv->rst[nr]);
  664. out_clk_free:
  665. while (--nc >= 0)
  666. clk_free(&priv->clk[nc]);
  667. return ret;
  668. }
  669. static int ave_probe(struct udevice *dev)
  670. {
  671. struct eth_pdata *pdata = dev_get_plat(dev);
  672. struct ave_private *priv = dev_get_priv(dev);
  673. int ret, nc, nr;
  674. priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
  675. if (!priv->data)
  676. return -EINVAL;
  677. priv->iobase = pdata->iobase;
  678. priv->phy_mode = pdata->phy_interface;
  679. priv->max_speed = pdata->max_speed;
  680. ret = priv->data->get_pinmode(priv);
  681. if (ret) {
  682. dev_err(dev, "Invalid phy-mode\n");
  683. return -EINVAL;
  684. }
  685. for (nc = 0; nc < priv->nclks; nc++) {
  686. ret = clk_enable(&priv->clk[nc]);
  687. if (ret) {
  688. dev_err(dev, "Failed to enable clk: %d\n", ret);
  689. goto out_clk_release;
  690. }
  691. }
  692. for (nr = 0; nr < priv->nrsts; nr++) {
  693. ret = reset_deassert(&priv->rst[nr]);
  694. if (ret) {
  695. dev_err(dev, "Failed to deassert reset: %d\n", ret);
  696. goto out_reset_release;
  697. }
  698. }
  699. ave_reset(priv);
  700. ret = ave_mdiobus_init(priv, dev->name);
  701. if (ret) {
  702. dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
  703. goto out_reset_release;
  704. }
  705. priv->bus = miiphy_get_dev_by_name(dev->name);
  706. ret = ave_phy_init(priv, dev);
  707. if (ret) {
  708. dev_err(dev, "Failed to initialize phy: %d\n", ret);
  709. goto out_mdiobus_release;
  710. }
  711. return 0;
  712. out_mdiobus_release:
  713. mdio_unregister(priv->bus);
  714. mdio_free(priv->bus);
  715. out_reset_release:
  716. reset_release_all(priv->rst, nr);
  717. out_clk_release:
  718. clk_release_all(priv->clk, nc);
  719. return ret;
  720. }
  721. static int ave_remove(struct udevice *dev)
  722. {
  723. struct ave_private *priv = dev_get_priv(dev);
  724. free(priv->phydev);
  725. mdio_unregister(priv->bus);
  726. mdio_free(priv->bus);
  727. reset_release_all(priv->rst, priv->nrsts);
  728. clk_release_all(priv->clk, priv->nclks);
  729. return 0;
  730. }
  731. static const struct eth_ops ave_ops = {
  732. .start = ave_start,
  733. .stop = ave_stop,
  734. .send = ave_send,
  735. .recv = ave_recv,
  736. .free_pkt = ave_free_packet,
  737. .write_hwaddr = ave_write_hwaddr,
  738. };
  739. static const struct ave_soc_data ave_pro4_data = {
  740. .is_desc_64bit = false,
  741. .clock_names = {
  742. "gio", "ether", "ether-gb", "ether-phy",
  743. },
  744. .reset_names = {
  745. "gio", "ether",
  746. },
  747. .get_pinmode = ave_pro4_get_pinmode,
  748. };
  749. static const struct ave_soc_data ave_pxs2_data = {
  750. .is_desc_64bit = false,
  751. .clock_names = {
  752. "ether",
  753. },
  754. .reset_names = {
  755. "ether",
  756. },
  757. .get_pinmode = ave_pro4_get_pinmode,
  758. };
  759. static const struct ave_soc_data ave_ld11_data = {
  760. .is_desc_64bit = false,
  761. .clock_names = {
  762. "ether",
  763. },
  764. .reset_names = {
  765. "ether",
  766. },
  767. .get_pinmode = ave_ld11_get_pinmode,
  768. };
  769. static const struct ave_soc_data ave_ld20_data = {
  770. .is_desc_64bit = true,
  771. .clock_names = {
  772. "ether",
  773. },
  774. .reset_names = {
  775. "ether",
  776. },
  777. .get_pinmode = ave_ld20_get_pinmode,
  778. };
  779. static const struct ave_soc_data ave_pxs3_data = {
  780. .is_desc_64bit = false,
  781. .clock_names = {
  782. "ether",
  783. },
  784. .reset_names = {
  785. "ether",
  786. },
  787. .get_pinmode = ave_pxs3_get_pinmode,
  788. };
  789. static const struct udevice_id ave_ids[] = {
  790. {
  791. .compatible = "socionext,uniphier-pro4-ave4",
  792. .data = (ulong)&ave_pro4_data,
  793. },
  794. {
  795. .compatible = "socionext,uniphier-pxs2-ave4",
  796. .data = (ulong)&ave_pxs2_data,
  797. },
  798. {
  799. .compatible = "socionext,uniphier-ld11-ave4",
  800. .data = (ulong)&ave_ld11_data,
  801. },
  802. {
  803. .compatible = "socionext,uniphier-ld20-ave4",
  804. .data = (ulong)&ave_ld20_data,
  805. },
  806. {
  807. .compatible = "socionext,uniphier-pxs3-ave4",
  808. .data = (ulong)&ave_pxs3_data,
  809. },
  810. { /* Sentinel */ }
  811. };
  812. U_BOOT_DRIVER(ave) = {
  813. .name = "ave",
  814. .id = UCLASS_ETH,
  815. .of_match = ave_ids,
  816. .probe = ave_probe,
  817. .remove = ave_remove,
  818. .of_to_plat = ave_of_to_plat,
  819. .ops = &ave_ops,
  820. .priv_auto = sizeof(struct ave_private),
  821. .plat_auto = sizeof(struct eth_pdata),
  822. };