smc91111.h 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*------------------------------------------------------------------------
  3. . smc91111.h - macros for the LAN91C111 Ethernet Driver
  4. .
  5. . (C) Copyright 2002
  6. . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. . Rolf Offermanns <rof@sysgo.de>
  8. . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  9. . Developed by Simple Network Magic Corporation (SNMC)
  10. . Copyright (C) 1996 by Erik Stahlman (ES)
  11. .
  12. . This file contains register information and access macros for
  13. . the LAN91C111 single chip ethernet controller. It is a modified
  14. . version of the smc9194.h file.
  15. .
  16. . Information contained in this file was obtained from the LAN91C111
  17. . manual from SMC. To get a copy, if you really want one, you can find
  18. . information under www.smsc.com.
  19. .
  20. . Authors
  21. . Erik Stahlman ( erik@vt.edu )
  22. . Daris A Nevil ( dnevil@snmc.com )
  23. .
  24. . History
  25. . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
  26. .
  27. ---------------------------------------------------------------------------*/
  28. #ifndef _SMC91111_H_
  29. #define _SMC91111_H_
  30. #include <asm/types.h>
  31. #include <config.h>
  32. #include <net.h>
  33. /*
  34. * This function may be called by the board specific initialisation code
  35. * in order to override the default mac address.
  36. */
  37. void smc_set_mac_addr (const unsigned char *addr);
  38. /* I want some simple types */
  39. typedef unsigned char byte;
  40. typedef unsigned short word;
  41. typedef unsigned long int dword;
  42. struct smc91111_priv{
  43. u8 dev_num;
  44. };
  45. /*
  46. . DEBUGGING LEVELS
  47. .
  48. . 0 for normal operation
  49. . 1 for slightly more details
  50. . >2 for various levels of increasingly useless information
  51. . 2 for interrupt tracking, status flags
  52. . 3 for packet info
  53. . 4 for complete packet dumps
  54. */
  55. /*#define SMC_DEBUG 0 */
  56. /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
  57. #define SMC_IO_EXTENT 16
  58. #ifdef CONFIG_CPU_PXA25X
  59. #ifdef CONFIG_XSENGINE
  60. #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
  61. #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
  62. #define SMC_inb(a,p) ({ \
  63. unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
  64. unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
  65. if (__p & 2) __v >>= 8; \
  66. else __v &= 0xff; \
  67. __v; })
  68. #else
  69. #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
  70. #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
  71. #define SMC_inb(a,p) ({ \
  72. unsigned int __p = (unsigned int)((a)->iobase + (p)); \
  73. unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
  74. if (__p & 1) __v >>= 8; \
  75. else __v &= 0xff; \
  76. __v; })
  77. #endif
  78. #ifdef CONFIG_XSENGINE
  79. #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
  80. #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
  81. #else
  82. #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
  83. #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
  84. #endif
  85. #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
  86. word __w = SMC_inw((a),(r)&~1); \
  87. __w &= ((r)&1) ? 0x00FF : 0xFF00; \
  88. __w |= ((r)&1) ? __d<<8 : __d; \
  89. SMC_outw((a),__w,(r)&~1); \
  90. })
  91. #define SMC_outsl(a,r,b,l) ({ int __i; \
  92. dword *__b2; \
  93. __b2 = (dword *) b; \
  94. for (__i = 0; __i < l; __i++) { \
  95. SMC_outl((a), *(__b2 + __i), r); \
  96. } \
  97. })
  98. #define SMC_outsw(a,r,b,l) ({ int __i; \
  99. word *__b2; \
  100. __b2 = (word *) b; \
  101. for (__i = 0; __i < l; __i++) { \
  102. SMC_outw((a), *(__b2 + __i), r); \
  103. } \
  104. })
  105. #define SMC_insl(a,r,b,l) ({ int __i ; \
  106. dword *__b2; \
  107. __b2 = (dword *) b; \
  108. for (__i = 0; __i < l; __i++) { \
  109. *(__b2 + __i) = SMC_inl((a),(r)); \
  110. SMC_inl((a),0); \
  111. }; \
  112. })
  113. #define SMC_insw(a,r,b,l) ({ int __i ; \
  114. word *__b2; \
  115. __b2 = (word *) b; \
  116. for (__i = 0; __i < l; __i++) { \
  117. *(__b2 + __i) = SMC_inw((a),(r)); \
  118. SMC_inw((a),0); \
  119. }; \
  120. })
  121. #define SMC_insb(a,r,b,l) ({ int __i ; \
  122. byte *__b2; \
  123. __b2 = (byte *) b; \
  124. for (__i = 0; __i < l; __i++) { \
  125. *(__b2 + __i) = SMC_inb((a),(r)); \
  126. SMC_inb((a),0); \
  127. }; \
  128. })
  129. #elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */
  130. #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
  131. #define SMC_LEON_SWAP32(_x_) \
  132. ({ dword _x = (_x_); \
  133. ((_x << 24) | \
  134. ((0x0000FF00UL & _x) << 8) | \
  135. ((0x00FF0000UL & _x) >> 8) | \
  136. (_x >> 24)); })
  137. #define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
  138. #define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0))))
  139. #define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
  140. #define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0))))
  141. #define SMC_inb(a,p) ({ \
  142. word ___v = SMC_inw((a),(p) & ~1); \
  143. if ((p) & 1) ___v >>= 8; \
  144. else ___v &= 0xff; \
  145. ___v; })
  146. #define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
  147. #define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d))
  148. #define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
  149. #define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d))
  150. #define SMC_outb(a,d,r) do{ word __d = (byte)(d); \
  151. word __w = SMC_inw((a),(r)&~1); \
  152. __w &= ((r)&1) ? 0x00FF : 0xFF00; \
  153. __w |= ((r)&1) ? __d<<8 : __d; \
  154. SMC_outw((a),__w,(r)&~1); \
  155. }while(0)
  156. #define SMC_outsl(a,r,b,l) do{ int __i; \
  157. dword *__b2; \
  158. __b2 = (dword *) b; \
  159. for (__i = 0; __i < l; __i++) { \
  160. SMC_outl_nosw((a), *(__b2 + __i), r); \
  161. } \
  162. }while(0)
  163. #define SMC_outsw(a,r,b,l) do{ int __i; \
  164. word *__b2; \
  165. __b2 = (word *) b; \
  166. for (__i = 0; __i < l; __i++) { \
  167. SMC_outw_nosw((a), *(__b2 + __i), r); \
  168. } \
  169. }while(0)
  170. #define SMC_insl(a,r,b,l) do{ int __i ; \
  171. dword *__b2; \
  172. __b2 = (dword *) b; \
  173. for (__i = 0; __i < l; __i++) { \
  174. *(__b2 + __i) = SMC_inl_nosw((a),(r)); \
  175. }; \
  176. }while(0)
  177. #define SMC_insw(a,r,b,l) do{ int __i ; \
  178. word *__b2; \
  179. __b2 = (word *) b; \
  180. for (__i = 0; __i < l; __i++) { \
  181. *(__b2 + __i) = SMC_inw_nosw((a),(r)); \
  182. }; \
  183. }while(0)
  184. #define SMC_insb(a,r,b,l) do{ int __i ; \
  185. byte *__b2; \
  186. __b2 = (byte *) b; \
  187. for (__i = 0; __i < l; __i++) { \
  188. *(__b2 + __i) = SMC_inb((a),(r)); \
  189. }; \
  190. }while(0)
  191. #elif defined(CONFIG_MS7206SE)
  192. #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
  193. #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
  194. #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
  195. #define SMC_insw(a, r, b, l) \
  196. do { \
  197. int __i; \
  198. word *__b2 = (word *)(b); \
  199. for (__i = 0; __i < (l); __i++) { \
  200. *__b2++ = SWAB7206(SMC_inw(a, r)); \
  201. } \
  202. } while (0)
  203. #define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d)
  204. #define SMC_outb(a, d, r) ({ word __d = (byte)(d); \
  205. word __w = SMC_inw((a), ((r)&(~1))); \
  206. if (((r) & 1)) \
  207. __w = (__w & 0x00ff) | (__d << 8); \
  208. else \
  209. __w = (__w & 0xff00) | (__d); \
  210. SMC_outw((a), __w, ((r)&(~1))); \
  211. })
  212. #define SMC_outsw(a, r, b, l) \
  213. do { \
  214. int __i; \
  215. word *__b2 = (word *)(b); \
  216. for (__i = 0; __i < (l); __i++) { \
  217. SMC_outw(a, SWAB7206(*__b2), r); \
  218. __b2++; \
  219. } \
  220. } while (0)
  221. #else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
  222. #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
  223. /*
  224. * We have only 16 Bit PCMCIA access on Socket 0
  225. */
  226. #ifdef CONFIG_ADNPESC1
  227. #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
  228. #elif CONFIG_ARM64
  229. #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
  230. #else
  231. #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
  232. #endif
  233. #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
  234. #ifdef CONFIG_ADNPESC1
  235. #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
  236. #elif CONFIG_ARM64
  237. #define SMC_outw(a, d, r) \
  238. (*((volatile word*)((a)->iobase+((dword)(r)))) = d)
  239. #else
  240. #define SMC_outw(a, d, r) \
  241. (*((volatile word*)((a)->iobase+(r))) = d)
  242. #endif
  243. #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
  244. word __w = SMC_inw((a),(r)&~1); \
  245. __w &= ((r)&1) ? 0x00FF : 0xFF00; \
  246. __w |= ((r)&1) ? __d<<8 : __d; \
  247. SMC_outw((a),__w,(r)&~1); \
  248. })
  249. #if 0
  250. #define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
  251. #else
  252. #define SMC_outsw(a,r,b,l) ({ int __i; \
  253. word *__b2; \
  254. __b2 = (word *) b; \
  255. for (__i = 0; __i < l; __i++) { \
  256. SMC_outw((a), *(__b2 + __i), r); \
  257. } \
  258. })
  259. #endif
  260. #if 0
  261. #define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
  262. #else
  263. #define SMC_insw(a,r,b,l) ({ int __i ; \
  264. word *__b2; \
  265. __b2 = (word *) b; \
  266. for (__i = 0; __i < l; __i++) { \
  267. *(__b2 + __i) = SMC_inw((a),(r)); \
  268. SMC_inw((a),0); \
  269. }; \
  270. })
  271. #endif
  272. #endif /* CONFIG_SMC_USE_IOFUNCS */
  273. #if defined(CONFIG_SMC_USE_32_BIT)
  274. #ifdef CONFIG_XSENGINE
  275. #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
  276. #else
  277. #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
  278. #endif
  279. #define SMC_insl(a,r,b,l) ({ int __i ; \
  280. dword *__b2; \
  281. __b2 = (dword *) b; \
  282. for (__i = 0; __i < l; __i++) { \
  283. *(__b2 + __i) = SMC_inl((a),(r)); \
  284. SMC_inl((a),0); \
  285. }; \
  286. })
  287. #ifdef CONFIG_XSENGINE
  288. #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
  289. #else
  290. #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
  291. #endif
  292. #define SMC_outsl(a,r,b,l) ({ int __i; \
  293. dword *__b2; \
  294. __b2 = (dword *) b; \
  295. for (__i = 0; __i < l; __i++) { \
  296. SMC_outl((a), *(__b2 + __i), r); \
  297. } \
  298. })
  299. #endif /* CONFIG_SMC_USE_32_BIT */
  300. #endif
  301. /*---------------------------------------------------------------
  302. .
  303. . A description of the SMSC registers is probably in order here,
  304. . although for details, the SMC datasheet is invaluable.
  305. .
  306. . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
  307. . are accessed by writing a number into the BANK_SELECT register
  308. . ( I also use a SMC_SELECT_BANK macro for this ).
  309. .
  310. . The banks are configured so that for most purposes, bank 2 is all
  311. . that is needed for simple run time tasks.
  312. -----------------------------------------------------------------------*/
  313. /*
  314. . Bank Select Register:
  315. .
  316. . yyyy yyyy 0000 00xx
  317. . xx = bank number
  318. . yyyy yyyy = 0x33, for identification purposes.
  319. */
  320. #define BANK_SELECT 14
  321. /* Transmit Control Register */
  322. /* BANK 0 */
  323. #define TCR_REG 0x0000 /* transmit control register */
  324. #define TCR_ENABLE 0x0001 /* When 1 we can transmit */
  325. #define TCR_LOOP 0x0002 /* Controls output pin LBK */
  326. #define TCR_FORCOL 0x0004 /* When 1 will force a collision */
  327. #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
  328. #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
  329. #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
  330. #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
  331. #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
  332. #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
  333. #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
  334. #define TCR_CLEAR 0 /* do NOTHING */
  335. /* the default settings for the TCR register : */
  336. /* QUESTION: do I want to enable padding of short packets ? */
  337. #define TCR_DEFAULT TCR_ENABLE
  338. /* EPH Status Register */
  339. /* BANK 0 */
  340. #define EPH_STATUS_REG 0x0002
  341. #define ES_TX_SUC 0x0001 /* Last TX was successful */
  342. #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
  343. #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
  344. #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
  345. #define ES_16COL 0x0010 /* 16 Collisions Reached */
  346. #define ES_SQET 0x0020 /* Signal Quality Error Test */
  347. #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
  348. #define ES_TXDEFR 0x0080 /* Transmit Deferred */
  349. #define ES_LATCOL 0x0200 /* Late collision detected on last tx */
  350. #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
  351. #define ES_EXC_DEF 0x0800 /* Excessive Deferral */
  352. #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
  353. #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
  354. #define ES_TXUNRN 0x8000 /* Tx Underrun */
  355. /* Receive Control Register */
  356. /* BANK 0 */
  357. #define RCR_REG 0x0004
  358. #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
  359. #define RCR_PRMS 0x0002 /* Enable promiscuous mode */
  360. #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
  361. #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
  362. #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
  363. #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
  364. #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
  365. #define RCR_SOFTRST 0x8000 /* resets the chip */
  366. /* the normal settings for the RCR register : */
  367. #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
  368. #define RCR_CLEAR 0x0 /* set it to a base state */
  369. /* Counter Register */
  370. /* BANK 0 */
  371. #define COUNTER_REG 0x0006
  372. /* Memory Information Register */
  373. /* BANK 0 */
  374. #define MIR_REG 0x0008
  375. /* Receive/Phy Control Register */
  376. /* BANK 0 */
  377. #define RPC_REG 0x000A
  378. #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
  379. #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
  380. #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
  381. #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
  382. #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
  383. #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
  384. #define RPC_LED_RES (0x01) /* LED = Reserved */
  385. #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
  386. #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
  387. #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
  388. #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
  389. #define RPC_LED_TX (0x06) /* LED = TX packet occurred */
  390. #define RPC_LED_RX (0x07) /* LED = RX packet occurred */
  391. #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
  392. /* buggy schematic: LEDa -> yellow, LEDb --> green */
  393. #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
  394. | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
  395. | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
  396. #elif defined(CONFIG_ADNPESC1)
  397. /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
  398. #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
  399. | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
  400. | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
  401. #else
  402. /* SMSC reference design: LEDa --> green, LEDb --> yellow */
  403. #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
  404. | (RPC_LED_100_10 << RPC_LSXA_SHFT) \
  405. | (RPC_LED_TX_RX << RPC_LSXB_SHFT) )
  406. #endif
  407. /* Bank 0 0x000C is reserved */
  408. /* Bank Select Register */
  409. /* All Banks */
  410. #define BSR_REG 0x000E
  411. /* Configuration Reg */
  412. /* BANK 1 */
  413. #define CONFIG_REG 0x0000
  414. #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
  415. #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
  416. #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
  417. #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
  418. /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
  419. #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
  420. /* Base Address Register */
  421. /* BANK 1 */
  422. #define BASE_REG 0x0002
  423. /* Individual Address Registers */
  424. /* BANK 1 */
  425. #define ADDR0_REG 0x0004
  426. #define ADDR1_REG 0x0006
  427. #define ADDR2_REG 0x0008
  428. /* General Purpose Register */
  429. /* BANK 1 */
  430. #define GP_REG 0x000A
  431. /* Control Register */
  432. /* BANK 1 */
  433. #define CTL_REG 0x000C
  434. #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
  435. #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
  436. #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
  437. #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
  438. #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
  439. #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
  440. #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
  441. #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
  442. #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/
  443. /* MMU Command Register */
  444. /* BANK 2 */
  445. #define MMU_CMD_REG 0x0000
  446. #define MC_BUSY 1 /* When 1 the last release has not completed */
  447. #define MC_NOP (0<<5) /* No Op */
  448. #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
  449. #define MC_RESET (2<<5) /* Reset MMU to initial state */
  450. #define MC_REMOVE (3<<5) /* Remove the current rx packet */
  451. #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
  452. #define MC_FREEPKT (5<<5) /* Release packet in PNR register */
  453. #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
  454. #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
  455. /* Packet Number Register */
  456. /* BANK 2 */
  457. #define PN_REG 0x0002
  458. /* Allocation Result Register */
  459. /* BANK 2 */
  460. #define AR_REG 0x0003
  461. #define AR_FAILED 0x80 /* Alocation Failed */
  462. /* RX FIFO Ports Register */
  463. /* BANK 2 */
  464. #define RXFIFO_REG 0x0004 /* Must be read as a word */
  465. #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
  466. /* TX FIFO Ports Register */
  467. /* BANK 2 */
  468. #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
  469. #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
  470. /* Pointer Register */
  471. /* BANK 2 */
  472. #define PTR_REG 0x0006
  473. #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
  474. #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
  475. #define PTR_READ 0x2000 /* When 1 the operation is a read */
  476. #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
  477. /* Data Register */
  478. /* BANK 2 */
  479. #define SMC91111_DATA_REG 0x0008
  480. /* Interrupt Status/Acknowledge Register */
  481. /* BANK 2 */
  482. #define SMC91111_INT_REG 0x000C
  483. /* Interrupt Mask Register */
  484. /* BANK 2 */
  485. #define IM_REG 0x000D
  486. #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
  487. #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
  488. #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
  489. #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
  490. #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
  491. #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
  492. #define IM_TX_INT 0x02 /* Transmit Interrrupt */
  493. #define IM_RCV_INT 0x01 /* Receive Interrupt */
  494. /* Multicast Table Registers */
  495. /* BANK 3 */
  496. #define MCAST_REG1 0x0000
  497. #define MCAST_REG2 0x0002
  498. #define MCAST_REG3 0x0004
  499. #define MCAST_REG4 0x0006
  500. /* Management Interface Register (MII) */
  501. /* BANK 3 */
  502. #define MII_REG 0x0008
  503. #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
  504. #define MII_MDOE 0x0008 /* MII Output Enable */
  505. #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
  506. #define MII_MDI 0x0002 /* MII Input, pin MDI */
  507. #define MII_MDO 0x0001 /* MII Output, pin MDO */
  508. /* Revision Register */
  509. /* BANK 3 */
  510. #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
  511. /* Early RCV Register */
  512. /* BANK 3 */
  513. /* this is NOT on SMC9192 */
  514. #define ERCV_REG 0x000C
  515. #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
  516. #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
  517. /* External Register */
  518. /* BANK 7 */
  519. #define EXT_REG 0x0000
  520. #define CHIP_9192 3
  521. #define CHIP_9194 4
  522. #define CHIP_9195 5
  523. #define CHIP_9196 6
  524. #define CHIP_91100 7
  525. #define CHIP_91100FD 8
  526. #define CHIP_91111FD 9
  527. #if 0
  528. static const char * chip_ids[ 15 ] = {
  529. NULL, NULL, NULL,
  530. /* 3 */ "SMC91C90/91C92",
  531. /* 4 */ "SMC91C94",
  532. /* 5 */ "SMC91C95",
  533. /* 6 */ "SMC91C96",
  534. /* 7 */ "SMC91C100",
  535. /* 8 */ "SMC91C100FD",
  536. /* 9 */ "SMC91C111",
  537. NULL, NULL,
  538. NULL, NULL, NULL};
  539. #endif
  540. /*
  541. . Transmit status bits
  542. */
  543. #define TS_SUCCESS 0x0001
  544. #define TS_LOSTCAR 0x0400
  545. #define TS_LATCOL 0x0200
  546. #define TS_16COL 0x0010
  547. /*
  548. . Receive status bits
  549. */
  550. #define RS_ALGNERR 0x8000
  551. #define RS_BRODCAST 0x4000
  552. #define RS_BADCRC 0x2000
  553. #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
  554. #define RS_TOOLONG 0x0800
  555. #define RS_TOOSHORT 0x0400
  556. #define RS_MULTICAST 0x0001
  557. #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
  558. /* PHY Types */
  559. enum {
  560. PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
  561. PHY_LAN83C180
  562. };
  563. /* PHY Register Addresses (LAN91C111 Internal PHY) */
  564. /* PHY Control Register */
  565. #define PHY_CNTL_REG 0x00
  566. #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
  567. #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
  568. #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
  569. #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
  570. #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
  571. #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
  572. #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
  573. #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
  574. #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
  575. /* PHY Status Register */
  576. #define PHY_STAT_REG 0x01
  577. #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
  578. #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
  579. #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
  580. #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
  581. #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
  582. #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
  583. #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
  584. #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
  585. #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
  586. #define PHY_STAT_LINK 0x0004 /* 1=valid link */
  587. #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
  588. #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
  589. /* PHY Identifier Registers */
  590. #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
  591. #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
  592. /* PHY Auto-Negotiation Advertisement Register */
  593. #define PHY_AD_REG 0x04
  594. #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
  595. #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
  596. #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
  597. #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
  598. #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
  599. #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
  600. #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
  601. #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
  602. #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
  603. /* PHY Auto-negotiation Remote End Capability Register */
  604. #define PHY_RMT_REG 0x05
  605. /* Uses same bit definitions as PHY_AD_REG */
  606. /* PHY Configuration Register 1 */
  607. #define PHY_CFG1_REG 0x10
  608. #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
  609. #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
  610. #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
  611. #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
  612. #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
  613. #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
  614. #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
  615. #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
  616. #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
  617. #define PHY_CFG1_TLVL_MASK 0x003C
  618. #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
  619. /* PHY Configuration Register 2 */
  620. #define PHY_CFG2_REG 0x11
  621. #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
  622. #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
  623. #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
  624. #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
  625. /* PHY Status Output (and Interrupt status) Register */
  626. #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
  627. #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
  628. #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
  629. #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
  630. #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
  631. #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
  632. #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
  633. #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
  634. #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
  635. #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
  636. #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
  637. /* PHY Interrupt/Status Mask Register */
  638. #define PHY_MASK_REG 0x13 /* Interrupt Mask */
  639. /* Uses the same bit definitions as PHY_INT_REG */
  640. /*-------------------------------------------------------------------------
  641. . I define some macros to make it easier to do somewhat common
  642. . or slightly complicated, repeated tasks.
  643. --------------------------------------------------------------------------*/
  644. /* select a register bank, 0 to 3 */
  645. #define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
  646. /* this enables an interrupt in the interrupt mask register */
  647. #define SMC_ENABLE_INT(a,x) {\
  648. unsigned char mask;\
  649. SMC_SELECT_BANK((a),2);\
  650. mask = SMC_inb((a), IM_REG );\
  651. mask |= (x);\
  652. SMC_outb( (a), mask, IM_REG ); \
  653. }
  654. /* this disables an interrupt from the interrupt mask register */
  655. #define SMC_DISABLE_INT(a,x) {\
  656. unsigned char mask;\
  657. SMC_SELECT_BANK(2);\
  658. mask = SMC_inb( (a), IM_REG );\
  659. mask &= ~(x);\
  660. SMC_outb( (a), mask, IM_REG ); \
  661. }
  662. /*----------------------------------------------------------------------
  663. . Define the interrupts that I want to receive from the card
  664. .
  665. . I want:
  666. . IM_EPH_INT, for nasty errors
  667. . IM_RCV_INT, for happy received packets
  668. . IM_RX_OVRN_INT, because I have to kick the receiver
  669. . IM_MDINT, for PHY Register 18 Status Changes
  670. --------------------------------------------------------------------------*/
  671. #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
  672. IM_MDINT)
  673. #endif /* _SMC_91111_H_ */