smc91111.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*------------------------------------------------------------------------
  3. . smc91111.c
  4. . This is a driver for SMSC's 91C111 single-chip Ethernet device.
  5. .
  6. . (C) Copyright 2002
  7. . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. . Rolf Offermanns <rof@sysgo.de>
  9. .
  10. . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  11. . Developed by Simple Network Magic Corporation (SNMC)
  12. . Copyright (C) 1996 by Erik Stahlman (ES)
  13. .
  14. .
  15. . Information contained in this file was obtained from the LAN91C111
  16. . manual from SMC. To get a copy, if you really want one, you can find
  17. . information under www.smsc.com.
  18. .
  19. .
  20. . "Features" of the SMC chip:
  21. . Integrated PHY/MAC for 10/100BaseT Operation
  22. . Supports internal and external MII
  23. . Integrated 8K packet memory
  24. . EEPROM interface for configuration
  25. .
  26. . Arguments:
  27. . io = for the base address
  28. . irq = for the IRQ
  29. .
  30. . author:
  31. . Erik Stahlman ( erik@vt.edu )
  32. . Daris A Nevil ( dnevil@snmc.com )
  33. .
  34. .
  35. . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
  36. .
  37. . Sources:
  38. . o SMSC LAN91C111 databook (www.smsc.com)
  39. . o smc9194.c by Erik Stahlman
  40. . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
  41. .
  42. . History:
  43. . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
  44. . 10/17/01 Marco Hasewinkel Modify for DNP/1110
  45. . 07/25/01 Woojung Huh Modify for ADS Bitsy
  46. . 04/25/01 Daris A Nevil Initial public release through SMSC
  47. . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
  48. ----------------------------------------------------------------------------*/
  49. #include <common.h>
  50. #include <command.h>
  51. #include <config.h>
  52. #include <malloc.h>
  53. #include <linux/delay.h>
  54. #include "smc91111.h"
  55. #include <net.h>
  56. /* Use power-down feature of the chip */
  57. #define POWER_DOWN 0
  58. #define NO_AUTOPROBE
  59. #define SMC_DEBUG 0
  60. #if SMC_DEBUG > 1
  61. static const char version[] =
  62. "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
  63. #endif
  64. /* Autonegotiation timeout in seconds */
  65. #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
  66. #define CONFIG_SMC_AUTONEG_TIMEOUT 10
  67. #endif
  68. /*------------------------------------------------------------------------
  69. .
  70. . Configuration options, for the experienced user to change.
  71. .
  72. -------------------------------------------------------------------------*/
  73. /*
  74. . Wait time for memory to be free. This probably shouldn't be
  75. . tuned that much, as waiting for this means nothing else happens
  76. . in the system
  77. */
  78. #define MEMORY_WAIT_TIME 16
  79. #if (SMC_DEBUG > 2 )
  80. #define PRINTK3(args...) printf(args)
  81. #else
  82. #define PRINTK3(args...)
  83. #endif
  84. #if SMC_DEBUG > 1
  85. #define PRINTK2(args...) printf(args)
  86. #else
  87. #define PRINTK2(args...)
  88. #endif
  89. #ifdef SMC_DEBUG
  90. #define PRINTK(args...) printf(args)
  91. #else
  92. #define PRINTK(args...)
  93. #endif
  94. /*------------------------------------------------------------------------
  95. .
  96. . The internal workings of the driver. If you are changing anything
  97. . here with the SMC stuff, you should have the datasheet and know
  98. . what you are doing.
  99. .
  100. -------------------------------------------------------------------------*/
  101. /* Memory sizing constant */
  102. #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
  103. #ifndef CONFIG_SMC91111_BASE
  104. #error "SMC91111 Base address must be passed to initialization funciton"
  105. /* #define CONFIG_SMC91111_BASE 0x20000300 */
  106. #endif
  107. #define SMC_DEV_NAME "SMC91111"
  108. #define SMC_PHY_ADDR 0x0000
  109. #define SMC_ALLOC_MAX_TRY 5
  110. #define SMC_TX_TIMEOUT 30
  111. #define SMC_PHY_CLOCK_DELAY 1000
  112. #define ETH_ZLEN 60
  113. #ifdef CONFIG_SMC_USE_32_BIT
  114. #define USE_32_BIT 1
  115. #else
  116. #undef USE_32_BIT
  117. #endif
  118. #ifdef SHARED_RESOURCES
  119. extern void swap_to(int device_id);
  120. #else
  121. # define swap_to(x)
  122. #endif
  123. #ifndef CONFIG_SMC91111_EXT_PHY
  124. static void smc_phy_configure(struct eth_device *dev);
  125. #endif /* !CONFIG_SMC91111_EXT_PHY */
  126. /*
  127. ------------------------------------------------------------
  128. .
  129. . Internal routines
  130. .
  131. ------------------------------------------------------------
  132. */
  133. #ifdef CONFIG_SMC_USE_IOFUNCS
  134. /*
  135. * input and output functions
  136. *
  137. * Implemented due to inx,outx macros accessing the device improperly
  138. * and putting the device into an unkown state.
  139. *
  140. * For instance, on Sharp LPD7A400 SDK, affects were chip memory
  141. * could not be free'd (hence the alloc failures), duplicate packets,
  142. * packets being corrupt (shifted) on the wire, etc. Switching to the
  143. * inx,outx functions fixed this problem.
  144. */
  145. static inline word SMC_inw(struct eth_device *dev, dword offset)
  146. {
  147. word v;
  148. v = *((volatile word*)(dev->iobase + offset));
  149. barrier(); *(volatile u32*)(0xc0000000);
  150. return v;
  151. }
  152. static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
  153. {
  154. *((volatile word*)(dev->iobase + offset)) = value;
  155. barrier(); *(volatile u32*)(0xc0000000);
  156. }
  157. static inline byte SMC_inb(struct eth_device *dev, dword offset)
  158. {
  159. word _w;
  160. _w = SMC_inw(dev, offset & ~((dword)1));
  161. return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
  162. }
  163. static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
  164. {
  165. word _w;
  166. _w = SMC_inw(dev, offset & ~((dword)1));
  167. if (offset & 1)
  168. *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
  169. (value<<8) | (_w & 0x00ff);
  170. else
  171. *((volatile word*)(dev->iobase + offset)) =
  172. value | (_w & 0xff00);
  173. }
  174. static inline void SMC_insw(struct eth_device *dev, dword offset,
  175. volatile uchar* buf, dword len)
  176. {
  177. volatile word *p = (volatile word *)buf;
  178. while (len-- > 0) {
  179. *p++ = SMC_inw(dev, offset);
  180. barrier();
  181. *((volatile u32*)(0xc0000000));
  182. }
  183. }
  184. static inline void SMC_outsw(struct eth_device *dev, dword offset,
  185. uchar* buf, dword len)
  186. {
  187. volatile word *p = (volatile word *)buf;
  188. while (len-- > 0) {
  189. SMC_outw(dev, *p++, offset);
  190. barrier();
  191. *(volatile u32*)(0xc0000000);
  192. }
  193. }
  194. #endif /* CONFIG_SMC_USE_IOFUNCS */
  195. /*
  196. . A rather simple routine to print out a packet for debugging purposes.
  197. */
  198. #if SMC_DEBUG > 2
  199. static void print_packet( byte *, int );
  200. #endif
  201. #define tx_done(dev) 1
  202. static int poll4int (struct eth_device *dev, byte mask, int timeout)
  203. {
  204. int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
  205. int is_timeout = 0;
  206. word old_bank = SMC_inw (dev, BSR_REG);
  207. PRINTK2 ("Polling...\n");
  208. SMC_SELECT_BANK (dev, 2);
  209. while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
  210. if (get_timer (0) >= tmo) {
  211. is_timeout = 1;
  212. break;
  213. }
  214. }
  215. /* restore old bank selection */
  216. SMC_SELECT_BANK (dev, old_bank);
  217. if (is_timeout)
  218. return 1;
  219. else
  220. return 0;
  221. }
  222. /* Only one release command at a time, please */
  223. static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
  224. {
  225. int count = 0;
  226. /* assume bank 2 selected */
  227. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  228. udelay(1); /* Wait until not busy */
  229. if (++count > 200)
  230. break;
  231. }
  232. }
  233. /*
  234. . Function: smc_reset( void )
  235. . Purpose:
  236. . This sets the SMC91111 chip to its normal state, hopefully from whatever
  237. . mess that any other DOS driver has put it in.
  238. .
  239. . Maybe I should reset more registers to defaults in here? SOFTRST should
  240. . do that for me.
  241. .
  242. . Method:
  243. . 1. send a SOFT RESET
  244. . 2. wait for it to finish
  245. . 3. enable autorelease mode
  246. . 4. reset the memory management unit
  247. . 5. clear all interrupts
  248. .
  249. */
  250. static void smc_reset (struct eth_device *dev)
  251. {
  252. PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
  253. /* This resets the registers mostly to defaults, but doesn't
  254. affect EEPROM. That seems unnecessary */
  255. SMC_SELECT_BANK (dev, 0);
  256. SMC_outw (dev, RCR_SOFTRST, RCR_REG);
  257. /* Setup the Configuration Register */
  258. /* This is necessary because the CONFIG_REG is not affected */
  259. /* by a soft reset */
  260. SMC_SELECT_BANK (dev, 1);
  261. #if defined(CONFIG_SMC91111_EXT_PHY)
  262. SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
  263. #else
  264. SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
  265. #endif
  266. /* Release from possible power-down state */
  267. /* Configuration register is not affected by Soft Reset */
  268. SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
  269. CONFIG_REG);
  270. SMC_SELECT_BANK (dev, 0);
  271. /* this should pause enough for the chip to be happy */
  272. udelay(10);
  273. /* Disable transmit and receive functionality */
  274. SMC_outw (dev, RCR_CLEAR, RCR_REG);
  275. SMC_outw (dev, TCR_CLEAR, TCR_REG);
  276. /* set the control register */
  277. SMC_SELECT_BANK (dev, 1);
  278. SMC_outw (dev, CTL_DEFAULT, CTL_REG);
  279. /* Reset the MMU */
  280. SMC_SELECT_BANK (dev, 2);
  281. smc_wait_mmu_release_complete (dev);
  282. SMC_outw (dev, MC_RESET, MMU_CMD_REG);
  283. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
  284. udelay(1); /* Wait until not busy */
  285. /* Note: It doesn't seem that waiting for the MMU busy is needed here,
  286. but this is a place where future chipsets _COULD_ break. Be wary
  287. of issuing another MMU command right after this */
  288. /* Disable all interrupts */
  289. SMC_outb (dev, 0, IM_REG);
  290. }
  291. /*
  292. . Function: smc_enable
  293. . Purpose: let the chip talk to the outside work
  294. . Method:
  295. . 1. Enable the transmitter
  296. . 2. Enable the receiver
  297. . 3. Enable interrupts
  298. */
  299. static void smc_enable(struct eth_device *dev)
  300. {
  301. PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
  302. SMC_SELECT_BANK( dev, 0 );
  303. /* see the header file for options in TCR/RCR DEFAULT*/
  304. SMC_outw( dev, TCR_DEFAULT, TCR_REG );
  305. SMC_outw( dev, RCR_DEFAULT, RCR_REG );
  306. /* clear MII_DIS */
  307. /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
  308. }
  309. /*
  310. . Function: smc_halt
  311. . Purpose: closes down the SMC91xxx chip.
  312. . Method:
  313. . 1. zero the interrupt mask
  314. . 2. clear the enable receive flag
  315. . 3. clear the enable xmit flags
  316. .
  317. . TODO:
  318. . (1) maybe utilize power down mode.
  319. . Why not yet? Because while the chip will go into power down mode,
  320. . the manual says that it will wake up in response to any I/O requests
  321. . in the register space. Empirical results do not show this working.
  322. */
  323. static void smc_halt(struct eth_device *dev)
  324. {
  325. PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
  326. /* no more interrupts for me */
  327. SMC_SELECT_BANK( dev, 2 );
  328. SMC_outb( dev, 0, IM_REG );
  329. /* and tell the card to stay away from that nasty outside world */
  330. SMC_SELECT_BANK( dev, 0 );
  331. SMC_outb( dev, RCR_CLEAR, RCR_REG );
  332. SMC_outb( dev, TCR_CLEAR, TCR_REG );
  333. swap_to(FLASH);
  334. }
  335. /*
  336. . Function: smc_send(struct net_device * )
  337. . Purpose:
  338. . This sends the actual packet to the SMC9xxx chip.
  339. .
  340. . Algorithm:
  341. . First, see if a saved_skb is available.
  342. . ( this should NOT be called if there is no 'saved_skb'
  343. . Now, find the packet number that the chip allocated
  344. . Point the data pointers at it in memory
  345. . Set the length word in the chip's memory
  346. . Dump the packet to chip memory
  347. . Check if a last byte is needed ( odd length packet )
  348. . if so, set the control flag right
  349. . Tell the card to send it
  350. . Enable the transmit interrupt, so I know if it failed
  351. . Free the kernel data if I actually sent it.
  352. */
  353. static int smc_send(struct eth_device *dev, void *packet, int packet_length)
  354. {
  355. byte packet_no;
  356. byte *buf;
  357. int length;
  358. int numPages;
  359. int try = 0;
  360. int time_out;
  361. byte status;
  362. byte saved_pnr;
  363. word saved_ptr;
  364. /* save PTR and PNR registers before manipulation */
  365. SMC_SELECT_BANK (dev, 2);
  366. saved_pnr = SMC_inb( dev, PN_REG );
  367. saved_ptr = SMC_inw( dev, PTR_REG );
  368. PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
  369. length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
  370. /* allocate memory
  371. ** The MMU wants the number of pages to be the number of 256 bytes
  372. ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
  373. **
  374. ** The 91C111 ignores the size bits, but the code is left intact
  375. ** for backwards and future compatibility.
  376. **
  377. ** Pkt size for allocating is data length +6 (for additional status
  378. ** words, length and ctl!)
  379. **
  380. ** If odd size then last byte is included in this header.
  381. */
  382. numPages = ((length & 0xfffe) + 6);
  383. numPages >>= 8; /* Divide by 256 */
  384. if (numPages > 7) {
  385. printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
  386. return 0;
  387. }
  388. /* now, try to allocate the memory */
  389. SMC_SELECT_BANK (dev, 2);
  390. SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
  391. /* FIXME: the ALLOC_INT bit never gets set *
  392. * so the following will always give a *
  393. * memory allocation error. *
  394. * same code works in armboot though *
  395. * -ro
  396. */
  397. again:
  398. try++;
  399. time_out = MEMORY_WAIT_TIME;
  400. do {
  401. status = SMC_inb (dev, SMC91111_INT_REG);
  402. if (status & IM_ALLOC_INT) {
  403. /* acknowledge the interrupt */
  404. SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
  405. break;
  406. }
  407. } while (--time_out);
  408. if (!time_out) {
  409. PRINTK2 ("%s: memory allocation, try %d failed ...\n",
  410. SMC_DEV_NAME, try);
  411. if (try < SMC_ALLOC_MAX_TRY)
  412. goto again;
  413. else
  414. return 0;
  415. }
  416. PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
  417. SMC_DEV_NAME, try);
  418. buf = (byte *) packet;
  419. /* If I get here, I _know_ there is a packet slot waiting for me */
  420. packet_no = SMC_inb (dev, AR_REG);
  421. if (packet_no & AR_FAILED) {
  422. /* or isn't there? BAD CHIP! */
  423. printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
  424. return 0;
  425. }
  426. /* we have a packet address, so tell the card to use it */
  427. SMC_outb (dev, packet_no, PN_REG);
  428. /* do not write new ptr value if Write data fifo not empty */
  429. while ( saved_ptr & PTR_NOTEMPTY )
  430. printf ("Write data fifo not empty!\n");
  431. /* point to the beginning of the packet */
  432. SMC_outw (dev, PTR_AUTOINC, PTR_REG);
  433. PRINTK3 ("%s: Trying to xmit packet of length %x\n",
  434. SMC_DEV_NAME, length);
  435. #if SMC_DEBUG > 2
  436. printf ("Transmitting Packet\n");
  437. print_packet (buf, length);
  438. #endif
  439. /* send the packet length ( +6 for status, length and ctl byte )
  440. and the status word ( set to zeros ) */
  441. #ifdef USE_32_BIT
  442. SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
  443. #else
  444. SMC_outw (dev, 0, SMC91111_DATA_REG);
  445. /* send the packet length ( +6 for status words, length, and ctl */
  446. SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
  447. #endif
  448. /* send the actual data
  449. . I _think_ it's faster to send the longs first, and then
  450. . mop up by sending the last word. It depends heavily
  451. . on alignment, at least on the 486. Maybe it would be
  452. . a good idea to check which is optimal? But that could take
  453. . almost as much time as is saved?
  454. */
  455. #ifdef USE_32_BIT
  456. SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
  457. if (length & 0x2)
  458. SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
  459. SMC91111_DATA_REG);
  460. #else
  461. SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
  462. #endif /* USE_32_BIT */
  463. /* Send the last byte, if there is one. */
  464. if ((length & 1) == 0) {
  465. SMC_outw (dev, 0, SMC91111_DATA_REG);
  466. } else {
  467. SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
  468. }
  469. /* and let the chipset deal with it */
  470. SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
  471. /* poll for TX INT */
  472. /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
  473. /* poll for TX_EMPTY INT - autorelease enabled */
  474. if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
  475. /* sending failed */
  476. PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
  477. /* release packet */
  478. /* no need to release, MMU does that now */
  479. /* wait for MMU getting ready (low) */
  480. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  481. udelay(10);
  482. }
  483. PRINTK2 ("MMU ready\n");
  484. return 0;
  485. } else {
  486. /* ack. int */
  487. SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
  488. /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
  489. PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
  490. length);
  491. /* release packet */
  492. /* no need to release, MMU does that now */
  493. /* wait for MMU getting ready (low) */
  494. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  495. udelay(10);
  496. }
  497. PRINTK2 ("MMU ready\n");
  498. }
  499. /* restore previously saved registers */
  500. SMC_outb( dev, saved_pnr, PN_REG );
  501. SMC_outw( dev, saved_ptr, PTR_REG );
  502. return length;
  503. }
  504. static int smc_write_hwaddr(struct eth_device *dev)
  505. {
  506. int i;
  507. swap_to(ETHERNET);
  508. SMC_SELECT_BANK (dev, 1);
  509. #ifdef USE_32_BIT
  510. for (i = 0; i < 6; i += 2) {
  511. word address;
  512. address = dev->enetaddr[i + 1] << 8;
  513. address |= dev->enetaddr[i];
  514. SMC_outw(dev, address, (ADDR0_REG + i));
  515. }
  516. #else
  517. for (i = 0; i < 6; i++)
  518. SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
  519. #endif
  520. swap_to(FLASH);
  521. return 0;
  522. }
  523. /*
  524. * Open and Initialize the board
  525. *
  526. * Set up everything, reset the card, etc ..
  527. *
  528. */
  529. static int smc_init(struct eth_device *dev, struct bd_info *bd)
  530. {
  531. swap_to(ETHERNET);
  532. PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
  533. /* reset the hardware */
  534. smc_reset (dev);
  535. smc_enable (dev);
  536. /* Configure the PHY */
  537. #ifndef CONFIG_SMC91111_EXT_PHY
  538. smc_phy_configure (dev);
  539. #endif
  540. /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
  541. /* SMC_SELECT_BANK(dev, 0); */
  542. /* SMC_outw(dev, 0, RPC_REG); */
  543. printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
  544. return 0;
  545. }
  546. /*-------------------------------------------------------------
  547. .
  548. . smc_rcv - receive a packet from the card
  549. .
  550. . There is ( at least ) a packet waiting to be read from
  551. . chip-memory.
  552. .
  553. . o Read the status
  554. . o If an error, record it
  555. . o otherwise, read in the packet
  556. --------------------------------------------------------------
  557. */
  558. static int smc_rcv(struct eth_device *dev)
  559. {
  560. int packet_number;
  561. word status;
  562. word packet_length;
  563. int is_error = 0;
  564. #ifdef USE_32_BIT
  565. dword stat_len;
  566. #endif
  567. byte saved_pnr;
  568. word saved_ptr;
  569. SMC_SELECT_BANK(dev, 2);
  570. /* save PTR and PTR registers */
  571. saved_pnr = SMC_inb( dev, PN_REG );
  572. saved_ptr = SMC_inw( dev, PTR_REG );
  573. packet_number = SMC_inw( dev, RXFIFO_REG );
  574. if ( packet_number & RXFIFO_REMPTY ) {
  575. return 0;
  576. }
  577. PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
  578. /* start reading from the start of the packet */
  579. SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
  580. /* First two words are status and packet_length */
  581. #ifdef USE_32_BIT
  582. stat_len = SMC_inl(dev, SMC91111_DATA_REG);
  583. status = stat_len & 0xffff;
  584. packet_length = stat_len >> 16;
  585. #else
  586. status = SMC_inw( dev, SMC91111_DATA_REG );
  587. packet_length = SMC_inw( dev, SMC91111_DATA_REG );
  588. #endif
  589. packet_length &= 0x07ff; /* mask off top bits */
  590. PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
  591. if ( !(status & RS_ERRORS ) ){
  592. /* Adjust for having already read the first two words */
  593. packet_length -= 4; /*4; */
  594. /* set odd length for bug in LAN91C111, */
  595. /* which never sets RS_ODDFRAME */
  596. /* TODO ? */
  597. #ifdef USE_32_BIT
  598. PRINTK3(" Reading %d dwords (and %d bytes)\n",
  599. packet_length >> 2, packet_length & 3 );
  600. /* QUESTION: Like in the TX routine, do I want
  601. to send the DWORDs or the bytes first, or some
  602. mixture. A mixture might improve already slow PIO
  603. performance */
  604. SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
  605. packet_length >> 2);
  606. /* read the left over bytes */
  607. if (packet_length & 3) {
  608. int i;
  609. byte *tail = (byte *)(net_rx_packets[0] +
  610. (packet_length & ~3));
  611. dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
  612. for (i=0; i<(packet_length & 3); i++)
  613. *tail++ = (byte) (leftover >> (8*i)) & 0xff;
  614. }
  615. #else
  616. PRINTK3(" Reading %d words and %d byte(s)\n",
  617. (packet_length >> 1 ), packet_length & 1 );
  618. SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
  619. packet_length >> 1);
  620. #endif /* USE_32_BIT */
  621. #if SMC_DEBUG > 2
  622. printf("Receiving Packet\n");
  623. print_packet(net_rx_packets[0], packet_length);
  624. #endif
  625. } else {
  626. /* error ... */
  627. /* TODO ? */
  628. is_error = 1;
  629. }
  630. while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
  631. udelay(1); /* Wait until not busy */
  632. /* error or good, tell the card to get rid of this packet */
  633. SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
  634. while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
  635. udelay(1); /* Wait until not busy */
  636. /* restore saved registers */
  637. SMC_outb( dev, saved_pnr, PN_REG );
  638. SMC_outw( dev, saved_ptr, PTR_REG );
  639. if (!is_error) {
  640. /* Pass the packet up to the protocol layers. */
  641. net_process_received_packet(net_rx_packets[0], packet_length);
  642. return packet_length;
  643. } else {
  644. return 0;
  645. }
  646. }
  647. #if 0
  648. /*------------------------------------------------------------
  649. . Modify a bit in the LAN91C111 register set
  650. .-------------------------------------------------------------*/
  651. static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
  652. unsigned int bit, int val)
  653. {
  654. word regval;
  655. SMC_SELECT_BANK( dev, bank );
  656. regval = SMC_inw( dev, reg );
  657. if (val)
  658. regval |= bit;
  659. else
  660. regval &= ~bit;
  661. SMC_outw( dev, regval, 0 );
  662. return(regval);
  663. }
  664. /*------------------------------------------------------------
  665. . Retrieve a bit in the LAN91C111 register set
  666. .-------------------------------------------------------------*/
  667. static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
  668. {
  669. SMC_SELECT_BANK( dev, bank );
  670. if ( SMC_inw( dev, reg ) & bit)
  671. return(1);
  672. else
  673. return(0);
  674. }
  675. /*------------------------------------------------------------
  676. . Modify a LAN91C111 register (word access only)
  677. .-------------------------------------------------------------*/
  678. static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
  679. {
  680. SMC_SELECT_BANK( dev, bank );
  681. SMC_outw( dev, val, reg );
  682. }
  683. /*------------------------------------------------------------
  684. . Retrieve a LAN91C111 register (word access only)
  685. .-------------------------------------------------------------*/
  686. static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
  687. {
  688. SMC_SELECT_BANK( dev, bank );
  689. return(SMC_inw( dev, reg ));
  690. }
  691. #endif /* 0 */
  692. /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
  693. #if (SMC_DEBUG > 2 )
  694. /*------------------------------------------------------------
  695. . Debugging function for viewing MII Management serial bitstream
  696. .-------------------------------------------------------------*/
  697. static void smc_dump_mii_stream (byte * bits, int size)
  698. {
  699. int i;
  700. printf ("BIT#:");
  701. for (i = 0; i < size; ++i) {
  702. printf ("%d", i % 10);
  703. }
  704. printf ("\nMDOE:");
  705. for (i = 0; i < size; ++i) {
  706. if (bits[i] & MII_MDOE)
  707. printf ("1");
  708. else
  709. printf ("0");
  710. }
  711. printf ("\nMDO :");
  712. for (i = 0; i < size; ++i) {
  713. if (bits[i] & MII_MDO)
  714. printf ("1");
  715. else
  716. printf ("0");
  717. }
  718. printf ("\nMDI :");
  719. for (i = 0; i < size; ++i) {
  720. if (bits[i] & MII_MDI)
  721. printf ("1");
  722. else
  723. printf ("0");
  724. }
  725. printf ("\n");
  726. }
  727. #endif
  728. /*------------------------------------------------------------
  729. . Reads a register from the MII Management serial interface
  730. .-------------------------------------------------------------*/
  731. #ifndef CONFIG_SMC91111_EXT_PHY
  732. static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
  733. {
  734. int oldBank;
  735. int i;
  736. byte mask;
  737. word mii_reg;
  738. byte bits[64];
  739. int clk_idx = 0;
  740. int input_idx;
  741. word phydata;
  742. byte phyaddr = SMC_PHY_ADDR;
  743. /* 32 consecutive ones on MDO to establish sync */
  744. for (i = 0; i < 32; ++i)
  745. bits[clk_idx++] = MII_MDOE | MII_MDO;
  746. /* Start code <01> */
  747. bits[clk_idx++] = MII_MDOE;
  748. bits[clk_idx++] = MII_MDOE | MII_MDO;
  749. /* Read command <10> */
  750. bits[clk_idx++] = MII_MDOE | MII_MDO;
  751. bits[clk_idx++] = MII_MDOE;
  752. /* Output the PHY address, msb first */
  753. mask = (byte) 0x10;
  754. for (i = 0; i < 5; ++i) {
  755. if (phyaddr & mask)
  756. bits[clk_idx++] = MII_MDOE | MII_MDO;
  757. else
  758. bits[clk_idx++] = MII_MDOE;
  759. /* Shift to next lowest bit */
  760. mask >>= 1;
  761. }
  762. /* Output the phy register number, msb first */
  763. mask = (byte) 0x10;
  764. for (i = 0; i < 5; ++i) {
  765. if (phyreg & mask)
  766. bits[clk_idx++] = MII_MDOE | MII_MDO;
  767. else
  768. bits[clk_idx++] = MII_MDOE;
  769. /* Shift to next lowest bit */
  770. mask >>= 1;
  771. }
  772. /* Tristate and turnaround (2 bit times) */
  773. bits[clk_idx++] = 0;
  774. /*bits[clk_idx++] = 0; */
  775. /* Input starts at this bit time */
  776. input_idx = clk_idx;
  777. /* Will input 16 bits */
  778. for (i = 0; i < 16; ++i)
  779. bits[clk_idx++] = 0;
  780. /* Final clock bit */
  781. bits[clk_idx++] = 0;
  782. /* Save the current bank */
  783. oldBank = SMC_inw (dev, BANK_SELECT);
  784. /* Select bank 3 */
  785. SMC_SELECT_BANK (dev, 3);
  786. /* Get the current MII register value */
  787. mii_reg = SMC_inw (dev, MII_REG);
  788. /* Turn off all MII Interface bits */
  789. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  790. /* Clock all 64 cycles */
  791. for (i = 0; i < sizeof bits; ++i) {
  792. /* Clock Low - output data */
  793. SMC_outw (dev, mii_reg | bits[i], MII_REG);
  794. udelay(SMC_PHY_CLOCK_DELAY);
  795. /* Clock Hi - input data */
  796. SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
  797. udelay(SMC_PHY_CLOCK_DELAY);
  798. bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  799. }
  800. /* Return to idle state */
  801. /* Set clock to low, data to low, and output tristated */
  802. SMC_outw (dev, mii_reg, MII_REG);
  803. udelay(SMC_PHY_CLOCK_DELAY);
  804. /* Restore original bank select */
  805. SMC_SELECT_BANK (dev, oldBank);
  806. /* Recover input data */
  807. phydata = 0;
  808. for (i = 0; i < 16; ++i) {
  809. phydata <<= 1;
  810. if (bits[input_idx++] & MII_MDI)
  811. phydata |= 0x0001;
  812. }
  813. #if (SMC_DEBUG > 2 )
  814. printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  815. phyaddr, phyreg, phydata);
  816. smc_dump_mii_stream (bits, sizeof bits);
  817. #endif
  818. return (phydata);
  819. }
  820. /*------------------------------------------------------------
  821. . Writes a register to the MII Management serial interface
  822. .-------------------------------------------------------------*/
  823. static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
  824. word phydata)
  825. {
  826. int oldBank;
  827. int i;
  828. word mask;
  829. word mii_reg;
  830. byte bits[65];
  831. int clk_idx = 0;
  832. byte phyaddr = SMC_PHY_ADDR;
  833. /* 32 consecutive ones on MDO to establish sync */
  834. for (i = 0; i < 32; ++i)
  835. bits[clk_idx++] = MII_MDOE | MII_MDO;
  836. /* Start code <01> */
  837. bits[clk_idx++] = MII_MDOE;
  838. bits[clk_idx++] = MII_MDOE | MII_MDO;
  839. /* Write command <01> */
  840. bits[clk_idx++] = MII_MDOE;
  841. bits[clk_idx++] = MII_MDOE | MII_MDO;
  842. /* Output the PHY address, msb first */
  843. mask = (byte) 0x10;
  844. for (i = 0; i < 5; ++i) {
  845. if (phyaddr & mask)
  846. bits[clk_idx++] = MII_MDOE | MII_MDO;
  847. else
  848. bits[clk_idx++] = MII_MDOE;
  849. /* Shift to next lowest bit */
  850. mask >>= 1;
  851. }
  852. /* Output the phy register number, msb first */
  853. mask = (byte) 0x10;
  854. for (i = 0; i < 5; ++i) {
  855. if (phyreg & mask)
  856. bits[clk_idx++] = MII_MDOE | MII_MDO;
  857. else
  858. bits[clk_idx++] = MII_MDOE;
  859. /* Shift to next lowest bit */
  860. mask >>= 1;
  861. }
  862. /* Tristate and turnaround (2 bit times) */
  863. bits[clk_idx++] = 0;
  864. bits[clk_idx++] = 0;
  865. /* Write out 16 bits of data, msb first */
  866. mask = 0x8000;
  867. for (i = 0; i < 16; ++i) {
  868. if (phydata & mask)
  869. bits[clk_idx++] = MII_MDOE | MII_MDO;
  870. else
  871. bits[clk_idx++] = MII_MDOE;
  872. /* Shift to next lowest bit */
  873. mask >>= 1;
  874. }
  875. /* Final clock bit (tristate) */
  876. bits[clk_idx++] = 0;
  877. /* Save the current bank */
  878. oldBank = SMC_inw (dev, BANK_SELECT);
  879. /* Select bank 3 */
  880. SMC_SELECT_BANK (dev, 3);
  881. /* Get the current MII register value */
  882. mii_reg = SMC_inw (dev, MII_REG);
  883. /* Turn off all MII Interface bits */
  884. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  885. /* Clock all cycles */
  886. for (i = 0; i < sizeof bits; ++i) {
  887. /* Clock Low - output data */
  888. SMC_outw (dev, mii_reg | bits[i], MII_REG);
  889. udelay(SMC_PHY_CLOCK_DELAY);
  890. /* Clock Hi - input data */
  891. SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
  892. udelay(SMC_PHY_CLOCK_DELAY);
  893. bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  894. }
  895. /* Return to idle state */
  896. /* Set clock to low, data to low, and output tristated */
  897. SMC_outw (dev, mii_reg, MII_REG);
  898. udelay(SMC_PHY_CLOCK_DELAY);
  899. /* Restore original bank select */
  900. SMC_SELECT_BANK (dev, oldBank);
  901. #if (SMC_DEBUG > 2 )
  902. printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  903. phyaddr, phyreg, phydata);
  904. smc_dump_mii_stream (bits, sizeof bits);
  905. #endif
  906. }
  907. #endif /* !CONFIG_SMC91111_EXT_PHY */
  908. /*------------------------------------------------------------
  909. . Configures the specified PHY using Autonegotiation. Calls
  910. . smc_phy_fixed() if the user has requested a certain config.
  911. .-------------------------------------------------------------*/
  912. #ifndef CONFIG_SMC91111_EXT_PHY
  913. static void smc_phy_configure (struct eth_device *dev)
  914. {
  915. int timeout;
  916. word my_phy_caps; /* My PHY capabilities */
  917. word my_ad_caps; /* My Advertised capabilities */
  918. word status = 0; /*;my status = 0 */
  919. PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
  920. /* Reset the PHY, setting all other bits to zero */
  921. smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
  922. /* Wait for the reset to complete, or time out */
  923. timeout = 6; /* Wait up to 3 seconds */
  924. while (timeout--) {
  925. if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
  926. & PHY_CNTL_RST)) {
  927. /* reset complete */
  928. break;
  929. }
  930. mdelay(500); /* wait 500 millisecs */
  931. }
  932. if (timeout < 1) {
  933. printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
  934. goto smc_phy_configure_exit;
  935. }
  936. /* Read PHY Register 18, Status Output */
  937. /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
  938. /* Enable PHY Interrupts (for register 18) */
  939. /* Interrupts listed here are disabled */
  940. smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
  941. /* Configure the Receive/Phy Control register */
  942. SMC_SELECT_BANK (dev, 0);
  943. SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  944. /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
  945. my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
  946. my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
  947. if (my_phy_caps & PHY_STAT_CAP_T4)
  948. my_ad_caps |= PHY_AD_T4;
  949. if (my_phy_caps & PHY_STAT_CAP_TXF)
  950. my_ad_caps |= PHY_AD_TX_FDX;
  951. if (my_phy_caps & PHY_STAT_CAP_TXH)
  952. my_ad_caps |= PHY_AD_TX_HDX;
  953. if (my_phy_caps & PHY_STAT_CAP_TF)
  954. my_ad_caps |= PHY_AD_10_FDX;
  955. if (my_phy_caps & PHY_STAT_CAP_TH)
  956. my_ad_caps |= PHY_AD_10_HDX;
  957. /* Update our Auto-Neg Advertisement Register */
  958. smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
  959. /* Read the register back. Without this, it appears that when */
  960. /* auto-negotiation is restarted, sometimes it isn't ready and */
  961. /* the link does not come up. */
  962. smc_read_phy_register(dev, PHY_AD_REG);
  963. PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
  964. PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
  965. /* Restart auto-negotiation process in order to advertise my caps */
  966. smc_write_phy_register (dev, PHY_CNTL_REG,
  967. PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
  968. /* Wait for the auto-negotiation to complete. This may take from */
  969. /* 2 to 3 seconds. */
  970. /* Wait for the reset to complete, or time out */
  971. timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
  972. while (timeout--) {
  973. status = smc_read_phy_register (dev, PHY_STAT_REG);
  974. if (status & PHY_STAT_ANEG_ACK) {
  975. /* auto-negotiate complete */
  976. break;
  977. }
  978. mdelay(500); /* wait 500 millisecs */
  979. /* Restart auto-negotiation if remote fault */
  980. if (status & PHY_STAT_REM_FLT) {
  981. printf ("%s: PHY remote fault detected\n",
  982. SMC_DEV_NAME);
  983. /* Restart auto-negotiation */
  984. printf ("%s: PHY restarting auto-negotiation\n",
  985. SMC_DEV_NAME);
  986. smc_write_phy_register (dev, PHY_CNTL_REG,
  987. PHY_CNTL_ANEG_EN |
  988. PHY_CNTL_ANEG_RST |
  989. PHY_CNTL_SPEED |
  990. PHY_CNTL_DPLX);
  991. }
  992. }
  993. if (timeout < 1) {
  994. printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
  995. }
  996. /* Fail if we detected an auto-negotiate remote fault */
  997. if (status & PHY_STAT_REM_FLT) {
  998. printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
  999. }
  1000. /* Re-Configure the Receive/Phy Control register */
  1001. SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  1002. smc_phy_configure_exit: ;
  1003. }
  1004. #endif /* !CONFIG_SMC91111_EXT_PHY */
  1005. #if SMC_DEBUG > 2
  1006. static void print_packet( byte * buf, int length )
  1007. {
  1008. int i;
  1009. int remainder;
  1010. int lines;
  1011. printf("Packet of length %d \n", length );
  1012. #if SMC_DEBUG > 3
  1013. lines = length / 16;
  1014. remainder = length % 16;
  1015. for ( i = 0; i < lines ; i ++ ) {
  1016. int cur;
  1017. for ( cur = 0; cur < 8; cur ++ ) {
  1018. byte a, b;
  1019. a = *(buf ++ );
  1020. b = *(buf ++ );
  1021. printf("%02x%02x ", a, b );
  1022. }
  1023. printf("\n");
  1024. }
  1025. for ( i = 0; i < remainder/2 ; i++ ) {
  1026. byte a, b;
  1027. a = *(buf ++ );
  1028. b = *(buf ++ );
  1029. printf("%02x%02x ", a, b );
  1030. }
  1031. printf("\n");
  1032. #endif
  1033. }
  1034. #endif
  1035. int smc91111_initialize(u8 dev_num, phys_addr_t base_addr)
  1036. {
  1037. struct smc91111_priv *priv;
  1038. struct eth_device *dev;
  1039. int i;
  1040. priv = malloc(sizeof(*priv));
  1041. if (!priv)
  1042. return 0;
  1043. dev = malloc(sizeof(*dev));
  1044. if (!dev) {
  1045. free(priv);
  1046. return 0;
  1047. }
  1048. memset(dev, 0, sizeof(*dev));
  1049. priv->dev_num = dev_num;
  1050. dev->priv = priv;
  1051. dev->iobase = base_addr;
  1052. swap_to(ETHERNET);
  1053. SMC_SELECT_BANK(dev, 1);
  1054. for (i = 0; i < 6; ++i)
  1055. dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
  1056. swap_to(FLASH);
  1057. dev->init = smc_init;
  1058. dev->halt = smc_halt;
  1059. dev->send = smc_send;
  1060. dev->recv = smc_rcv;
  1061. dev->write_hwaddr = smc_write_hwaddr;
  1062. sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
  1063. eth_register(dev);
  1064. return 0;
  1065. }