sh_eth.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sh_eth.c - Driver for Renesas ethernet controller.
  4. *
  5. * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  6. * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
  7. * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  8. * Copyright (C) 2013, 2014 Renesas Electronics Corporation
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <env.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <miiphy.h>
  19. #include <asm/cache.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <asm/global_data.h>
  23. #include <asm/io.h>
  24. #ifdef CONFIG_DM_ETH
  25. #include <clk.h>
  26. #include <dm.h>
  27. #include <linux/mii.h>
  28. #include <asm/gpio.h>
  29. #endif
  30. #include "sh_eth.h"
  31. #ifndef CONFIG_SH_ETHER_USE_PORT
  32. # error "Please define CONFIG_SH_ETHER_USE_PORT"
  33. #endif
  34. #ifndef CONFIG_SH_ETHER_PHY_ADDR
  35. # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  36. #endif
  37. #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  38. !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  39. #define flush_cache_wback(addr, len) \
  40. flush_dcache_range((unsigned long)addr, \
  41. (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  42. #else
  43. #define flush_cache_wback(...)
  44. #endif
  45. #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  46. #define invalidate_cache(addr, len) \
  47. { \
  48. unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
  49. unsigned long start, end; \
  50. \
  51. start = (unsigned long)addr; \
  52. end = start + len; \
  53. start &= ~(line_size - 1); \
  54. end = ((end + line_size - 1) & ~(line_size - 1)); \
  55. \
  56. invalidate_dcache_range(start, end); \
  57. }
  58. #else
  59. #define invalidate_cache(...)
  60. #endif
  61. #define TIMEOUT_CNT 1000
  62. static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  63. {
  64. int ret = 0, timeout;
  65. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  66. if (!packet || len > 0xffff) {
  67. printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  68. ret = -EINVAL;
  69. goto err;
  70. }
  71. /* packet must be a 4 byte boundary */
  72. if ((uintptr_t)packet & 3) {
  73. printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  74. , __func__);
  75. ret = -EFAULT;
  76. goto err;
  77. }
  78. /* Update tx descriptor */
  79. flush_cache_wback(packet, len);
  80. port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  81. port_info->tx_desc_cur->td1 = len << 16;
  82. /* Must preserve the end of descriptor list indication */
  83. if (port_info->tx_desc_cur->td0 & TD_TDLE)
  84. port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  85. else
  86. port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  87. flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  88. /* Restart the transmitter if disabled */
  89. if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  90. sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  91. /* Wait until packet is transmitted */
  92. timeout = TIMEOUT_CNT;
  93. do {
  94. invalidate_cache(port_info->tx_desc_cur,
  95. sizeof(struct tx_desc_s));
  96. udelay(100);
  97. } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
  98. if (timeout < 0) {
  99. printf(SHETHER_NAME ": transmit timeout\n");
  100. ret = -ETIMEDOUT;
  101. goto err;
  102. }
  103. port_info->tx_desc_cur++;
  104. if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
  105. port_info->tx_desc_cur = port_info->tx_desc_base;
  106. err:
  107. return ret;
  108. }
  109. static int sh_eth_recv_start(struct sh_eth_dev *eth)
  110. {
  111. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  112. /* Check if the rx descriptor is ready */
  113. invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
  114. if (port_info->rx_desc_cur->rd0 & RD_RACT)
  115. return -EINVAL;
  116. /* Check for errors */
  117. if (port_info->rx_desc_cur->rd0 & RD_RFE)
  118. return -EINVAL;
  119. return port_info->rx_desc_cur->rd1 & 0xffff;
  120. }
  121. static void sh_eth_recv_finish(struct sh_eth_dev *eth)
  122. {
  123. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  124. /* Make current descriptor available again */
  125. if (port_info->rx_desc_cur->rd0 & RD_RDLE)
  126. port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
  127. else
  128. port_info->rx_desc_cur->rd0 = RD_RACT;
  129. flush_cache_wback(port_info->rx_desc_cur,
  130. sizeof(struct rx_desc_s));
  131. /* Point to the next descriptor */
  132. port_info->rx_desc_cur++;
  133. if (port_info->rx_desc_cur >=
  134. port_info->rx_desc_base + NUM_RX_DESC)
  135. port_info->rx_desc_cur = port_info->rx_desc_base;
  136. }
  137. static int sh_eth_reset(struct sh_eth_dev *eth)
  138. {
  139. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  140. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  141. int ret = 0, i;
  142. /* Start e-dmac transmitter and receiver */
  143. sh_eth_write(port_info, EDSR_ENALL, EDSR);
  144. /* Perform a software reset and wait for it to complete */
  145. sh_eth_write(port_info, EDMR_SRST, EDMR);
  146. for (i = 0; i < TIMEOUT_CNT; i++) {
  147. if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
  148. break;
  149. udelay(1000);
  150. }
  151. if (i == TIMEOUT_CNT) {
  152. printf(SHETHER_NAME ": Software reset timeout\n");
  153. ret = -EIO;
  154. }
  155. return ret;
  156. #else
  157. sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
  158. mdelay(3);
  159. sh_eth_write(port_info,
  160. sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
  161. return 0;
  162. #endif
  163. }
  164. static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
  165. {
  166. int i, ret = 0;
  167. u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
  168. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  169. struct tx_desc_s *cur_tx_desc;
  170. /*
  171. * Allocate rx descriptors. They must be aligned to size of struct
  172. * tx_desc_s.
  173. */
  174. port_info->tx_desc_alloc =
  175. memalign(sizeof(struct tx_desc_s), alloc_desc_size);
  176. if (!port_info->tx_desc_alloc) {
  177. printf(SHETHER_NAME ": memalign failed\n");
  178. ret = -ENOMEM;
  179. goto err;
  180. }
  181. flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
  182. /* Make sure we use a P2 address (non-cacheable) */
  183. port_info->tx_desc_base =
  184. (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
  185. port_info->tx_desc_cur = port_info->tx_desc_base;
  186. /* Initialize all descriptors */
  187. for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
  188. cur_tx_desc++, i++) {
  189. cur_tx_desc->td0 = 0x00;
  190. cur_tx_desc->td1 = 0x00;
  191. cur_tx_desc->td2 = 0x00;
  192. }
  193. /* Mark the end of the descriptors */
  194. cur_tx_desc--;
  195. cur_tx_desc->td0 |= TD_TDLE;
  196. /*
  197. * Point the controller to the tx descriptor list. Must use physical
  198. * addresses
  199. */
  200. sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
  201. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  202. sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
  203. sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
  204. sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
  205. #endif
  206. err:
  207. return ret;
  208. }
  209. static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
  210. {
  211. int i, ret = 0;
  212. u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
  213. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  214. struct rx_desc_s *cur_rx_desc;
  215. u8 *rx_buf;
  216. /*
  217. * Allocate rx descriptors. They must be aligned to size of struct
  218. * rx_desc_s.
  219. */
  220. port_info->rx_desc_alloc =
  221. memalign(sizeof(struct rx_desc_s), alloc_desc_size);
  222. if (!port_info->rx_desc_alloc) {
  223. printf(SHETHER_NAME ": memalign failed\n");
  224. ret = -ENOMEM;
  225. goto err;
  226. }
  227. flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
  228. /* Make sure we use a P2 address (non-cacheable) */
  229. port_info->rx_desc_base =
  230. (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
  231. port_info->rx_desc_cur = port_info->rx_desc_base;
  232. /*
  233. * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
  234. * aligned and in P2 area.
  235. */
  236. port_info->rx_buf_alloc =
  237. memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
  238. if (!port_info->rx_buf_alloc) {
  239. printf(SHETHER_NAME ": alloc failed\n");
  240. ret = -ENOMEM;
  241. goto err_buf_alloc;
  242. }
  243. port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
  244. /* Initialize all descriptors */
  245. for (cur_rx_desc = port_info->rx_desc_base,
  246. rx_buf = port_info->rx_buf_base, i = 0;
  247. i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
  248. cur_rx_desc->rd0 = RD_RACT;
  249. cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
  250. cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
  251. }
  252. /* Mark the end of the descriptors */
  253. cur_rx_desc--;
  254. cur_rx_desc->rd0 |= RD_RDLE;
  255. /* Point the controller to the rx descriptor list */
  256. sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
  257. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  258. sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
  259. sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
  260. sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
  261. #endif
  262. return ret;
  263. err_buf_alloc:
  264. free(port_info->rx_desc_alloc);
  265. port_info->rx_desc_alloc = NULL;
  266. err:
  267. return ret;
  268. }
  269. static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
  270. {
  271. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  272. if (port_info->tx_desc_alloc) {
  273. free(port_info->tx_desc_alloc);
  274. port_info->tx_desc_alloc = NULL;
  275. }
  276. }
  277. static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
  278. {
  279. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  280. if (port_info->rx_desc_alloc) {
  281. free(port_info->rx_desc_alloc);
  282. port_info->rx_desc_alloc = NULL;
  283. }
  284. if (port_info->rx_buf_alloc) {
  285. free(port_info->rx_buf_alloc);
  286. port_info->rx_buf_alloc = NULL;
  287. }
  288. }
  289. static int sh_eth_desc_init(struct sh_eth_dev *eth)
  290. {
  291. int ret = 0;
  292. ret = sh_eth_tx_desc_init(eth);
  293. if (ret)
  294. goto err_tx_init;
  295. ret = sh_eth_rx_desc_init(eth);
  296. if (ret)
  297. goto err_rx_init;
  298. return ret;
  299. err_rx_init:
  300. sh_eth_tx_desc_free(eth);
  301. err_tx_init:
  302. return ret;
  303. }
  304. static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
  305. unsigned char *mac)
  306. {
  307. u32 val;
  308. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  309. sh_eth_write(port_info, val, MAHR);
  310. val = (mac[4] << 8) | mac[5];
  311. sh_eth_write(port_info, val, MALR);
  312. }
  313. static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
  314. {
  315. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  316. unsigned long edmr;
  317. /* Configure e-dmac registers */
  318. edmr = sh_eth_read(port_info, EDMR);
  319. edmr &= ~EMDR_DESC_R;
  320. edmr |= EMDR_DESC | EDMR_EL;
  321. #if defined(CONFIG_R8A77980)
  322. edmr |= EDMR_NBST;
  323. #endif
  324. sh_eth_write(port_info, edmr, EDMR);
  325. sh_eth_write(port_info, 0, EESIPR);
  326. sh_eth_write(port_info, 0, TRSCER);
  327. sh_eth_write(port_info, 0, TFTR);
  328. sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
  329. sh_eth_write(port_info, RMCR_RST, RMCR);
  330. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  331. sh_eth_write(port_info, 0, RPADIR);
  332. #endif
  333. sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
  334. /* Configure e-mac registers */
  335. sh_eth_write(port_info, 0, ECSIPR);
  336. /* Set Mac address */
  337. sh_eth_write_hwaddr(port_info, mac);
  338. sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
  339. #if defined(SH_ETH_TYPE_GETHER)
  340. sh_eth_write(port_info, 0, PIPR);
  341. #endif
  342. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  343. sh_eth_write(port_info, APR_AP, APR);
  344. sh_eth_write(port_info, MPR_MP, MPR);
  345. sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
  346. #endif
  347. #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
  348. sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
  349. #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
  350. sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
  351. #endif
  352. }
  353. static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
  354. {
  355. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  356. struct phy_device *phy = port_info->phydev;
  357. int ret = 0;
  358. u32 val = 0;
  359. /* Set the transfer speed */
  360. if (phy->speed == 100) {
  361. printf(SHETHER_NAME ": 100Base/");
  362. #if defined(SH_ETH_TYPE_GETHER)
  363. sh_eth_write(port_info, GECMR_100B, GECMR);
  364. #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
  365. sh_eth_write(port_info, 1, RTRATE);
  366. #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
  367. val = ECMR_RTM;
  368. #endif
  369. } else if (phy->speed == 10) {
  370. printf(SHETHER_NAME ": 10Base/");
  371. #if defined(SH_ETH_TYPE_GETHER)
  372. sh_eth_write(port_info, GECMR_10B, GECMR);
  373. #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
  374. sh_eth_write(port_info, 0, RTRATE);
  375. #endif
  376. }
  377. #if defined(SH_ETH_TYPE_GETHER)
  378. else if (phy->speed == 1000) {
  379. printf(SHETHER_NAME ": 1000Base/");
  380. sh_eth_write(port_info, GECMR_1000B, GECMR);
  381. }
  382. #endif
  383. /* Check if full duplex mode is supported by the phy */
  384. if (phy->duplex) {
  385. printf("Full\n");
  386. sh_eth_write(port_info,
  387. val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
  388. ECMR);
  389. } else {
  390. printf("Half\n");
  391. sh_eth_write(port_info,
  392. val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
  393. ECMR);
  394. }
  395. return ret;
  396. }
  397. static void sh_eth_start(struct sh_eth_dev *eth)
  398. {
  399. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  400. /*
  401. * Enable the e-dmac receiver only. The transmitter will be enabled when
  402. * we have something to transmit
  403. */
  404. sh_eth_write(port_info, EDRRR_R, EDRRR);
  405. }
  406. static void sh_eth_stop(struct sh_eth_dev *eth)
  407. {
  408. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  409. sh_eth_write(port_info, ~EDRRR_R, EDRRR);
  410. }
  411. static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
  412. {
  413. int ret = 0;
  414. ret = sh_eth_reset(eth);
  415. if (ret)
  416. return ret;
  417. ret = sh_eth_desc_init(eth);
  418. if (ret)
  419. return ret;
  420. sh_eth_mac_regs_config(eth, mac);
  421. return 0;
  422. }
  423. static int sh_eth_start_common(struct sh_eth_dev *eth)
  424. {
  425. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  426. int ret;
  427. ret = phy_startup(port_info->phydev);
  428. if (ret) {
  429. printf(SHETHER_NAME ": phy startup failure\n");
  430. return ret;
  431. }
  432. ret = sh_eth_phy_regs_config(eth);
  433. if (ret)
  434. return ret;
  435. sh_eth_start(eth);
  436. return 0;
  437. }
  438. #ifndef CONFIG_DM_ETH
  439. static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
  440. {
  441. int ret = 0;
  442. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  443. struct eth_device *dev = port_info->dev;
  444. struct phy_device *phydev;
  445. phydev = phy_connect(
  446. miiphy_get_dev_by_name(dev->name),
  447. port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
  448. port_info->phydev = phydev;
  449. phy_config(phydev);
  450. return ret;
  451. }
  452. static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
  453. {
  454. struct sh_eth_dev *eth = dev->priv;
  455. return sh_eth_send_common(eth, packet, len);
  456. }
  457. static int sh_eth_recv_common(struct sh_eth_dev *eth)
  458. {
  459. int len = 0;
  460. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  461. uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
  462. len = sh_eth_recv_start(eth);
  463. if (len > 0) {
  464. invalidate_cache(packet, len);
  465. net_process_received_packet(packet, len);
  466. sh_eth_recv_finish(eth);
  467. } else
  468. len = 0;
  469. /* Restart the receiver if disabled */
  470. if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
  471. sh_eth_write(port_info, EDRRR_R, EDRRR);
  472. return len;
  473. }
  474. static int sh_eth_recv_legacy(struct eth_device *dev)
  475. {
  476. struct sh_eth_dev *eth = dev->priv;
  477. return sh_eth_recv_common(eth);
  478. }
  479. static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd)
  480. {
  481. struct sh_eth_dev *eth = dev->priv;
  482. int ret;
  483. ret = sh_eth_init_common(eth, dev->enetaddr);
  484. if (ret)
  485. return ret;
  486. ret = sh_eth_phy_config_legacy(eth);
  487. if (ret) {
  488. printf(SHETHER_NAME ": phy config timeout\n");
  489. goto err_start;
  490. }
  491. ret = sh_eth_start_common(eth);
  492. if (ret)
  493. goto err_start;
  494. return 0;
  495. err_start:
  496. sh_eth_tx_desc_free(eth);
  497. sh_eth_rx_desc_free(eth);
  498. return ret;
  499. }
  500. void sh_eth_halt_legacy(struct eth_device *dev)
  501. {
  502. struct sh_eth_dev *eth = dev->priv;
  503. sh_eth_stop(eth);
  504. }
  505. int sh_eth_initialize(struct bd_info *bd)
  506. {
  507. int ret = 0;
  508. struct sh_eth_dev *eth = NULL;
  509. struct eth_device *dev = NULL;
  510. struct mii_dev *mdiodev;
  511. eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
  512. if (!eth) {
  513. printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
  514. ret = -ENOMEM;
  515. goto err;
  516. }
  517. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  518. if (!dev) {
  519. printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
  520. ret = -ENOMEM;
  521. goto err;
  522. }
  523. memset(dev, 0, sizeof(struct eth_device));
  524. memset(eth, 0, sizeof(struct sh_eth_dev));
  525. eth->port = CONFIG_SH_ETHER_USE_PORT;
  526. eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
  527. eth->port_info[eth->port].iobase =
  528. (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
  529. dev->priv = (void *)eth;
  530. dev->iobase = 0;
  531. dev->init = sh_eth_init_legacy;
  532. dev->halt = sh_eth_halt_legacy;
  533. dev->send = sh_eth_send_legacy;
  534. dev->recv = sh_eth_recv_legacy;
  535. eth->port_info[eth->port].dev = dev;
  536. strcpy(dev->name, SHETHER_NAME);
  537. /* Register Device to EtherNet subsystem */
  538. eth_register(dev);
  539. bb_miiphy_buses[0].priv = eth;
  540. mdiodev = mdio_alloc();
  541. if (!mdiodev)
  542. return -ENOMEM;
  543. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  544. mdiodev->read = bb_miiphy_read;
  545. mdiodev->write = bb_miiphy_write;
  546. ret = mdio_register(mdiodev);
  547. if (ret < 0)
  548. return ret;
  549. if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
  550. puts("Please set MAC address\n");
  551. return ret;
  552. err:
  553. if (dev)
  554. free(dev);
  555. if (eth)
  556. free(eth);
  557. printf(SHETHER_NAME ": Failed\n");
  558. return ret;
  559. }
  560. #else /* CONFIG_DM_ETH */
  561. struct sh_ether_priv {
  562. struct sh_eth_dev shdev;
  563. struct mii_dev *bus;
  564. phys_addr_t iobase;
  565. struct clk clk;
  566. struct gpio_desc reset_gpio;
  567. };
  568. static int sh_ether_send(struct udevice *dev, void *packet, int len)
  569. {
  570. struct sh_ether_priv *priv = dev_get_priv(dev);
  571. struct sh_eth_dev *eth = &priv->shdev;
  572. return sh_eth_send_common(eth, packet, len);
  573. }
  574. static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
  575. {
  576. struct sh_ether_priv *priv = dev_get_priv(dev);
  577. struct sh_eth_dev *eth = &priv->shdev;
  578. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  579. uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
  580. int len;
  581. len = sh_eth_recv_start(eth);
  582. if (len > 0) {
  583. invalidate_cache(packet, len);
  584. *packetp = packet;
  585. return len;
  586. } else {
  587. len = 0;
  588. /* Restart the receiver if disabled */
  589. if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
  590. sh_eth_write(port_info, EDRRR_R, EDRRR);
  591. return -EAGAIN;
  592. }
  593. }
  594. static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
  595. {
  596. struct sh_ether_priv *priv = dev_get_priv(dev);
  597. struct sh_eth_dev *eth = &priv->shdev;
  598. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  599. sh_eth_recv_finish(eth);
  600. /* Restart the receiver if disabled */
  601. if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
  602. sh_eth_write(port_info, EDRRR_R, EDRRR);
  603. return 0;
  604. }
  605. static int sh_ether_write_hwaddr(struct udevice *dev)
  606. {
  607. struct sh_ether_priv *priv = dev_get_priv(dev);
  608. struct sh_eth_dev *eth = &priv->shdev;
  609. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  610. struct eth_pdata *pdata = dev_get_plat(dev);
  611. sh_eth_write_hwaddr(port_info, pdata->enetaddr);
  612. return 0;
  613. }
  614. static int sh_eth_phy_config(struct udevice *dev)
  615. {
  616. struct sh_ether_priv *priv = dev_get_priv(dev);
  617. struct eth_pdata *pdata = dev_get_plat(dev);
  618. struct sh_eth_dev *eth = &priv->shdev;
  619. int ret = 0;
  620. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  621. struct phy_device *phydev;
  622. int mask = 0xffffffff;
  623. phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
  624. if (!phydev)
  625. return -ENODEV;
  626. phy_connect_dev(phydev, dev);
  627. port_info->phydev = phydev;
  628. phy_config(phydev);
  629. return ret;
  630. }
  631. static int sh_ether_start(struct udevice *dev)
  632. {
  633. struct sh_ether_priv *priv = dev_get_priv(dev);
  634. struct eth_pdata *pdata = dev_get_plat(dev);
  635. struct sh_eth_dev *eth = &priv->shdev;
  636. int ret;
  637. ret = sh_eth_init_common(eth, pdata->enetaddr);
  638. if (ret)
  639. return ret;
  640. ret = sh_eth_start_common(eth);
  641. if (ret)
  642. goto err_start;
  643. return 0;
  644. err_start:
  645. sh_eth_tx_desc_free(eth);
  646. sh_eth_rx_desc_free(eth);
  647. return ret;
  648. }
  649. static void sh_ether_stop(struct udevice *dev)
  650. {
  651. struct sh_ether_priv *priv = dev_get_priv(dev);
  652. struct sh_eth_dev *eth = &priv->shdev;
  653. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  654. phy_shutdown(port_info->phydev);
  655. sh_eth_stop(&priv->shdev);
  656. }
  657. static int sh_ether_probe(struct udevice *udev)
  658. {
  659. struct eth_pdata *pdata = dev_get_plat(udev);
  660. struct sh_ether_priv *priv = dev_get_priv(udev);
  661. struct sh_eth_dev *eth = &priv->shdev;
  662. struct ofnode_phandle_args phandle_args;
  663. struct mii_dev *mdiodev;
  664. int ret;
  665. priv->iobase = pdata->iobase;
  666. #if CONFIG_IS_ENABLED(CLK)
  667. ret = clk_get_by_index(udev, 0, &priv->clk);
  668. if (ret < 0)
  669. return ret;
  670. #endif
  671. ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
  672. if (!ret) {
  673. gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
  674. &priv->reset_gpio, GPIOD_IS_OUT);
  675. }
  676. if (!dm_gpio_is_valid(&priv->reset_gpio)) {
  677. gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
  678. GPIOD_IS_OUT);
  679. }
  680. mdiodev = mdio_alloc();
  681. if (!mdiodev) {
  682. ret = -ENOMEM;
  683. return ret;
  684. }
  685. mdiodev->read = bb_miiphy_read;
  686. mdiodev->write = bb_miiphy_write;
  687. bb_miiphy_buses[0].priv = eth;
  688. snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
  689. ret = mdio_register(mdiodev);
  690. if (ret < 0)
  691. goto err_mdio_register;
  692. priv->bus = miiphy_get_dev_by_name(udev->name);
  693. eth->port = CONFIG_SH_ETHER_USE_PORT;
  694. eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
  695. eth->port_info[eth->port].iobase =
  696. (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
  697. #if CONFIG_IS_ENABLED(CLK)
  698. ret = clk_enable(&priv->clk);
  699. if (ret)
  700. goto err_mdio_register;
  701. #endif
  702. ret = sh_eth_init_common(eth, pdata->enetaddr);
  703. if (ret)
  704. goto err_phy_config;
  705. ret = sh_eth_phy_config(udev);
  706. if (ret) {
  707. printf(SHETHER_NAME ": phy config timeout\n");
  708. goto err_phy_config;
  709. }
  710. return 0;
  711. err_phy_config:
  712. #if CONFIG_IS_ENABLED(CLK)
  713. clk_disable(&priv->clk);
  714. #endif
  715. err_mdio_register:
  716. mdio_free(mdiodev);
  717. return ret;
  718. }
  719. static int sh_ether_remove(struct udevice *udev)
  720. {
  721. struct sh_ether_priv *priv = dev_get_priv(udev);
  722. struct sh_eth_dev *eth = &priv->shdev;
  723. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  724. #if CONFIG_IS_ENABLED(CLK)
  725. clk_disable(&priv->clk);
  726. #endif
  727. free(port_info->phydev);
  728. mdio_unregister(priv->bus);
  729. mdio_free(priv->bus);
  730. if (dm_gpio_is_valid(&priv->reset_gpio))
  731. dm_gpio_free(udev, &priv->reset_gpio);
  732. return 0;
  733. }
  734. static const struct eth_ops sh_ether_ops = {
  735. .start = sh_ether_start,
  736. .send = sh_ether_send,
  737. .recv = sh_ether_recv,
  738. .free_pkt = sh_ether_free_pkt,
  739. .stop = sh_ether_stop,
  740. .write_hwaddr = sh_ether_write_hwaddr,
  741. };
  742. int sh_ether_of_to_plat(struct udevice *dev)
  743. {
  744. struct eth_pdata *pdata = dev_get_plat(dev);
  745. const char *phy_mode;
  746. const fdt32_t *cell;
  747. int ret = 0;
  748. pdata->iobase = dev_read_addr(dev);
  749. pdata->phy_interface = -1;
  750. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  751. NULL);
  752. if (phy_mode)
  753. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  754. if (pdata->phy_interface == -1) {
  755. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  756. return -EINVAL;
  757. }
  758. pdata->max_speed = 1000;
  759. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
  760. if (cell)
  761. pdata->max_speed = fdt32_to_cpu(*cell);
  762. sprintf(bb_miiphy_buses[0].name, dev->name);
  763. return ret;
  764. }
  765. static const struct udevice_id sh_ether_ids[] = {
  766. { .compatible = "renesas,ether-r7s72100" },
  767. { .compatible = "renesas,ether-r8a7790" },
  768. { .compatible = "renesas,ether-r8a7791" },
  769. { .compatible = "renesas,ether-r8a7793" },
  770. { .compatible = "renesas,ether-r8a7794" },
  771. { .compatible = "renesas,gether-r8a77980" },
  772. { }
  773. };
  774. U_BOOT_DRIVER(eth_sh_ether) = {
  775. .name = "sh_ether",
  776. .id = UCLASS_ETH,
  777. .of_match = sh_ether_ids,
  778. .of_to_plat = sh_ether_of_to_plat,
  779. .probe = sh_ether_probe,
  780. .remove = sh_ether_remove,
  781. .ops = &sh_ether_ops,
  782. .priv_auto = sizeof(struct sh_ether_priv),
  783. .plat_auto = sizeof(struct eth_pdata),
  784. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  785. };
  786. #endif
  787. /******* for bb_miiphy *******/
  788. static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
  789. {
  790. return 0;
  791. }
  792. static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
  793. {
  794. struct sh_eth_dev *eth = bus->priv;
  795. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  796. sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
  797. return 0;
  798. }
  799. static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
  800. {
  801. struct sh_eth_dev *eth = bus->priv;
  802. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  803. sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
  804. return 0;
  805. }
  806. static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
  807. {
  808. struct sh_eth_dev *eth = bus->priv;
  809. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  810. if (v)
  811. sh_eth_write(port_info,
  812. sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
  813. else
  814. sh_eth_write(port_info,
  815. sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
  816. return 0;
  817. }
  818. static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
  819. {
  820. struct sh_eth_dev *eth = bus->priv;
  821. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  822. *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
  823. return 0;
  824. }
  825. static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
  826. {
  827. struct sh_eth_dev *eth = bus->priv;
  828. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  829. if (v)
  830. sh_eth_write(port_info,
  831. sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
  832. else
  833. sh_eth_write(port_info,
  834. sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
  835. return 0;
  836. }
  837. static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
  838. {
  839. udelay(10);
  840. return 0;
  841. }
  842. struct bb_miiphy_bus bb_miiphy_buses[] = {
  843. {
  844. .name = "sh_eth",
  845. .init = sh_eth_bb_init,
  846. .mdio_active = sh_eth_bb_mdio_active,
  847. .mdio_tristate = sh_eth_bb_mdio_tristate,
  848. .set_mdio = sh_eth_bb_set_mdio,
  849. .get_mdio = sh_eth_bb_get_mdio,
  850. .set_mdc = sh_eth_bb_set_mdc,
  851. .delay = sh_eth_bb_delay,
  852. }
  853. };
  854. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);