pic32_eth.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  4. *
  5. */
  6. #ifndef __MICROCHIP_PIC32_ETH_H_
  7. #define __MICROCHIP_PIC32_ETH_H_
  8. #include <linux/bitops.h>
  9. #include <mach/pic32.h>
  10. /* Ethernet */
  11. struct pic32_ectl_regs {
  12. struct pic32_reg_atomic con1; /* 0x00 */
  13. struct pic32_reg_atomic con2; /* 0x10 */
  14. struct pic32_reg_atomic txst; /* 0x20 */
  15. struct pic32_reg_atomic rxst; /* 0x30 */
  16. struct pic32_reg_atomic ht0; /* 0x40 */
  17. struct pic32_reg_atomic ht1; /* 0x50 */
  18. struct pic32_reg_atomic pmm0; /* 0x60 */
  19. struct pic32_reg_atomic pmm1; /* 0x70 */
  20. struct pic32_reg_atomic pmcs; /* 0x80 */
  21. struct pic32_reg_atomic pmo; /* 0x90 */
  22. struct pic32_reg_atomic rxfc; /* 0xa0 */
  23. struct pic32_reg_atomic rxwm; /* 0xb0 */
  24. struct pic32_reg_atomic ien; /* 0xc0 */
  25. struct pic32_reg_atomic irq; /* 0xd0 */
  26. struct pic32_reg_atomic stat; /* 0xe0 */
  27. };
  28. struct pic32_mii_regs {
  29. struct pic32_reg_atomic mcfg; /* 0x280 */
  30. struct pic32_reg_atomic mcmd; /* 0x290 */
  31. struct pic32_reg_atomic madr; /* 0x2a0 */
  32. struct pic32_reg_atomic mwtd; /* 0x2b0 */
  33. struct pic32_reg_atomic mrdd; /* 0x2c0 */
  34. struct pic32_reg_atomic mind; /* 0x2d0 */
  35. };
  36. struct pic32_emac_regs {
  37. struct pic32_reg_atomic cfg1; /* 0x200*/
  38. struct pic32_reg_atomic cfg2; /* 0x210*/
  39. struct pic32_reg_atomic ipgt; /* 0x220*/
  40. struct pic32_reg_atomic ipgr; /* 0x230*/
  41. struct pic32_reg_atomic clrt; /* 0x240*/
  42. struct pic32_reg_atomic maxf; /* 0x250*/
  43. struct pic32_reg_atomic supp; /* 0x260*/
  44. struct pic32_reg_atomic test; /* 0x270*/
  45. struct pic32_mii_regs mii; /* 0x280 - 0x2d0 */
  46. struct pic32_reg_atomic res1; /* 0x2e0 */
  47. struct pic32_reg_atomic res2; /* 0x2f0 */
  48. struct pic32_reg_atomic sa0; /* 0x300 */
  49. struct pic32_reg_atomic sa1; /* 0x310 */
  50. struct pic32_reg_atomic sa2; /* 0x320 */
  51. };
  52. /* ETHCON1 Reg field */
  53. #define ETHCON_BUFCDEC BIT(0)
  54. #define ETHCON_RXEN BIT(8)
  55. #define ETHCON_TXRTS BIT(9)
  56. #define ETHCON_ON BIT(15)
  57. /* ETHCON2 Reg field */
  58. #define ETHCON_RXBUFSZ 0x7f
  59. #define ETHCON_RXBUFSZ_SHFT 0x4
  60. /* ETHSTAT Reg field */
  61. #define ETHSTAT_BUSY BIT(7)
  62. #define ETHSTAT_BUFCNT 0x00ff0000
  63. /* ETHRXFC Register fields */
  64. #define ETHRXFC_BCEN BIT(0)
  65. #define ETHRXFC_MCEN BIT(1)
  66. #define ETHRXFC_UCEN BIT(3)
  67. #define ETHRXFC_RUNTEN BIT(4)
  68. #define ETHRXFC_CRCOKEN BIT(5)
  69. /* EMAC1CFG1 register offset */
  70. #define PIC32_EMAC1CFG1 0x0200
  71. /* EMAC1CFG1 register fields */
  72. #define EMAC_RXENABLE BIT(0)
  73. #define EMAC_RXPAUSE BIT(2)
  74. #define EMAC_TXPAUSE BIT(3)
  75. #define EMAC_SOFTRESET BIT(15)
  76. /* EMAC1CFG2 register fields */
  77. #define EMAC_FULLDUP BIT(0)
  78. #define EMAC_LENGTHCK BIT(1)
  79. #define EMAC_CRCENABLE BIT(4)
  80. #define EMAC_PADENABLE BIT(5)
  81. #define EMAC_AUTOPAD BIT(7)
  82. #define EMAC_EXCESS BIT(14)
  83. /* EMAC1IPGT register magic */
  84. #define FULLDUP_GAP_TIME 0x15
  85. #define HALFDUP_GAP_TIME 0x12
  86. /* EMAC1SUPP register fields */
  87. #define EMAC_RMII_SPD100 BIT(8)
  88. #define EMAC_RMII_RESET BIT(11)
  89. /* MII Management Configuration Register */
  90. #define MIIMCFG_RSTMGMT BIT(15)
  91. #define MIIMCFG_CLKSEL_DIV40 0x0020 /* 100Mhz / 40 */
  92. /* MII Management Command Register */
  93. #define MIIMCMD_READ BIT(0)
  94. #define MIIMCMD_SCAN BIT(1)
  95. /* MII Management Address Register */
  96. #define MIIMADD_REGADDR 0x1f
  97. #define MIIMADD_REGADDR_SHIFT 0
  98. #define MIIMADD_PHYADDR_SHIFT 8
  99. /* MII Management Indicator Register */
  100. #define MIIMIND_BUSY BIT(0)
  101. #define MIIMIND_NOTVALID BIT(2)
  102. #define MIIMIND_LINKFAIL BIT(3)
  103. /* Packet Descriptor */
  104. /* Received Packet Status */
  105. #define _RSV1_PKT_CSUM 0xffff
  106. #define _RSV2_CRC_ERR BIT(20)
  107. #define _RSV2_LEN_ERR BIT(21)
  108. #define _RSV2_RX_OK BIT(23)
  109. #define _RSV2_RX_COUNT 0xffff
  110. #define RSV_RX_CSUM(__rsv1) ((__rsv1) & _RSV1_PKT_CSUM)
  111. #define RSV_RX_COUNT(__rsv2) ((__rsv2) & _RSV2_RX_COUNT)
  112. #define RSV_RX_OK(__rsv2) ((__rsv2) & _RSV2_RX_OK)
  113. #define RSV_CRC_ERR(__rsv2) ((__rsv2) & _RSV2_CRC_ERR)
  114. /* Ethernet Hardware Descriptor Header bits */
  115. #define EDH_EOWN BIT(7)
  116. #define EDH_NPV BIT(8)
  117. #define EDH_STICKY BIT(9)
  118. #define _EDH_BCOUNT 0x07ff0000
  119. #define EDH_EOP BIT(30)
  120. #define EDH_SOP BIT(31)
  121. #define EDH_BCOUNT_SHIFT 16
  122. #define EDH_BCOUNT(len) ((len) << EDH_BCOUNT_SHIFT)
  123. /* Ethernet Hardware Descriptors
  124. * ref: PIC32 Family Reference Manual Table 35-7
  125. * This structure represents the layout of the DMA
  126. * memory shared between the CPU and the Ethernet
  127. * controller.
  128. */
  129. /* TX/RX DMA descriptor */
  130. struct eth_dma_desc {
  131. u32 hdr; /* header */
  132. u32 data_buff; /* data buffer address */
  133. u32 stat1; /* transmit/receive packet status */
  134. u32 stat2; /* transmit/receive packet status */
  135. u32 next_ed; /* next descriptor */
  136. };
  137. #define PIC32_MDIO_NAME "PIC32_EMAC"
  138. int pic32_mdio_init(const char *name, ulong ioaddr);
  139. #endif /* __MICROCHIP_PIC32_ETH_H_*/