realtek.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * RealTek PHY drivers
  4. *
  5. * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
  6. * author Andy Fleming
  7. * Copyright 2016 Karsten Merker <merker@debian.org>
  8. */
  9. #include <common.h>
  10. #include <linux/bitops.h>
  11. #include <phy.h>
  12. #include <linux/delay.h>
  13. #define PHY_RTL8211x_FORCE_MASTER BIT(1)
  14. #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
  15. #define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
  16. #define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4)
  17. #define PHY_AUTONEGOTIATE_TIMEOUT 5000
  18. /* RTL8211x 1000BASE-T Control Register */
  19. #define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
  20. #define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
  21. /* RTL8211x PHY Status Register */
  22. #define MIIM_RTL8211x_PHY_STATUS 0x11
  23. #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
  24. #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
  25. #define MIIM_RTL8211x_PHYSTAT_100 0x4000
  26. #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
  27. #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
  28. #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
  29. /* RTL8211x PHY Interrupt Enable Register */
  30. #define MIIM_RTL8211x_PHY_INER 0x12
  31. #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
  32. #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
  33. /* RTL8211x PHY Interrupt Status Register */
  34. #define MIIM_RTL8211x_PHY_INSR 0x13
  35. /* RTL8211F PHY Status Register */
  36. #define MIIM_RTL8211F_PHY_STATUS 0x1a
  37. #define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
  38. #define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
  39. #define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
  40. #define MIIM_RTL8211F_PHYSTAT_100 0x0010
  41. #define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
  42. #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
  43. #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
  44. #define MIIM_RTL8211E_CONFREG 0x1c
  45. #define MIIM_RTL8211E_CONFREG_TXD 0x0002
  46. #define MIIM_RTL8211E_CONFREG_RXD 0x0004
  47. #define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
  48. #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
  49. #define MIIM_RTL8211F_PAGE_SELECT 0x1f
  50. #define MIIM_RTL8211F_TX_DELAY 0x100
  51. #define MIIM_RTL8211F_RX_DELAY 0x8
  52. #define MIIM_RTL8211F_LCR 0x10
  53. #define RTL8201F_RMSR 0x10
  54. #define RMSR_RX_TIMING_SHIFT BIT(2)
  55. #define RMSR_RX_TIMING_MASK GENMASK(7, 4)
  56. #define RMSR_RX_TIMING_VAL 0x4
  57. #define RMSR_TX_TIMING_SHIFT BIT(3)
  58. #define RMSR_TX_TIMING_MASK GENMASK(11, 8)
  59. #define RMSR_TX_TIMING_VAL 0x5
  60. static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
  61. int devaddr, int regnum)
  62. {
  63. int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
  64. MIIM_RTL8211F_PAGE_SELECT);
  65. int val;
  66. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
  67. val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
  68. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
  69. return val;
  70. }
  71. static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
  72. int devaddr, int regnum, u16 val)
  73. {
  74. int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
  75. MIIM_RTL8211F_PAGE_SELECT);
  76. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
  77. phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
  78. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
  79. return 0;
  80. }
  81. static int rtl8211b_probe(struct phy_device *phydev)
  82. {
  83. #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
  84. phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
  85. #endif
  86. return 0;
  87. }
  88. static int rtl8211e_probe(struct phy_device *phydev)
  89. {
  90. #ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
  91. phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
  92. #endif
  93. return 0;
  94. }
  95. static int rtl8211f_probe(struct phy_device *phydev)
  96. {
  97. #ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
  98. phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
  99. #endif
  100. return 0;
  101. }
  102. static int rtl8210f_probe(struct phy_device *phydev)
  103. {
  104. #ifdef CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS
  105. phydev->flags |= PHY_RTL8201F_S700_RMII_TIMINGS;
  106. #endif
  107. return 0;
  108. }
  109. /* RealTek RTL8211x */
  110. static int rtl8211x_config(struct phy_device *phydev)
  111. {
  112. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  113. /* mask interrupt at init; if the interrupt is
  114. * needed indeed, it should be explicitly enabled
  115. */
  116. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
  117. MIIM_RTL8211x_PHY_INTR_DIS);
  118. if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
  119. unsigned int reg;
  120. reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
  121. /* force manual master/slave configuration */
  122. reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
  123. /* force master mode */
  124. reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
  125. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
  126. }
  127. if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
  128. unsigned int reg;
  129. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
  130. 7);
  131. phy_write(phydev, MDIO_DEVAD_NONE,
  132. MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
  133. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
  134. /* Ensure both internal delays are turned off */
  135. reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
  136. /* Flip the magic undocumented bits */
  137. reg |= MIIM_RTL8211E_CONFREG_MAGIC;
  138. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
  139. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
  140. 0);
  141. }
  142. /* read interrupt status just to clear it */
  143. phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
  144. genphy_config_aneg(phydev);
  145. return 0;
  146. }
  147. /* RealTek RTL8201F */
  148. static int rtl8201f_config(struct phy_device *phydev)
  149. {
  150. unsigned int reg;
  151. if (phydev->flags & PHY_RTL8201F_S700_RMII_TIMINGS) {
  152. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
  153. 7);
  154. reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR);
  155. reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK);
  156. /* Set the needed Rx/Tx Timings for proper PHY operation */
  157. reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT)
  158. | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT);
  159. phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);
  160. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
  161. 0);
  162. }
  163. genphy_config_aneg(phydev);
  164. return 0;
  165. }
  166. static int rtl8211f_config(struct phy_device *phydev)
  167. {
  168. u16 reg;
  169. if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
  170. unsigned int reg;
  171. reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
  172. reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
  173. phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
  174. }
  175. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  176. phy_write(phydev, MDIO_DEVAD_NONE,
  177. MIIM_RTL8211F_PAGE_SELECT, 0xd08);
  178. reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
  179. /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
  180. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  181. phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
  182. reg |= MIIM_RTL8211F_TX_DELAY;
  183. else
  184. reg &= ~MIIM_RTL8211F_TX_DELAY;
  185. phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
  186. /* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
  187. reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
  188. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  189. phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  190. reg |= MIIM_RTL8211F_RX_DELAY;
  191. else
  192. reg &= ~MIIM_RTL8211F_RX_DELAY;
  193. phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
  194. /* restore to default page 0 */
  195. phy_write(phydev, MDIO_DEVAD_NONE,
  196. MIIM_RTL8211F_PAGE_SELECT, 0x0);
  197. /* Set green LED for Link, yellow LED for Active */
  198. phy_write(phydev, MDIO_DEVAD_NONE,
  199. MIIM_RTL8211F_PAGE_SELECT, 0xd04);
  200. phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
  201. phy_write(phydev, MDIO_DEVAD_NONE,
  202. MIIM_RTL8211F_PAGE_SELECT, 0x0);
  203. genphy_config_aneg(phydev);
  204. return 0;
  205. }
  206. static int rtl8211x_parse_status(struct phy_device *phydev)
  207. {
  208. unsigned int speed;
  209. unsigned int mii_reg;
  210. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
  211. if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
  212. int i = 0;
  213. /* in case of timeout ->link is cleared */
  214. phydev->link = 1;
  215. puts("Waiting for PHY realtime link");
  216. while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
  217. /* Timeout reached ? */
  218. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  219. puts(" TIMEOUT !\n");
  220. phydev->link = 0;
  221. break;
  222. }
  223. if ((i++ % 1000) == 0)
  224. putc('.');
  225. udelay(1000); /* 1 ms */
  226. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
  227. MIIM_RTL8211x_PHY_STATUS);
  228. }
  229. puts(" done\n");
  230. udelay(500000); /* another 500 ms (results in faster booting) */
  231. } else {
  232. if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
  233. phydev->link = 1;
  234. else
  235. phydev->link = 0;
  236. }
  237. if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
  238. phydev->duplex = DUPLEX_FULL;
  239. else
  240. phydev->duplex = DUPLEX_HALF;
  241. speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
  242. switch (speed) {
  243. case MIIM_RTL8211x_PHYSTAT_GBIT:
  244. phydev->speed = SPEED_1000;
  245. break;
  246. case MIIM_RTL8211x_PHYSTAT_100:
  247. phydev->speed = SPEED_100;
  248. break;
  249. default:
  250. phydev->speed = SPEED_10;
  251. }
  252. return 0;
  253. }
  254. static int rtl8211f_parse_status(struct phy_device *phydev)
  255. {
  256. unsigned int speed;
  257. unsigned int mii_reg;
  258. int i = 0;
  259. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
  260. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
  261. phydev->link = 1;
  262. while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
  263. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  264. puts(" TIMEOUT !\n");
  265. phydev->link = 0;
  266. break;
  267. }
  268. if ((i++ % 1000) == 0)
  269. putc('.');
  270. udelay(1000);
  271. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
  272. MIIM_RTL8211F_PHY_STATUS);
  273. }
  274. if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
  275. phydev->duplex = DUPLEX_FULL;
  276. else
  277. phydev->duplex = DUPLEX_HALF;
  278. speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
  279. switch (speed) {
  280. case MIIM_RTL8211F_PHYSTAT_GBIT:
  281. phydev->speed = SPEED_1000;
  282. break;
  283. case MIIM_RTL8211F_PHYSTAT_100:
  284. phydev->speed = SPEED_100;
  285. break;
  286. default:
  287. phydev->speed = SPEED_10;
  288. }
  289. return 0;
  290. }
  291. static int rtl8211x_startup(struct phy_device *phydev)
  292. {
  293. int ret;
  294. /* Read the Status (2x to make sure link is right) */
  295. ret = genphy_update_link(phydev);
  296. if (ret)
  297. return ret;
  298. return rtl8211x_parse_status(phydev);
  299. }
  300. static int rtl8211e_startup(struct phy_device *phydev)
  301. {
  302. int ret;
  303. ret = genphy_update_link(phydev);
  304. if (ret)
  305. return ret;
  306. return genphy_parse_link(phydev);
  307. }
  308. static int rtl8211f_startup(struct phy_device *phydev)
  309. {
  310. int ret;
  311. /* Read the Status (2x to make sure link is right) */
  312. ret = genphy_update_link(phydev);
  313. if (ret)
  314. return ret;
  315. /* Read the Status (2x to make sure link is right) */
  316. return rtl8211f_parse_status(phydev);
  317. }
  318. /* Support for RTL8211B PHY */
  319. static struct phy_driver RTL8211B_driver = {
  320. .name = "RealTek RTL8211B",
  321. .uid = 0x1cc912,
  322. .mask = 0xffffff,
  323. .features = PHY_GBIT_FEATURES,
  324. .probe = &rtl8211b_probe,
  325. .config = &rtl8211x_config,
  326. .startup = &rtl8211x_startup,
  327. .shutdown = &genphy_shutdown,
  328. };
  329. /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
  330. static struct phy_driver RTL8211E_driver = {
  331. .name = "RealTek RTL8211E",
  332. .uid = 0x1cc915,
  333. .mask = 0xffffff,
  334. .features = PHY_GBIT_FEATURES,
  335. .probe = &rtl8211e_probe,
  336. .config = &rtl8211x_config,
  337. .startup = &rtl8211e_startup,
  338. .shutdown = &genphy_shutdown,
  339. };
  340. /* Support for RTL8211DN PHY */
  341. static struct phy_driver RTL8211DN_driver = {
  342. .name = "RealTek RTL8211DN",
  343. .uid = 0x1cc914,
  344. .mask = 0xffffff,
  345. .features = PHY_GBIT_FEATURES,
  346. .config = &rtl8211x_config,
  347. .startup = &rtl8211x_startup,
  348. .shutdown = &genphy_shutdown,
  349. };
  350. /* Support for RTL8211F PHY */
  351. static struct phy_driver RTL8211F_driver = {
  352. .name = "RealTek RTL8211F",
  353. .uid = 0x1cc916,
  354. .mask = 0xffffff,
  355. .features = PHY_GBIT_FEATURES,
  356. .probe = &rtl8211f_probe,
  357. .config = &rtl8211f_config,
  358. .startup = &rtl8211f_startup,
  359. .shutdown = &genphy_shutdown,
  360. .readext = &rtl8211f_phy_extread,
  361. .writeext = &rtl8211f_phy_extwrite,
  362. };
  363. /* Support for RTL8201F PHY */
  364. static struct phy_driver RTL8201F_driver = {
  365. .name = "RealTek RTL8201F 10/100Mbps Ethernet",
  366. .uid = 0x1cc816,
  367. .mask = 0xffffff,
  368. .features = PHY_BASIC_FEATURES,
  369. .probe = &rtl8210f_probe,
  370. .config = &rtl8201f_config,
  371. .startup = &rtl8211e_startup,
  372. .shutdown = &genphy_shutdown,
  373. };
  374. int phy_realtek_init(void)
  375. {
  376. phy_register(&RTL8211B_driver);
  377. phy_register(&RTL8211E_driver);
  378. phy_register(&RTL8211F_driver);
  379. phy_register(&RTL8211DN_driver);
  380. phy_register(&RTL8201F_driver);
  381. return 0;
  382. }