miiphybb.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 Industrie Dial Face S.p.A.
  4. * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
  5. *
  6. * (C) Copyright 2001
  7. * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  8. */
  9. /*
  10. * This provides a bit-banged interface to the ethernet MII management
  11. * channel.
  12. */
  13. #include <common.h>
  14. #include <ioports.h>
  15. #include <ppc_asm.tmpl>
  16. #include <miiphy.h>
  17. #include <asm/global_data.h>
  18. #define BB_MII_RELOCATE(v,off) (v += (v?off:0))
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #ifndef CONFIG_BITBANGMII_MULTI
  21. /*
  22. * If CONFIG_BITBANGMII_MULTI is not defined we use a
  23. * compatibility layer with the previous miiphybb implementation
  24. * based on macros usage.
  25. *
  26. */
  27. static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
  28. {
  29. #ifdef MII_INIT
  30. MII_INIT;
  31. #endif
  32. return 0;
  33. }
  34. static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
  35. {
  36. #ifdef MDIO_DECLARE
  37. MDIO_DECLARE;
  38. #endif
  39. MDIO_ACTIVE;
  40. return 0;
  41. }
  42. static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
  43. {
  44. #ifdef MDIO_DECLARE
  45. MDIO_DECLARE;
  46. #endif
  47. MDIO_TRISTATE;
  48. return 0;
  49. }
  50. static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
  51. {
  52. #ifdef MDIO_DECLARE
  53. MDIO_DECLARE;
  54. #endif
  55. MDIO(v);
  56. return 0;
  57. }
  58. static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
  59. {
  60. #ifdef MDIO_DECLARE
  61. MDIO_DECLARE;
  62. #endif
  63. *v = MDIO_READ;
  64. return 0;
  65. }
  66. static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
  67. {
  68. #ifdef MDC_DECLARE
  69. MDC_DECLARE;
  70. #endif
  71. MDC(v);
  72. return 0;
  73. }
  74. static int bb_delay_wrap(struct bb_miiphy_bus *bus)
  75. {
  76. MIIDELAY;
  77. return 0;
  78. }
  79. struct bb_miiphy_bus bb_miiphy_buses[] = {
  80. {
  81. .name = BB_MII_DEVNAME,
  82. .init = bb_mii_init_wrap,
  83. .mdio_active = bb_mdio_active_wrap,
  84. .mdio_tristate = bb_mdio_tristate_wrap,
  85. .set_mdio = bb_set_mdio_wrap,
  86. .get_mdio = bb_get_mdio_wrap,
  87. .set_mdc = bb_set_mdc_wrap,
  88. .delay = bb_delay_wrap,
  89. }
  90. };
  91. int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
  92. sizeof(bb_miiphy_buses[0]);
  93. #endif
  94. int bb_miiphy_init(void)
  95. {
  96. int i;
  97. for (i = 0; i < bb_miiphy_buses_num; i++) {
  98. #if defined(CONFIG_NEEDS_MANUAL_RELOC)
  99. /* Relocate the hook pointers*/
  100. BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
  101. BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
  102. BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
  103. BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
  104. BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
  105. BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
  106. BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
  107. #endif
  108. if (bb_miiphy_buses[i].init != NULL) {
  109. bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
  110. }
  111. }
  112. return 0;
  113. }
  114. static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
  115. {
  116. #ifdef CONFIG_BITBANGMII_MULTI
  117. int i;
  118. /* Search the correct bus */
  119. for (i = 0; i < bb_miiphy_buses_num; i++) {
  120. if (!strcmp(bb_miiphy_buses[i].name, devname)) {
  121. return &bb_miiphy_buses[i];
  122. }
  123. }
  124. return NULL;
  125. #else
  126. /* We have just one bitbanging bus */
  127. return &bb_miiphy_buses[0];
  128. #endif
  129. }
  130. /*****************************************************************************
  131. *
  132. * Utility to send the preamble, address, and register (common to read
  133. * and write).
  134. */
  135. static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
  136. unsigned char addr, unsigned char reg)
  137. {
  138. int j;
  139. /*
  140. * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
  141. * The IEEE spec says this is a PHY optional requirement. The AMD
  142. * 79C874 requires one after power up and one after a MII communications
  143. * error. This means that we are doing more preambles than we need,
  144. * but it is safer and will be much more robust.
  145. */
  146. bus->mdio_active(bus);
  147. bus->set_mdio(bus, 1);
  148. for (j = 0; j < 32; j++) {
  149. bus->set_mdc(bus, 0);
  150. bus->delay(bus);
  151. bus->set_mdc(bus, 1);
  152. bus->delay(bus);
  153. }
  154. /* send the start bit (01) and the read opcode (10) or write (10) */
  155. bus->set_mdc(bus, 0);
  156. bus->set_mdio(bus, 0);
  157. bus->delay(bus);
  158. bus->set_mdc(bus, 1);
  159. bus->delay(bus);
  160. bus->set_mdc(bus, 0);
  161. bus->set_mdio(bus, 1);
  162. bus->delay(bus);
  163. bus->set_mdc(bus, 1);
  164. bus->delay(bus);
  165. bus->set_mdc(bus, 0);
  166. bus->set_mdio(bus, read);
  167. bus->delay(bus);
  168. bus->set_mdc(bus, 1);
  169. bus->delay(bus);
  170. bus->set_mdc(bus, 0);
  171. bus->set_mdio(bus, !read);
  172. bus->delay(bus);
  173. bus->set_mdc(bus, 1);
  174. bus->delay(bus);
  175. /* send the PHY address */
  176. for (j = 0; j < 5; j++) {
  177. bus->set_mdc(bus, 0);
  178. if ((addr & 0x10) == 0) {
  179. bus->set_mdio(bus, 0);
  180. } else {
  181. bus->set_mdio(bus, 1);
  182. }
  183. bus->delay(bus);
  184. bus->set_mdc(bus, 1);
  185. bus->delay(bus);
  186. addr <<= 1;
  187. }
  188. /* send the register address */
  189. for (j = 0; j < 5; j++) {
  190. bus->set_mdc(bus, 0);
  191. if ((reg & 0x10) == 0) {
  192. bus->set_mdio(bus, 0);
  193. } else {
  194. bus->set_mdio(bus, 1);
  195. }
  196. bus->delay(bus);
  197. bus->set_mdc(bus, 1);
  198. bus->delay(bus);
  199. reg <<= 1;
  200. }
  201. }
  202. /*****************************************************************************
  203. *
  204. * Read a MII PHY register.
  205. *
  206. * Returns:
  207. * 0 on success
  208. */
  209. int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
  210. {
  211. unsigned short rdreg; /* register working value */
  212. int v;
  213. int j; /* counter */
  214. struct bb_miiphy_bus *bus;
  215. bus = bb_miiphy_getbus(miidev->name);
  216. if (bus == NULL) {
  217. return -1;
  218. }
  219. miiphy_pre (bus, 1, addr, reg);
  220. /* tri-state our MDIO I/O pin so we can read */
  221. bus->set_mdc(bus, 0);
  222. bus->mdio_tristate(bus);
  223. bus->delay(bus);
  224. bus->set_mdc(bus, 1);
  225. bus->delay(bus);
  226. /* check the turnaround bit: the PHY should be driving it to zero */
  227. bus->get_mdio(bus, &v);
  228. if (v != 0) {
  229. /* puts ("PHY didn't drive TA low\n"); */
  230. for (j = 0; j < 32; j++) {
  231. bus->set_mdc(bus, 0);
  232. bus->delay(bus);
  233. bus->set_mdc(bus, 1);
  234. bus->delay(bus);
  235. }
  236. /* There is no PHY, return */
  237. return -1;
  238. }
  239. bus->set_mdc(bus, 0);
  240. bus->delay(bus);
  241. /* read 16 bits of register data, MSB first */
  242. rdreg = 0;
  243. for (j = 0; j < 16; j++) {
  244. bus->set_mdc(bus, 1);
  245. bus->delay(bus);
  246. rdreg <<= 1;
  247. bus->get_mdio(bus, &v);
  248. rdreg |= (v & 0x1);
  249. bus->set_mdc(bus, 0);
  250. bus->delay(bus);
  251. }
  252. bus->set_mdc(bus, 1);
  253. bus->delay(bus);
  254. bus->set_mdc(bus, 0);
  255. bus->delay(bus);
  256. bus->set_mdc(bus, 1);
  257. bus->delay(bus);
  258. #ifdef DEBUG
  259. printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg);
  260. #endif
  261. return rdreg;
  262. }
  263. /*****************************************************************************
  264. *
  265. * Write a MII PHY register.
  266. *
  267. * Returns:
  268. * 0 on success
  269. */
  270. int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
  271. u16 value)
  272. {
  273. struct bb_miiphy_bus *bus;
  274. int j; /* counter */
  275. bus = bb_miiphy_getbus(miidev->name);
  276. if (bus == NULL) {
  277. /* Bus not found! */
  278. return -1;
  279. }
  280. miiphy_pre (bus, 0, addr, reg);
  281. /* send the turnaround (10) */
  282. bus->set_mdc(bus, 0);
  283. bus->set_mdio(bus, 1);
  284. bus->delay(bus);
  285. bus->set_mdc(bus, 1);
  286. bus->delay(bus);
  287. bus->set_mdc(bus, 0);
  288. bus->set_mdio(bus, 0);
  289. bus->delay(bus);
  290. bus->set_mdc(bus, 1);
  291. bus->delay(bus);
  292. /* write 16 bits of register data, MSB first */
  293. for (j = 0; j < 16; j++) {
  294. bus->set_mdc(bus, 0);
  295. if ((value & 0x00008000) == 0) {
  296. bus->set_mdio(bus, 0);
  297. } else {
  298. bus->set_mdio(bus, 1);
  299. }
  300. bus->delay(bus);
  301. bus->set_mdc(bus, 1);
  302. bus->delay(bus);
  303. value <<= 1;
  304. }
  305. /*
  306. * Tri-state the MDIO line.
  307. */
  308. bus->mdio_tristate(bus);
  309. bus->set_mdc(bus, 0);
  310. bus->delay(bus);
  311. bus->set_mdc(bus, 1);
  312. bus->delay(bus);
  313. return 0;
  314. }