micrel_ksz90x1.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Micrel PHY drivers
  4. *
  5. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  6. * author Andy Fleming
  7. * (C) 2012 NetModule AG, David Andrey, added KSZ9031
  8. * (C) Copyright 2017 Adaptrum, Inc.
  9. * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <env.h>
  14. #include <errno.h>
  15. #include <micrel.h>
  16. #include <phy.h>
  17. /*
  18. * KSZ9021 - KSZ9031 common
  19. */
  20. #define MII_KSZ90xx_PHY_CTL 0x1f
  21. #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
  22. #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
  23. #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
  24. #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
  25. /* KSZ9021 PHY Registers */
  26. #define MII_KSZ9021_EXTENDED_CTRL 0x0b
  27. #define MII_KSZ9021_EXTENDED_DATAW 0x0c
  28. #define MII_KSZ9021_EXTENDED_DATAR 0x0d
  29. #define CTRL1000_PREFER_MASTER (1 << 10)
  30. #define CTRL1000_CONFIG_MASTER (1 << 11)
  31. #define CTRL1000_MANUAL_CONFIG (1 << 12)
  32. #define KSZ9021_PS_TO_REG 120
  33. /* KSZ9031 PHY Registers */
  34. #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
  35. #define MII_KSZ9031_MMD_REG_DATA 0x0e
  36. #define KSZ9031_PS_TO_REG 60
  37. static int ksz90xx_startup(struct phy_device *phydev)
  38. {
  39. unsigned phy_ctl;
  40. int ret;
  41. ret = genphy_update_link(phydev);
  42. if (ret)
  43. return ret;
  44. phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
  45. if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
  46. phydev->duplex = DUPLEX_FULL;
  47. else
  48. phydev->duplex = DUPLEX_HALF;
  49. if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
  50. phydev->speed = SPEED_1000;
  51. else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
  52. phydev->speed = SPEED_100;
  53. else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
  54. phydev->speed = SPEED_10;
  55. return 0;
  56. }
  57. /* Common OF config bits for KSZ9021 and KSZ9031 */
  58. #ifdef CONFIG_DM_ETH
  59. struct ksz90x1_reg_field {
  60. const char *name;
  61. const u8 size; /* Size of the bitfield, in bits */
  62. const u8 off; /* Offset from bit 0 */
  63. const u8 dflt; /* Default value */
  64. };
  65. struct ksz90x1_ofcfg {
  66. const u16 reg;
  67. const u16 devad;
  68. const struct ksz90x1_reg_field *grp;
  69. const u16 grpsz;
  70. };
  71. static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
  72. { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
  73. { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
  74. };
  75. static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
  76. { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
  77. { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
  78. };
  79. static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
  80. { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
  81. { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
  82. };
  83. static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
  84. { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
  85. };
  86. static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
  87. { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
  88. };
  89. static int ksz90x1_of_config_group(struct phy_device *phydev,
  90. struct ksz90x1_ofcfg *ofcfg,
  91. int ps_to_regval)
  92. {
  93. struct udevice *dev = phydev->dev;
  94. struct phy_driver *drv = phydev->drv;
  95. int val[4];
  96. int i, changed = 0, offset, max;
  97. u16 regval = 0;
  98. ofnode node;
  99. if (!drv || !drv->writeext)
  100. return -EOPNOTSUPP;
  101. node = phydev->node;
  102. if (!ofnode_valid(node)) {
  103. /* Look for a PHY node under the Ethernet node */
  104. node = dev_read_subnode(dev, "ethernet-phy");
  105. }
  106. if (!ofnode_valid(node)) {
  107. /* No node found, look in the Ethernet node */
  108. node = dev_ofnode(dev);
  109. }
  110. for (i = 0; i < ofcfg->grpsz; i++) {
  111. val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0);
  112. offset = ofcfg->grp[i].off;
  113. if (val[i] == -1) {
  114. /* Default register value for KSZ9021 */
  115. regval |= ofcfg->grp[i].dflt << offset;
  116. } else {
  117. changed = 1; /* Value was changed in OF */
  118. /* Calculate the register value and fix corner cases */
  119. max = (1 << ofcfg->grp[i].size) - 1;
  120. if (val[i] > ps_to_regval * max) {
  121. regval |= max << offset;
  122. } else {
  123. regval |= (val[i] / ps_to_regval) << offset;
  124. }
  125. }
  126. }
  127. if (!changed)
  128. return 0;
  129. return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
  130. }
  131. static int ksz9021_of_config(struct phy_device *phydev)
  132. {
  133. struct ksz90x1_ofcfg ofcfg[] = {
  134. { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
  135. { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
  136. { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
  137. };
  138. int i, ret = 0;
  139. for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
  140. ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
  141. KSZ9021_PS_TO_REG);
  142. if (ret)
  143. return ret;
  144. }
  145. return 0;
  146. }
  147. static int ksz9031_of_config(struct phy_device *phydev)
  148. {
  149. struct ksz90x1_ofcfg ofcfg[] = {
  150. { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
  151. { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
  152. { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
  153. { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
  154. };
  155. int i, ret = 0;
  156. for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
  157. ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
  158. KSZ9031_PS_TO_REG);
  159. if (ret)
  160. return ret;
  161. }
  162. return 0;
  163. }
  164. static int ksz9031_center_flp_timing(struct phy_device *phydev)
  165. {
  166. struct phy_driver *drv = phydev->drv;
  167. int ret = 0;
  168. if (!drv || !drv->writeext)
  169. return -EOPNOTSUPP;
  170. ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
  171. if (ret)
  172. return ret;
  173. ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
  174. return ret;
  175. }
  176. #else /* !CONFIG_DM_ETH */
  177. static int ksz9021_of_config(struct phy_device *phydev)
  178. {
  179. return 0;
  180. }
  181. static int ksz9031_of_config(struct phy_device *phydev)
  182. {
  183. return 0;
  184. }
  185. static int ksz9031_center_flp_timing(struct phy_device *phydev)
  186. {
  187. return 0;
  188. }
  189. #endif
  190. /*
  191. * KSZ9021
  192. */
  193. int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
  194. {
  195. /* extended registers */
  196. phy_write(phydev, MDIO_DEVAD_NONE,
  197. MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
  198. return phy_write(phydev, MDIO_DEVAD_NONE,
  199. MII_KSZ9021_EXTENDED_DATAW, val);
  200. }
  201. int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
  202. {
  203. /* extended registers */
  204. phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
  205. return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
  206. }
  207. static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
  208. int regnum)
  209. {
  210. return ksz9021_phy_extended_read(phydev, regnum);
  211. }
  212. static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
  213. int devaddr, int regnum, u16 val)
  214. {
  215. return ksz9021_phy_extended_write(phydev, regnum, val);
  216. }
  217. static int ksz9021_config(struct phy_device *phydev)
  218. {
  219. unsigned ctrl1000 = 0;
  220. const unsigned master = CTRL1000_PREFER_MASTER |
  221. CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
  222. unsigned features = phydev->drv->features;
  223. int ret;
  224. ret = ksz9021_of_config(phydev);
  225. if (ret)
  226. return ret;
  227. if (env_get("disable_giga"))
  228. features &= ~(SUPPORTED_1000baseT_Half |
  229. SUPPORTED_1000baseT_Full);
  230. /* force master mode for 1000BaseT due to chip errata */
  231. if (features & SUPPORTED_1000baseT_Half)
  232. ctrl1000 |= ADVERTISE_1000HALF | master;
  233. if (features & SUPPORTED_1000baseT_Full)
  234. ctrl1000 |= ADVERTISE_1000FULL | master;
  235. phydev->advertising = features;
  236. phydev->supported = features;
  237. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
  238. genphy_config_aneg(phydev);
  239. genphy_restart_aneg(phydev);
  240. return 0;
  241. }
  242. static struct phy_driver ksz9021_driver = {
  243. .name = "Micrel ksz9021",
  244. .uid = 0x221610,
  245. .mask = 0xfffffe,
  246. .features = PHY_GBIT_FEATURES,
  247. .config = &ksz9021_config,
  248. .startup = &ksz90xx_startup,
  249. .shutdown = &genphy_shutdown,
  250. .writeext = &ksz9021_phy_extwrite,
  251. .readext = &ksz9021_phy_extread,
  252. };
  253. /*
  254. * KSZ9031
  255. */
  256. int ksz9031_phy_extended_write(struct phy_device *phydev,
  257. int devaddr, int regnum, u16 mode, u16 val)
  258. {
  259. /*select register addr for mmd*/
  260. phy_write(phydev, MDIO_DEVAD_NONE,
  261. MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
  262. /*select register for mmd*/
  263. phy_write(phydev, MDIO_DEVAD_NONE,
  264. MII_KSZ9031_MMD_REG_DATA, regnum);
  265. /*setup mode*/
  266. phy_write(phydev, MDIO_DEVAD_NONE,
  267. MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
  268. /*write the value*/
  269. return phy_write(phydev, MDIO_DEVAD_NONE,
  270. MII_KSZ9031_MMD_REG_DATA, val);
  271. }
  272. int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
  273. int regnum, u16 mode)
  274. {
  275. phy_write(phydev, MDIO_DEVAD_NONE,
  276. MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
  277. phy_write(phydev, MDIO_DEVAD_NONE,
  278. MII_KSZ9031_MMD_REG_DATA, regnum);
  279. phy_write(phydev, MDIO_DEVAD_NONE,
  280. MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
  281. return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
  282. }
  283. static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
  284. int regnum)
  285. {
  286. return ksz9031_phy_extended_read(phydev, devaddr, regnum,
  287. MII_KSZ9031_MOD_DATA_NO_POST_INC);
  288. }
  289. static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
  290. int devaddr, int regnum, u16 val)
  291. {
  292. return ksz9031_phy_extended_write(phydev, devaddr, regnum,
  293. MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
  294. }
  295. static int ksz9031_config(struct phy_device *phydev)
  296. {
  297. int ret;
  298. ret = ksz9031_of_config(phydev);
  299. if (ret)
  300. return ret;
  301. ret = ksz9031_center_flp_timing(phydev);
  302. if (ret)
  303. return ret;
  304. /* add an option to disable the gigabit feature of this PHY */
  305. if (env_get("disable_giga")) {
  306. unsigned features;
  307. unsigned bmcr;
  308. /* disable speed 1000 in features supported by the PHY */
  309. features = phydev->drv->features;
  310. features &= ~(SUPPORTED_1000baseT_Half |
  311. SUPPORTED_1000baseT_Full);
  312. phydev->advertising = phydev->supported = features;
  313. /* disable speed 1000 in Basic Control Register */
  314. bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  315. bmcr &= ~(1 << 6);
  316. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
  317. /* disable speed 1000 in 1000Base-T Control Register */
  318. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
  319. /* start autoneg */
  320. genphy_config_aneg(phydev);
  321. genphy_restart_aneg(phydev);
  322. return 0;
  323. }
  324. return genphy_config(phydev);
  325. }
  326. static struct phy_driver ksz9031_driver = {
  327. .name = "Micrel ksz9031",
  328. .uid = PHY_ID_KSZ9031,
  329. .mask = MII_KSZ9x31_SILICON_REV_MASK,
  330. .features = PHY_GBIT_FEATURES,
  331. .config = &ksz9031_config,
  332. .startup = &ksz90xx_startup,
  333. .shutdown = &genphy_shutdown,
  334. .writeext = &ksz9031_phy_extwrite,
  335. .readext = &ksz9031_phy_extread,
  336. };
  337. /*
  338. * KSZ9131
  339. */
  340. #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
  341. #define KSZ9131RN_RXC_DLL_CTRL 76
  342. #define KSZ9131RN_TXC_DLL_CTRL 77
  343. #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
  344. #define KSZ9131RN_DLL_ENABLE_DELAY 0
  345. #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
  346. static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
  347. {
  348. struct phy_driver *drv = phydev->drv;
  349. u16 rxcdll_val, txcdll_val, val;
  350. int ret;
  351. switch (phydev->interface) {
  352. case PHY_INTERFACE_MODE_RGMII:
  353. rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  354. txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  355. break;
  356. case PHY_INTERFACE_MODE_RGMII_ID:
  357. rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  358. txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  359. break;
  360. case PHY_INTERFACE_MODE_RGMII_RXID:
  361. rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  362. txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  363. break;
  364. case PHY_INTERFACE_MODE_RGMII_TXID:
  365. rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  366. txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  367. break;
  368. default:
  369. return 0;
  370. }
  371. val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
  372. KSZ9131RN_RXC_DLL_CTRL);
  373. val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
  374. val |= rxcdll_val;
  375. ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
  376. KSZ9131RN_RXC_DLL_CTRL, val);
  377. if (ret)
  378. return ret;
  379. val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
  380. KSZ9131RN_TXC_DLL_CTRL);
  381. val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
  382. val |= txcdll_val;
  383. ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
  384. KSZ9131RN_TXC_DLL_CTRL, val);
  385. return ret;
  386. }
  387. static int ksz9131_config(struct phy_device *phydev)
  388. {
  389. int ret;
  390. if (phy_interface_is_rgmii(phydev)) {
  391. ret = ksz9131_config_rgmii_delay(phydev);
  392. if (ret)
  393. return ret;
  394. }
  395. /* add an option to disable the gigabit feature of this PHY */
  396. if (env_get("disable_giga")) {
  397. unsigned features;
  398. unsigned bmcr;
  399. /* disable speed 1000 in features supported by the PHY */
  400. features = phydev->drv->features;
  401. features &= ~(SUPPORTED_1000baseT_Half |
  402. SUPPORTED_1000baseT_Full);
  403. phydev->advertising = phydev->supported = features;
  404. /* disable speed 1000 in Basic Control Register */
  405. bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  406. bmcr &= ~(1 << 6);
  407. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
  408. /* disable speed 1000 in 1000Base-T Control Register */
  409. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
  410. /* start autoneg */
  411. genphy_config_aneg(phydev);
  412. genphy_restart_aneg(phydev);
  413. return 0;
  414. }
  415. return genphy_config(phydev);
  416. }
  417. static struct phy_driver ksz9131_driver = {
  418. .name = "Micrel ksz9131",
  419. .uid = PHY_ID_KSZ9131,
  420. .mask = MII_KSZ9x31_SILICON_REV_MASK,
  421. .features = PHY_GBIT_FEATURES,
  422. .config = &ksz9131_config,
  423. .startup = &ksz90xx_startup,
  424. .shutdown = &genphy_shutdown,
  425. .writeext = &ksz9031_phy_extwrite,
  426. .readext = &ksz9031_phy_extread,
  427. };
  428. int ksz9xx1_phy_get_id(struct phy_device *phydev)
  429. {
  430. unsigned int phyid;
  431. get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phyid);
  432. return phyid;
  433. }
  434. int phy_micrel_ksz90x1_init(void)
  435. {
  436. phy_register(&ksz9021_driver);
  437. phy_register(&ksz9031_driver);
  438. phy_register(&ksz9131_driver);
  439. return 0;
  440. }