marvell.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell PHY drivers
  4. *
  5. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  6. * author Andy Fleming
  7. */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <phy.h>
  11. #include <linux/bitops.h>
  12. #include <linux/delay.h>
  13. #define PHY_AUTONEGOTIATE_TIMEOUT 5000
  14. #define MII_MARVELL_PHY_PAGE 22
  15. /* 88E1011 PHY Status Register */
  16. #define MIIM_88E1xxx_PHY_STATUS 0x11
  17. #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
  18. #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
  19. #define MIIM_88E1xxx_PHYSTAT_100 0x4000
  20. #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
  21. #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
  22. #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
  23. #define MIIM_88E1xxx_PHY_SCR 0x10
  24. #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
  25. /* 88E1111 PHY LED Control Register */
  26. #define MIIM_88E1111_PHY_LED_CONTROL 24
  27. #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
  28. #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
  29. /* 88E1111 Extended PHY Specific Control Register */
  30. #define MIIM_88E1111_PHY_EXT_CR 0x14
  31. #define MIIM_88E1111_RX_DELAY 0x80
  32. #define MIIM_88E1111_TX_DELAY 0x2
  33. /* 88E1111 Extended PHY Specific Status Register */
  34. #define MIIM_88E1111_PHY_EXT_SR 0x1b
  35. #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
  36. #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
  37. #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
  38. #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
  39. #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
  40. #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
  41. #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
  42. #define MIIM_88E1111_COPPER 0
  43. #define MIIM_88E1111_FIBER 1
  44. /* 88E1118 PHY defines */
  45. #define MIIM_88E1118_PHY_PAGE 22
  46. #define MIIM_88E1118_PHY_LED_PAGE 3
  47. /* 88E1121 PHY LED Control Register */
  48. #define MIIM_88E1121_PHY_LED_CTRL 16
  49. #define MIIM_88E1121_PHY_LED_PAGE 3
  50. #define MIIM_88E1121_PHY_LED_DEF 0x0030
  51. /* 88E1121 PHY IRQ Enable/Status Register */
  52. #define MIIM_88E1121_PHY_IRQ_EN 18
  53. #define MIIM_88E1121_PHY_IRQ_STATUS 19
  54. #define MIIM_88E1121_PHY_PAGE 22
  55. /* 88E1145 Extended PHY Specific Control Register */
  56. #define MIIM_88E1145_PHY_EXT_CR 20
  57. #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
  58. #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
  59. #define MIIM_88E1145_PHY_LED_CONTROL 24
  60. #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
  61. #define MIIM_88E1145_PHY_PAGE 29
  62. #define MIIM_88E1145_PHY_CAL_OV 30
  63. #define MIIM_88E1149_PHY_PAGE 29
  64. /* 88E1310 PHY defines */
  65. #define MIIM_88E1310_PHY_LED_CTRL 16
  66. #define MIIM_88E1310_PHY_IRQ_EN 18
  67. #define MIIM_88E1310_PHY_RGMII_CTRL 21
  68. #define MIIM_88E1310_PHY_PAGE 22
  69. /* 88E151x PHY defines */
  70. /* Page 2 registers */
  71. #define MIIM_88E151x_PHY_MSCR 21
  72. #define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
  73. #define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
  74. #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
  75. /* Page 3 registers */
  76. #define MIIM_88E151x_LED_FUNC_CTRL 16
  77. #define MIIM_88E151x_LED_FLD_SZ 4
  78. #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
  79. #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
  80. #define MIIM_88E151x_LED0_ACT 3
  81. #define MIIM_88E151x_LED1_100_1000_LINK 6
  82. #define MIIM_88E151x_LED_TIMER_CTRL 18
  83. #define MIIM_88E151x_INT_EN_OFFS 7
  84. /* Page 18 registers */
  85. #define MIIM_88E151x_GENERAL_CTRL 20
  86. #define MIIM_88E151x_MODE_SGMII 1
  87. #define MIIM_88E151x_RESET_OFFS 15
  88. static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
  89. int devaddr, int regnum)
  90. {
  91. int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
  92. int val;
  93. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
  94. val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
  95. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
  96. return val;
  97. }
  98. static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
  99. int devaddr, int regnum, u16 val)
  100. {
  101. int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
  102. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
  103. phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
  104. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
  105. return 0;
  106. }
  107. /* Marvell 88E1011S */
  108. static int m88e1011s_config(struct phy_device *phydev)
  109. {
  110. /* Reset and configure the PHY */
  111. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  112. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  113. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
  114. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  117. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  118. genphy_config_aneg(phydev);
  119. return 0;
  120. }
  121. /* Parse the 88E1011's status register for speed and duplex
  122. * information
  123. */
  124. static int m88e1xxx_parse_status(struct phy_device *phydev)
  125. {
  126. unsigned int speed;
  127. unsigned int mii_reg;
  128. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
  129. if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
  130. !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
  131. int i = 0;
  132. puts("Waiting for PHY realtime link");
  133. while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
  134. /* Timeout reached ? */
  135. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  136. puts(" TIMEOUT !\n");
  137. phydev->link = 0;
  138. return -ETIMEDOUT;
  139. }
  140. if ((i++ % 1000) == 0)
  141. putc('.');
  142. udelay(1000);
  143. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
  144. MIIM_88E1xxx_PHY_STATUS);
  145. }
  146. puts(" done\n");
  147. mdelay(500); /* another 500 ms (results in faster booting) */
  148. } else {
  149. if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
  150. phydev->link = 1;
  151. else
  152. phydev->link = 0;
  153. }
  154. if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
  155. phydev->duplex = DUPLEX_FULL;
  156. else
  157. phydev->duplex = DUPLEX_HALF;
  158. speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
  159. switch (speed) {
  160. case MIIM_88E1xxx_PHYSTAT_GBIT:
  161. phydev->speed = SPEED_1000;
  162. break;
  163. case MIIM_88E1xxx_PHYSTAT_100:
  164. phydev->speed = SPEED_100;
  165. break;
  166. default:
  167. phydev->speed = SPEED_10;
  168. break;
  169. }
  170. return 0;
  171. }
  172. static int m88e1011s_startup(struct phy_device *phydev)
  173. {
  174. int ret;
  175. ret = genphy_update_link(phydev);
  176. if (ret)
  177. return ret;
  178. return m88e1xxx_parse_status(phydev);
  179. }
  180. /* Marvell 88E1111S */
  181. static int m88e1111s_config(struct phy_device *phydev)
  182. {
  183. int reg;
  184. if (phy_interface_is_rgmii(phydev)) {
  185. reg = phy_read(phydev,
  186. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
  187. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  188. (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
  189. reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
  190. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  191. reg &= ~MIIM_88E1111_TX_DELAY;
  192. reg |= MIIM_88E1111_RX_DELAY;
  193. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  194. reg &= ~MIIM_88E1111_RX_DELAY;
  195. reg |= MIIM_88E1111_TX_DELAY;
  196. }
  197. phy_write(phydev,
  198. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
  199. reg = phy_read(phydev,
  200. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
  201. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
  202. if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
  203. reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
  204. else
  205. reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
  206. phy_write(phydev,
  207. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
  208. }
  209. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  210. reg = phy_read(phydev,
  211. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
  212. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
  213. reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
  214. reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  215. phy_write(phydev, MDIO_DEVAD_NONE,
  216. MIIM_88E1111_PHY_EXT_SR, reg);
  217. }
  218. if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
  219. reg = phy_read(phydev,
  220. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
  221. reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
  222. phy_write(phydev,
  223. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
  224. reg = phy_read(phydev, MDIO_DEVAD_NONE,
  225. MIIM_88E1111_PHY_EXT_SR);
  226. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
  227. MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
  228. reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  229. phy_write(phydev, MDIO_DEVAD_NONE,
  230. MIIM_88E1111_PHY_EXT_SR, reg);
  231. /* soft reset */
  232. phy_reset(phydev);
  233. reg = phy_read(phydev, MDIO_DEVAD_NONE,
  234. MIIM_88E1111_PHY_EXT_SR);
  235. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
  236. MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
  237. reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
  238. MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  239. phy_write(phydev, MDIO_DEVAD_NONE,
  240. MIIM_88E1111_PHY_EXT_SR, reg);
  241. }
  242. /* soft reset */
  243. phy_reset(phydev);
  244. genphy_config_aneg(phydev);
  245. genphy_restart_aneg(phydev);
  246. return 0;
  247. }
  248. /**
  249. * m88e151x_phy_writebits - write bits to a register
  250. */
  251. void m88e151x_phy_writebits(struct phy_device *phydev,
  252. u8 reg_num, u16 offset, u16 len, u16 data)
  253. {
  254. u16 reg, mask;
  255. if ((len + offset) >= 16)
  256. mask = 0 - (1 << offset);
  257. else
  258. mask = (1 << (len + offset)) - (1 << offset);
  259. reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
  260. reg &= ~mask;
  261. reg |= data << offset;
  262. phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
  263. }
  264. static int m88e151x_config(struct phy_device *phydev)
  265. {
  266. u16 reg;
  267. /*
  268. * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
  269. * /88E1514 Rev A0, Errata Section 3.1
  270. */
  271. /* EEE initialization */
  272. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
  273. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
  274. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
  275. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
  276. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
  277. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
  278. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
  279. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
  280. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
  281. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  282. /* SGMII-to-Copper mode initialization */
  283. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  284. /* Select page 18 */
  285. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
  286. /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
  287. m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
  288. 0, 3, MIIM_88E151x_MODE_SGMII);
  289. /* PHY reset is necessary after changing MODE[2:0] */
  290. m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
  291. MIIM_88E151x_RESET_OFFS, 1, 1);
  292. /* Reset page selection */
  293. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
  294. udelay(100);
  295. }
  296. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  297. reg = phy_read(phydev, MDIO_DEVAD_NONE,
  298. MIIM_88E1111_PHY_EXT_SR);
  299. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
  300. reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
  301. reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  302. #if CONFIG_IS_ENABLED(FPGA_GMAC_SPEED10)
  303. reg &= ~((1 << 6) | (1 << 13));//10M
  304. #elif CONFIG_IS_ENABLED(FPGA_GMAC_SPEED100)
  305. reg |= (1 << 13);//100M
  306. #endif
  307. phy_write(phydev, MDIO_DEVAD_NONE,
  308. MIIM_88E1111_PHY_EXT_SR, reg);
  309. }
  310. if (phy_interface_is_rgmii(phydev)) {
  311. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
  312. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
  313. reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
  314. if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
  315. phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  316. reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
  317. else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  318. reg |= MIIM_88E151x_RGMII_RX_DELAY;
  319. else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
  320. reg |= MIIM_88E151x_RGMII_TX_DELAY;
  321. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
  322. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
  323. }
  324. /* soft reset */
  325. phy_reset(phydev);
  326. genphy_config_aneg(phydev);
  327. genphy_restart_aneg(phydev);
  328. return 0;
  329. }
  330. /* Marvell 88E1118 */
  331. static int m88e1118_config(struct phy_device *phydev)
  332. {
  333. /* Change Page Number */
  334. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
  335. /* Delay RGMII TX and RX */
  336. phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
  337. /* Change Page Number */
  338. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
  339. /* Adjust LED control */
  340. phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
  341. /* Change Page Number */
  342. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  343. return genphy_config_aneg(phydev);
  344. }
  345. static int m88e1118_startup(struct phy_device *phydev)
  346. {
  347. int ret;
  348. /* Change Page Number */
  349. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  350. ret = genphy_update_link(phydev);
  351. if (ret)
  352. return ret;
  353. return m88e1xxx_parse_status(phydev);
  354. }
  355. /* Marvell 88E1121R */
  356. static int m88e1121_config(struct phy_device *phydev)
  357. {
  358. int pg;
  359. /* Configure the PHY */
  360. genphy_config_aneg(phydev);
  361. /* Switch the page to access the led register */
  362. pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
  363. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
  364. MIIM_88E1121_PHY_LED_PAGE);
  365. /* Configure leds */
  366. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
  367. MIIM_88E1121_PHY_LED_DEF);
  368. /* Restore the page pointer */
  369. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
  370. /* Disable IRQs and de-assert interrupt */
  371. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
  372. phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
  373. return 0;
  374. }
  375. /* Marvell 88E1145 */
  376. static int m88e1145_config(struct phy_device *phydev)
  377. {
  378. int reg;
  379. /* Errata E0, E1 */
  380. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
  381. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
  382. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
  383. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
  384. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
  385. MIIM_88E1xxx_PHY_MDI_X_AUTO);
  386. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
  387. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  388. reg |= MIIM_M88E1145_RGMII_RX_DELAY |
  389. MIIM_M88E1145_RGMII_TX_DELAY;
  390. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
  391. genphy_config_aneg(phydev);
  392. /* soft reset */
  393. reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  394. reg |= BMCR_RESET;
  395. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
  396. return 0;
  397. }
  398. static int m88e1145_startup(struct phy_device *phydev)
  399. {
  400. int ret;
  401. ret = genphy_update_link(phydev);
  402. if (ret)
  403. return ret;
  404. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
  405. MIIM_88E1145_PHY_LED_DIRECT);
  406. return m88e1xxx_parse_status(phydev);
  407. }
  408. /* Marvell 88E1149S */
  409. static int m88e1149_config(struct phy_device *phydev)
  410. {
  411. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
  412. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
  413. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
  414. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
  415. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  416. genphy_config_aneg(phydev);
  417. phy_reset(phydev);
  418. return 0;
  419. }
  420. /* Marvell 88E1310 */
  421. static int m88e1310_config(struct phy_device *phydev)
  422. {
  423. u16 reg;
  424. /* LED link and activity */
  425. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
  426. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
  427. reg = (reg & ~0xf) | 0x1;
  428. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
  429. /* Set LED2/INT to INT mode, low active */
  430. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
  431. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
  432. reg = (reg & 0x77ff) | 0x0880;
  433. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
  434. /* Set RGMII delay */
  435. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
  436. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
  437. reg |= 0x0030;
  438. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
  439. /* Ensure to return to page 0 */
  440. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
  441. return genphy_config_aneg(phydev);
  442. }
  443. static int m88e1680_config(struct phy_device *phydev)
  444. {
  445. /*
  446. * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
  447. * Errata Section 4.1
  448. */
  449. u16 reg;
  450. int res;
  451. /* Matrix LED mode (not neede if single LED mode is used */
  452. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
  453. reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
  454. reg |= (1 << 5);
  455. phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
  456. /* QSGMII TX amplitude change */
  457. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
  458. phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
  459. phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
  460. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  461. /* EEE initialization */
  462. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
  463. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
  464. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
  465. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
  466. phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
  467. phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
  468. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  469. phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
  470. res = genphy_config_aneg(phydev);
  471. if (res < 0)
  472. return res;
  473. /* soft reset */
  474. reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  475. reg |= BMCR_RESET;
  476. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
  477. return 0;
  478. }
  479. static struct phy_driver M88E1011S_driver = {
  480. .name = "Marvell 88E1011S",
  481. .uid = 0x1410c60,
  482. .mask = 0xffffff0,
  483. .features = PHY_GBIT_FEATURES,
  484. .config = &m88e1011s_config,
  485. .startup = &m88e1011s_startup,
  486. .shutdown = &genphy_shutdown,
  487. };
  488. static struct phy_driver M88E1111S_driver = {
  489. .name = "Marvell 88E1111S",
  490. .uid = 0x1410cc0,
  491. .mask = 0xffffff0,
  492. .features = PHY_GBIT_FEATURES,
  493. .config = &m88e1111s_config,
  494. .startup = &m88e1011s_startup,
  495. .shutdown = &genphy_shutdown,
  496. };
  497. static struct phy_driver M88E1118_driver = {
  498. .name = "Marvell 88E1118",
  499. .uid = 0x1410e10,
  500. .mask = 0xffffff0,
  501. .features = PHY_GBIT_FEATURES,
  502. .config = &m88e1118_config,
  503. .startup = &m88e1118_startup,
  504. .shutdown = &genphy_shutdown,
  505. };
  506. static struct phy_driver M88E1118R_driver = {
  507. .name = "Marvell 88E1118R",
  508. .uid = 0x1410e40,
  509. .mask = 0xffffff0,
  510. .features = PHY_GBIT_FEATURES,
  511. .config = &m88e1118_config,
  512. .startup = &m88e1118_startup,
  513. .shutdown = &genphy_shutdown,
  514. };
  515. static struct phy_driver M88E1121R_driver = {
  516. .name = "Marvell 88E1121R",
  517. .uid = 0x1410cb0,
  518. .mask = 0xffffff0,
  519. .features = PHY_GBIT_FEATURES,
  520. .config = &m88e1121_config,
  521. .startup = &genphy_startup,
  522. .shutdown = &genphy_shutdown,
  523. };
  524. static struct phy_driver M88E1145_driver = {
  525. .name = "Marvell 88E1145",
  526. .uid = 0x1410cd0,
  527. .mask = 0xffffff0,
  528. .features = PHY_GBIT_FEATURES,
  529. .config = &m88e1145_config,
  530. .startup = &m88e1145_startup,
  531. .shutdown = &genphy_shutdown,
  532. };
  533. static struct phy_driver M88E1149S_driver = {
  534. .name = "Marvell 88E1149S",
  535. .uid = 0x1410ca0,
  536. .mask = 0xffffff0,
  537. .features = PHY_GBIT_FEATURES,
  538. .config = &m88e1149_config,
  539. .startup = &m88e1011s_startup,
  540. .shutdown = &genphy_shutdown,
  541. };
  542. static struct phy_driver M88E151x_driver = {
  543. .name = "Marvell 88E151x",
  544. .uid = 0x1410dd0,
  545. .mask = 0xffffff0,
  546. .features = PHY_GBIT_FEATURES,
  547. .config = &m88e151x_config,
  548. .startup = &m88e1011s_startup,
  549. .shutdown = &genphy_shutdown,
  550. .readext = &m88e1xxx_phy_extread,
  551. .writeext = &m88e1xxx_phy_extwrite,
  552. };
  553. static struct phy_driver M88E1310_driver = {
  554. .name = "Marvell 88E1310",
  555. .uid = 0x01410e90,
  556. .mask = 0xffffff0,
  557. .features = PHY_GBIT_FEATURES,
  558. .config = &m88e1310_config,
  559. .startup = &m88e1011s_startup,
  560. .shutdown = &genphy_shutdown,
  561. };
  562. static struct phy_driver M88E1680_driver = {
  563. .name = "Marvell 88E1680",
  564. .uid = 0x1410ed0,
  565. .mask = 0xffffff0,
  566. .features = PHY_GBIT_FEATURES,
  567. .config = &m88e1680_config,
  568. .startup = &genphy_startup,
  569. .shutdown = &genphy_shutdown,
  570. };
  571. int phy_marvell_init(void)
  572. {
  573. phy_register(&M88E1310_driver);
  574. phy_register(&M88E1149S_driver);
  575. phy_register(&M88E1145_driver);
  576. phy_register(&M88E1121R_driver);
  577. phy_register(&M88E1118_driver);
  578. phy_register(&M88E1118R_driver);
  579. phy_register(&M88E1111S_driver);
  580. phy_register(&M88E1011S_driver);
  581. phy_register(&M88E151x_driver);
  582. phy_register(&M88E1680_driver);
  583. return 0;
  584. }