dp83867.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TI PHY drivers
  4. *
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <phy.h>
  9. #include <dm/devres.h>
  10. #include <linux/bitops.h>
  11. #include <linux/compat.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #include <dt-bindings/net/ti-dp83867.h>
  15. #include "ti_phy_init.h"
  16. /* TI DP83867 */
  17. #define DP83867_DEVADDR 0x1f
  18. #define MII_DP83867_PHYCTRL 0x10
  19. #define MII_DP83867_MICR 0x12
  20. #define MII_DP83867_CFG2 0x14
  21. #define MII_DP83867_BISCR 0x16
  22. #define DP83867_CTRL 0x1f
  23. /* Extended Registers */
  24. #define DP83867_CFG4 0x0031
  25. #define DP83867_RGMIICTL 0x0032
  26. #define DP83867_STRAP_STS1 0x006E
  27. #define DP83867_STRAP_STS2 0x006f
  28. #define DP83867_RGMIIDCTL 0x0086
  29. #define DP83867_IO_MUX_CFG 0x0170
  30. #define DP83867_SGMIICTL 0x00D3
  31. #define DP83867_SW_RESET BIT(15)
  32. #define DP83867_SW_RESTART BIT(14)
  33. /* MICR Interrupt bits */
  34. #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
  35. #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
  36. #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
  37. #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
  38. #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
  39. #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
  40. #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
  41. #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  42. #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
  43. #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
  44. #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
  45. #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
  46. /* RGMIICTL bits */
  47. #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
  48. #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
  49. /* STRAP_STS1 bits */
  50. #define DP83867_STRAP_STS1_RESERVED BIT(11)
  51. /* STRAP_STS2 bits */
  52. #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
  53. #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
  54. #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
  55. #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
  56. #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
  57. /* PHY CTRL bits */
  58. #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
  59. #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
  60. #define DP83867_PHYCR_RESERVED_MASK BIT(11)
  61. #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
  62. #define DP83867_MDI_CROSSOVER 5
  63. #define DP83867_MDI_CROSSOVER_MDIX 2
  64. #define DP83867_PHYCTRL_SGMIIEN 0x0800
  65. #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
  66. #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
  67. /* RGMIIDCTL bits */
  68. #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
  69. #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
  70. #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
  71. /* CFG2 bits */
  72. #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
  73. #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
  74. #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
  75. #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
  76. #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
  77. #define MII_DP83867_CFG2_MASK 0x003F
  78. /* User setting - can be taken from DTS */
  79. #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  80. /* IO_MUX_CFG bits */
  81. #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
  82. #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
  83. #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
  84. #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
  85. #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
  86. #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
  87. GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
  88. /* CFG4 bits */
  89. #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
  90. /* SGMIICTL bits */
  91. #define DP83867_SGMII_TYPE BIT(14)
  92. enum {
  93. DP83867_PORT_MIRRORING_KEEP,
  94. DP83867_PORT_MIRRORING_EN,
  95. DP83867_PORT_MIRRORING_DIS,
  96. };
  97. struct dp83867_private {
  98. u32 rx_id_delay;
  99. u32 tx_id_delay;
  100. int fifo_depth;
  101. int io_impedance;
  102. bool rxctrl_strap_quirk;
  103. int port_mirroring;
  104. bool set_clk_output;
  105. unsigned int clk_output_sel;
  106. bool sgmii_ref_clk_en;
  107. };
  108. static int dp83867_config_port_mirroring(struct phy_device *phydev)
  109. {
  110. struct dp83867_private *dp83867 =
  111. (struct dp83867_private *)phydev->priv;
  112. u16 val;
  113. val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
  114. if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
  115. val |= DP83867_CFG4_PORT_MIRROR_EN;
  116. else
  117. val &= ~DP83867_CFG4_PORT_MIRROR_EN;
  118. phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
  119. return 0;
  120. }
  121. #if defined(CONFIG_DM_ETH)
  122. /**
  123. * dp83867_data_init - Convenience function for setting PHY specific data
  124. *
  125. * @phydev: the phy_device struct
  126. */
  127. static int dp83867_of_init(struct phy_device *phydev)
  128. {
  129. struct dp83867_private *dp83867 = phydev->priv;
  130. ofnode node;
  131. int ret;
  132. node = phy_get_ofnode(phydev);
  133. if (!ofnode_valid(node))
  134. return -EINVAL;
  135. /* Optional configuration */
  136. ret = ofnode_read_u32(node, "ti,clk-output-sel",
  137. &dp83867->clk_output_sel);
  138. /* If not set, keep default */
  139. if (!ret) {
  140. dp83867->set_clk_output = true;
  141. /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
  142. * DP83867_CLK_O_SEL_OFF.
  143. */
  144. if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
  145. dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
  146. pr_debug("ti,clk-output-sel value %u out of range\n",
  147. dp83867->clk_output_sel);
  148. return -EINVAL;
  149. }
  150. }
  151. if (ofnode_read_bool(node, "ti,max-output-impedance"))
  152. dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
  153. else if (ofnode_read_bool(node, "ti,min-output-impedance"))
  154. dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
  155. else
  156. dp83867->io_impedance = -EINVAL;
  157. if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
  158. dp83867->rxctrl_strap_quirk = true;
  159. /* Existing behavior was to use default pin strapping delay in rgmii
  160. * mode, but rgmii should have meant no delay. Warn existing users.
  161. */
  162. if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
  163. u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
  164. DP83867_STRAP_STS2);
  165. u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
  166. DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
  167. u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
  168. DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
  169. if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
  170. rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
  171. pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
  172. "Should be 'rgmii-id' to use internal delays\n");
  173. }
  174. /* RX delay *must* be specified if internal delay of RX is used. */
  175. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  176. phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  177. ret = ofnode_read_u32(node, "ti,rx-internal-delay",
  178. &dp83867->rx_id_delay);
  179. if (ret) {
  180. pr_debug("ti,rx-internal-delay must be specified\n");
  181. return ret;
  182. }
  183. if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
  184. pr_debug("ti,rx-internal-delay value of %u out of range\n",
  185. dp83867->rx_id_delay);
  186. return -EINVAL;
  187. }
  188. }
  189. /* TX delay *must* be specified if internal delay of RX is used. */
  190. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  191. phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  192. ret = ofnode_read_u32(node, "ti,tx-internal-delay",
  193. &dp83867->tx_id_delay);
  194. if (ret) {
  195. debug("ti,tx-internal-delay must be specified\n");
  196. return ret;
  197. }
  198. if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
  199. pr_debug("ti,tx-internal-delay value of %u out of range\n",
  200. dp83867->tx_id_delay);
  201. return -EINVAL;
  202. }
  203. }
  204. dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
  205. DEFAULT_FIFO_DEPTH);
  206. if (ofnode_read_bool(node, "enet-phy-lane-swap"))
  207. dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
  208. if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
  209. dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
  210. if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
  211. dp83867->sgmii_ref_clk_en = true;
  212. return 0;
  213. }
  214. #else
  215. static int dp83867_of_init(struct phy_device *phydev)
  216. {
  217. struct dp83867_private *dp83867 = phydev->priv;
  218. dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
  219. dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
  220. dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
  221. dp83867->io_impedance = -EINVAL;
  222. return 0;
  223. }
  224. #endif
  225. static int dp83867_config(struct phy_device *phydev)
  226. {
  227. struct dp83867_private *dp83867;
  228. unsigned int val, delay, cfg2;
  229. int ret, bs;
  230. dp83867 = (struct dp83867_private *)phydev->priv;
  231. ret = dp83867_of_init(phydev);
  232. if (ret)
  233. return ret;
  234. /* Restart the PHY. */
  235. val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
  236. phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
  237. val | DP83867_SW_RESTART);
  238. /* Mode 1 or 2 workaround */
  239. if (dp83867->rxctrl_strap_quirk) {
  240. val = phy_read_mmd(phydev, DP83867_DEVADDR,
  241. DP83867_CFG4);
  242. val &= ~BIT(7);
  243. phy_write_mmd(phydev, DP83867_DEVADDR,
  244. DP83867_CFG4, val);
  245. }
  246. if (phy_interface_is_rgmii(phydev)) {
  247. val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
  248. if (val < 0)
  249. goto err_out;
  250. val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
  251. val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
  252. /* Do not force link good */
  253. val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
  254. /* The code below checks if "port mirroring" N/A MODE4 has been
  255. * enabled during power on bootstrap.
  256. *
  257. * Such N/A mode enabled by mistake can put PHY IC in some
  258. * internal testing mode and disable RGMII transmission.
  259. *
  260. * In this particular case one needs to check STRAP_STS1
  261. * register's bit 11 (marked as RESERVED).
  262. */
  263. bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
  264. if (bs & DP83867_STRAP_STS1_RESERVED)
  265. val &= ~DP83867_PHYCR_RESERVED_MASK;
  266. ret = phy_write(phydev, MDIO_DEVAD_NONE,
  267. MII_DP83867_PHYCTRL, val);
  268. val = phy_read_mmd(phydev, DP83867_DEVADDR,
  269. DP83867_RGMIICTL);
  270. val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
  271. DP83867_RGMII_RX_CLK_DELAY_EN);
  272. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  273. val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
  274. DP83867_RGMII_RX_CLK_DELAY_EN);
  275. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
  276. val |= DP83867_RGMII_TX_CLK_DELAY_EN;
  277. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  278. val |= DP83867_RGMII_RX_CLK_DELAY_EN;
  279. phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
  280. delay = (dp83867->rx_id_delay |
  281. (dp83867->tx_id_delay <<
  282. DP83867_RGMII_TX_CLK_DELAY_SHIFT));
  283. phy_write_mmd(phydev, DP83867_DEVADDR,
  284. DP83867_RGMIIDCTL, delay);
  285. }
  286. if (phy_interface_is_sgmii(phydev)) {
  287. if (dp83867->sgmii_ref_clk_en)
  288. phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
  289. DP83867_SGMII_TYPE);
  290. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  291. (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
  292. cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
  293. cfg2 &= MII_DP83867_CFG2_MASK;
  294. cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
  295. MII_DP83867_CFG2_SGMII_AUTONEGEN |
  296. MII_DP83867_CFG2_SPEEDOPT_ENH |
  297. MII_DP83867_CFG2_SPEEDOPT_CNT |
  298. MII_DP83867_CFG2_SPEEDOPT_INTLOW);
  299. phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
  300. phy_write_mmd(phydev, DP83867_DEVADDR,
  301. DP83867_RGMIICTL, 0x0);
  302. phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
  303. DP83867_PHYCTRL_SGMIIEN |
  304. (DP83867_MDI_CROSSOVER_MDIX <<
  305. DP83867_MDI_CROSSOVER) |
  306. (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
  307. (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
  308. phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
  309. }
  310. if (dp83867->io_impedance >= 0) {
  311. val = phy_read_mmd(phydev,
  312. DP83867_DEVADDR,
  313. DP83867_IO_MUX_CFG);
  314. val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
  315. val |= dp83867->io_impedance &
  316. DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
  317. phy_write_mmd(phydev, DP83867_DEVADDR,
  318. DP83867_IO_MUX_CFG, val);
  319. }
  320. if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
  321. dp83867_config_port_mirroring(phydev);
  322. /* Clock output selection if muxing property is set */
  323. if (dp83867->set_clk_output) {
  324. val = phy_read_mmd(phydev, DP83867_DEVADDR,
  325. DP83867_IO_MUX_CFG);
  326. if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
  327. val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
  328. } else {
  329. val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
  330. DP83867_IO_MUX_CFG_CLK_O_DISABLE);
  331. val |= dp83867->clk_output_sel <<
  332. DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
  333. }
  334. phy_write_mmd(phydev, DP83867_DEVADDR,
  335. DP83867_IO_MUX_CFG, val);
  336. }
  337. genphy_config_aneg(phydev);
  338. return 0;
  339. err_out:
  340. return ret;
  341. }
  342. static int dp83867_probe(struct phy_device *phydev)
  343. {
  344. struct dp83867_private *dp83867;
  345. dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
  346. if (!dp83867)
  347. return -ENOMEM;
  348. phydev->priv = dp83867;
  349. return 0;
  350. }
  351. static struct phy_driver DP83867_driver = {
  352. .name = "TI DP83867",
  353. .uid = 0x2000a231,
  354. .mask = 0xfffffff0,
  355. .features = PHY_GBIT_FEATURES,
  356. .probe = dp83867_probe,
  357. .config = &dp83867_config,
  358. .startup = &genphy_startup,
  359. .shutdown = &genphy_shutdown,
  360. };
  361. int phy_dp83867_init(void)
  362. {
  363. phy_register(&DP83867_driver);
  364. return 0;
  365. }