cortina.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cortina CS4315/CS4340 10G PHY drivers
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2018, 2020 NXP
  7. *
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <linux/ctype.h>
  14. #include <linux/delay.h>
  15. #include <linux/string.h>
  16. #include <linux/err.h>
  17. #include <phy.h>
  18. #include <cortina.h>
  19. #include <nand.h>
  20. #include <spi_flash.h>
  21. #include <mmc.h>
  22. #ifdef CONFIG_ARM64
  23. #include <asm/arch/cpu.h>
  24. #endif
  25. #ifndef CONFIG_PHYLIB_10G
  26. #error The Cortina PHY needs 10G support
  27. #endif
  28. #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
  29. struct cortina_reg_config cortina_reg_cfg[] = {
  30. /* CS4315_enable_sr_mode */
  31. {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  32. {VILLA_MSEQ_OPTIONS, 0xf},
  33. {VILLA_MSEQ_PC, 0x0},
  34. {VILLA_MSEQ_BANKSELECT, 0x4},
  35. {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
  36. {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
  37. {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
  38. {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
  39. {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
  40. {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
  41. {VILLA_MSEQ_ENABLE_MSB, 0x0000},
  42. {VILLA_MSEQ_SPARE21_LSB, 0x6},
  43. {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
  44. {VILLA_MSEQ_SPARE12_MSB, 0x0000},
  45. /*
  46. * to invert the receiver path, uncomment the next line
  47. * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
  48. *
  49. * SPARE2_LSB is used to configure the device while in sr mode to
  50. * enable power savings and to use the optical module LOS signal.
  51. * in power savings mode, the internal prbs checker can not be used.
  52. * if the optical module LOS signal is used as an input to the micro
  53. * code, then the micro code will wait until the optical module
  54. * LOS = 0 before turning on the adaptive equalizer.
  55. * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
  56. * while setting bit 0 to 0 disables power savings mode.
  57. * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
  58. * optical module LOS signal while setting bit 2 to 1 configures the
  59. * device so that it will ignore the optical module LOS SPARE2_LSB = 0
  60. */
  61. /* enable power savings, ignore optical module LOS */
  62. {VILLA_MSEQ_SPARE2_LSB, 0x5},
  63. {VILLA_MSEQ_SPARE7_LSB, 0x1e},
  64. {VILLA_MSEQ_BANKSELECT, 0x4},
  65. {VILLA_MSEQ_SPARE9_LSB, 0x2},
  66. {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
  67. {VILLA_MSEQ_SPARE3_MSB, 0x2006},
  68. {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
  69. {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
  70. {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
  71. {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
  72. {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
  73. {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
  74. {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
  75. {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
  76. {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
  77. {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
  78. {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
  79. {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
  80. {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
  81. {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
  82. {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
  83. {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
  84. {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
  85. {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  86. {VILLA_MSEQ_OPTIONS, 0x7},
  87. /* set up min value for ffe1 */
  88. {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
  89. {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
  90. /* CS4315_sr_rx_pre_eq_set_4in */
  91. {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  92. {VILLA_MSEQ_OPTIONS, 0xf},
  93. {VILLA_MSEQ_BANKSELECT, 0x4},
  94. {VILLA_MSEQ_PC, 0x0},
  95. /* for lengths from 3.5 to 4.5inches */
  96. {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
  97. {VILLA_MSEQ_SPARE25_LSB, 0x0306},
  98. {VILLA_MSEQ_SPARE21_LSB, 0x2},
  99. {VILLA_MSEQ_SPARE23_LSB, 0x2},
  100. {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
  101. {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  102. {VILLA_MSEQ_OPTIONS, 0x7},
  103. /* CS4315_rx_drive_4inch */
  104. /* for length 4inches */
  105. {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
  106. {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
  107. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
  108. /* CS4315_tx_drive_4inch */
  109. /* for length 4inches */
  110. {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
  111. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
  112. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
  113. };
  114. __weak ulong *cs4340_get_fw_addr(void)
  115. {
  116. return (ulong *)CONFIG_CORTINA_FW_ADDR;
  117. }
  118. void cs4340_upload_firmware(struct phy_device *phydev)
  119. {
  120. char line_temp[0x50] = {0};
  121. char reg_addr[0x50] = {0};
  122. char reg_data[0x50] = {0};
  123. int i, line_cnt = 0, column_cnt = 0;
  124. struct cortina_reg_config fw_temp;
  125. char *addr = NULL;
  126. ulong cortina_fw_addr = (ulong)cs4340_get_fw_addr();
  127. #ifdef CONFIG_TFABOOT
  128. enum boot_src src = get_boot_src();
  129. if (src == BOOT_SOURCE_IFC_NOR) {
  130. addr = (char *)cortina_fw_addr;
  131. } else if (src == BOOT_SOURCE_IFC_NAND) {
  132. int ret;
  133. size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
  134. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  135. ret = nand_read(get_nand_dev_by_index(0),
  136. (loff_t)cortina_fw_addr, &fw_length, (u_char *)addr);
  137. if (ret == -EUCLEAN) {
  138. printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
  139. cortina_fw_addr, ret);
  140. }
  141. } else if (src == BOOT_SOURCE_QSPI_NOR) {
  142. int ret;
  143. struct spi_flash *ucode_flash;
  144. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  145. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  146. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  147. if (!ucode_flash) {
  148. puts("SF: probe for Cortina ucode failed\n");
  149. } else {
  150. ret = spi_flash_read(ucode_flash, cortina_fw_addr,
  151. CONFIG_CORTINA_FW_LENGTH, addr);
  152. if (ret)
  153. puts("SF: read for Cortina ucode failed\n");
  154. spi_flash_free(ucode_flash);
  155. }
  156. } else if (src == BOOT_SOURCE_SD_MMC) {
  157. int dev = CONFIG_SYS_MMC_ENV_DEV;
  158. u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
  159. u32 blk = cortina_fw_addr / 512;
  160. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  161. if (!mmc) {
  162. puts("Failed to find MMC device for Cortina ucode\n");
  163. } else {
  164. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  165. printf("MMC read: dev # %u, block # %u, count %u ...\n",
  166. dev, blk, cnt);
  167. mmc_init(mmc);
  168. #ifdef CONFIG_BLK
  169. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
  170. #else
  171. (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
  172. #endif
  173. }
  174. }
  175. #else /* CONFIG_TFABOOT */
  176. #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
  177. defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
  178. addr = (char *)cortina_fw_addr;
  179. #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
  180. int ret;
  181. size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
  182. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  183. ret = nand_read(get_nand_dev_by_index(0),
  184. (loff_t)cortina_fw_addr,
  185. &fw_length, (u_char *)addr);
  186. if (ret == -EUCLEAN) {
  187. printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
  188. cortina_fw_addr, ret);
  189. }
  190. #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
  191. int ret;
  192. struct spi_flash *ucode_flash;
  193. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  194. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  195. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  196. if (!ucode_flash) {
  197. puts("SF: probe for Cortina ucode failed\n");
  198. } else {
  199. ret = spi_flash_read(ucode_flash, cortina_fw_addr,
  200. CONFIG_CORTINA_FW_LENGTH, addr);
  201. if (ret)
  202. puts("SF: read for Cortina ucode failed\n");
  203. spi_flash_free(ucode_flash);
  204. }
  205. #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
  206. int dev = CONFIG_SYS_MMC_ENV_DEV;
  207. u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
  208. u32 blk = cortina_fw_addr / 512;
  209. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  210. if (!mmc) {
  211. puts("Failed to find MMC device for Cortina ucode\n");
  212. } else {
  213. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  214. printf("MMC read: dev # %u, block # %u, count %u ...\n",
  215. dev, blk, cnt);
  216. mmc_init(mmc);
  217. #ifdef CONFIG_BLK
  218. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  219. addr);
  220. #else
  221. (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
  222. addr);
  223. #endif
  224. }
  225. #endif
  226. #endif
  227. while (*addr != 'Q') {
  228. i = 0;
  229. while (*addr != 0x0a) {
  230. line_temp[i++] = *addr++;
  231. if (0x50 < i) {
  232. printf("Not found Cortina PHY ucode at 0x%p\n",
  233. (char *)cortina_fw_addr);
  234. return;
  235. }
  236. }
  237. addr++; /* skip '\n' */
  238. line_cnt++;
  239. column_cnt = i;
  240. line_temp[column_cnt] = '\0';
  241. if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
  242. return;
  243. for (i = 0; i < column_cnt; i++) {
  244. if (isspace(line_temp[i++]))
  245. break;
  246. }
  247. memcpy(reg_addr, line_temp, i);
  248. memcpy(reg_data, &line_temp[i], column_cnt - i);
  249. strim(reg_addr);
  250. strim(reg_data);
  251. fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
  252. fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
  253. 0xffff;
  254. phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
  255. }
  256. }
  257. #endif
  258. int cs4340_phy_init(struct phy_device *phydev)
  259. {
  260. #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
  261. int timeout = 100; /* 100ms */
  262. #endif
  263. int reg_value;
  264. /*
  265. * Cortina phy has provision to store
  266. * phy firmware in attached dedicated EEPROM.
  267. * Boards designed with EEPROM attached to Cortina
  268. * does not require FW upload.
  269. */
  270. #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
  271. /* step1: BIST test */
  272. phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
  273. phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
  274. phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
  275. while (--timeout) {
  276. reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
  277. if (reg_value & mseq_edc_bist_done) {
  278. if (0 == (reg_value & mseq_edc_bist_fail))
  279. break;
  280. }
  281. udelay(1000);
  282. }
  283. if (!timeout) {
  284. printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
  285. return -1;
  286. }
  287. /* setp2: upload ucode */
  288. cs4340_upload_firmware(phydev);
  289. #endif
  290. reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
  291. if (reg_value) {
  292. debug("%s checksum status failed.\n", __func__);
  293. return -1;
  294. }
  295. return 0;
  296. }
  297. int cs4340_config(struct phy_device *phydev)
  298. {
  299. cs4340_phy_init(phydev);
  300. return 0;
  301. }
  302. int cs4340_probe(struct phy_device *phydev)
  303. {
  304. phydev->flags = PHY_FLAG_BROKEN_RESET;
  305. return 0;
  306. }
  307. int cs4340_startup(struct phy_device *phydev)
  308. {
  309. phydev->link = 1;
  310. /* For now just lie and say it's 10G all the time */
  311. phydev->speed = SPEED_10000;
  312. phydev->duplex = DUPLEX_FULL;
  313. return 0;
  314. }
  315. int cs4223_phy_init(struct phy_device *phydev)
  316. {
  317. int reg_value;
  318. reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
  319. if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
  320. printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
  321. return -ENOSYS;
  322. }
  323. return 0;
  324. }
  325. int cs4223_config(struct phy_device *phydev)
  326. {
  327. return cs4223_phy_init(phydev);
  328. }
  329. int cs4223_probe(struct phy_device *phydev)
  330. {
  331. phydev->flags = PHY_FLAG_BROKEN_RESET;
  332. return 0;
  333. }
  334. int cs4223_startup(struct phy_device *phydev)
  335. {
  336. phydev->link = 1;
  337. phydev->speed = SPEED_10000;
  338. phydev->duplex = DUPLEX_FULL;
  339. return 0;
  340. }
  341. struct phy_driver cs4340_driver = {
  342. .name = "Cortina CS4315/CS4340",
  343. .uid = PHY_UID_CS4340,
  344. .mask = 0xfffffff0,
  345. .features = PHY_10G_FEATURES,
  346. .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
  347. MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
  348. MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
  349. .config = &cs4340_config,
  350. .probe = &cs4340_probe,
  351. .startup = &cs4340_startup,
  352. .shutdown = &gen10g_shutdown,
  353. };
  354. struct phy_driver cs4223_driver = {
  355. .name = "Cortina CS4223",
  356. .uid = PHY_UID_CS4223,
  357. .mask = 0x0ffff00f,
  358. .features = PHY_10G_FEATURES,
  359. .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
  360. MDIO_DEVS_AN),
  361. .config = &cs4223_config,
  362. .probe = &cs4223_probe,
  363. .startup = &cs4223_startup,
  364. .shutdown = &gen10g_shutdown,
  365. };
  366. int phy_cortina_init(void)
  367. {
  368. phy_register(&cs4340_driver);
  369. phy_register(&cs4223_driver);
  370. return 0;
  371. }
  372. int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
  373. {
  374. int phy_reg;
  375. /* Cortina PHY has non-standard offset of PHY ID registers */
  376. phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
  377. if (phy_reg < 0)
  378. return -EIO;
  379. *phy_id = (phy_reg & 0xffff) << 16;
  380. phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
  381. if (phy_reg < 0)
  382. return -EIO;
  383. *phy_id |= (phy_reg & 0xffff);
  384. if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
  385. return 0;
  386. /*
  387. * If Cortina PHY not detected,
  388. * try generic way to find PHY ID registers
  389. */
  390. phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  391. if (phy_reg < 0)
  392. return -EIO;
  393. *phy_id = (phy_reg & 0xffff) << 16;
  394. phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  395. if (phy_reg < 0)
  396. return -EIO;
  397. *phy_id |= (phy_reg & 0xffff);
  398. return 0;
  399. }