ca_phy.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cortina CS4315/CS4340 10G PHY drivers
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2018 NXP
  7. *
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <linux/ctype.h>
  14. #include <linux/delay.h>
  15. #include <linux/string.h>
  16. #include <linux/err.h>
  17. #include <phy.h>
  18. #define PHY_ID_RTL8211_EXT 0x001cc910
  19. #define PHY_ID_RTL8211_INT 0x001cc980
  20. #define PHY_ID_MASK 0xFFFFFFF0
  21. static void __internal_phy_init(struct phy_device *phydev, int reset_phy)
  22. {
  23. u8 phy_addr;
  24. u16 data;
  25. /* should initialize 4 GPHYs at once */
  26. for (phy_addr = 4; phy_addr > 0; phy_addr--) {
  27. phydev->addr = phy_addr;
  28. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0BC6);
  29. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x0053);
  30. phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x4003);
  31. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x7e01);
  32. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A42);
  33. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A40);
  34. phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1140);
  35. }
  36. /* workaround to fix GPHY fail */
  37. for (phy_addr = 1; phy_addr < 5; phy_addr++) {
  38. /* Clear clock fail interrupt */
  39. phydev->addr = phy_addr;
  40. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
  41. data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
  42. if (data == 0x10) {
  43. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
  44. data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
  45. printf("%s: read again.\n", __func__);
  46. }
  47. printf("%s: phy_addr=%d, read register 19, value=0x%x\n",
  48. __func__, phy_addr, data);
  49. }
  50. }
  51. static void __external_phy_init(struct phy_device *phydev, int reset_phy)
  52. {
  53. u16 val;
  54. /* Disable response PHYAD=0 function of RTL8211 series PHY */
  55. /* REG31 write 0x0007, set to extension page */
  56. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0007);
  57. /* REG30 write 0x002C, set to extension page 44 */
  58. phy_write(phydev, MDIO_DEVAD_NONE, 30, 0x002C);
  59. /*
  60. * REG27 write bit[2] = 0 disable response PHYAD = 0 function.
  61. * we should read REG27 and clear bit[2], and write back
  62. */
  63. val = phy_read(phydev, MDIO_DEVAD_NONE, 27);
  64. val &= ~(1 << 2);
  65. phy_write(phydev, MDIO_DEVAD_NONE, 27, val);
  66. /* REG31 write 0X0000, back to page0 */
  67. phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
  68. }
  69. static int rtl8211_external_config(struct phy_device *phydev)
  70. {
  71. __external_phy_init(phydev, 0);
  72. printf("%s: initialize RTL8211 external done.\n", __func__);
  73. return 0;
  74. }
  75. static int rtl8211_internal_config(struct phy_device *phydev)
  76. {
  77. struct phy_device phydev_init;
  78. memcpy(&phydev_init, phydev, sizeof(struct phy_device));
  79. /* should initialize 4 GPHYs at once */
  80. __internal_phy_init(&phydev_init, 0);
  81. printf("%s: initialize RTL8211 internal done.\n", __func__);
  82. return 0;
  83. }
  84. static int rtl8211_probe(struct phy_device *phydev)
  85. {
  86. /* disable reset behavior */
  87. phydev->flags = PHY_FLAG_BROKEN_RESET;
  88. return 0;
  89. }
  90. /* Support for RTL8211 External PHY */
  91. struct phy_driver rtl8211_external_driver = {
  92. .name = "Cortina RTL8211 External",
  93. .uid = PHY_ID_RTL8211_EXT,
  94. .mask = PHY_ID_MASK,
  95. .features = PHY_GBIT_FEATURES,
  96. .config = &rtl8211_external_config,
  97. .probe = &rtl8211_probe,
  98. .startup = &genphy_startup,
  99. };
  100. /* Support for RTL8211 Internal PHY */
  101. struct phy_driver rtl8211_internal_driver = {
  102. .name = "Cortina RTL8211 Inrernal",
  103. .uid = PHY_ID_RTL8211_INT,
  104. .mask = PHY_ID_MASK,
  105. .features = PHY_GBIT_FEATURES,
  106. .config = &rtl8211_internal_config,
  107. .probe = &rtl8211_probe,
  108. .startup = &genphy_startup,
  109. };
  110. int phy_cortina_access_init(void)
  111. {
  112. phy_register(&rtl8211_external_driver);
  113. phy_register(&rtl8211_internal_driver);
  114. return 0;
  115. }