atheros.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atheros PHY drivers
  4. *
  5. * Copyright 2011, 2013 Freescale Semiconductor, Inc.
  6. * author Andy Fleming
  7. * Copyright (c) 2019 Michael Walle <michael@walle.cc>
  8. */
  9. #include <common.h>
  10. #include <phy.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/bitfield.h>
  13. #include <linux/bitops.h>
  14. #include <dt-bindings/net/qca-ar803x.h>
  15. #define AR803x_PHY_DEBUG_ADDR_REG 0x1d
  16. #define AR803x_PHY_DEBUG_DATA_REG 0x1e
  17. /* Debug registers */
  18. #define AR803x_DEBUG_REG_0 0x0
  19. #define AR803x_RGMII_RX_CLK_DLY BIT(15)
  20. #define AR803x_DEBUG_REG_5 0x5
  21. #define AR803x_RGMII_TX_CLK_DLY BIT(8)
  22. #define AR803x_DEBUG_REG_1F 0x1f
  23. #define AR803x_PLL_ON BIT(2)
  24. #define AR803x_RGMII_1V8 BIT(3)
  25. /* CLK_25M register is at MMD 7, address 0x8016 */
  26. #define AR803x_CLK_25M_SEL_REG 0x8016
  27. #define AR803x_CLK_25M_MASK GENMASK(4, 2)
  28. #define AR803x_CLK_25M_25MHZ_XTAL 0
  29. #define AR803x_CLK_25M_25MHZ_DSP 1
  30. #define AR803x_CLK_25M_50MHZ_PLL 2
  31. #define AR803x_CLK_25M_50MHZ_DSP 3
  32. #define AR803x_CLK_25M_62_5MHZ_PLL 4
  33. #define AR803x_CLK_25M_62_5MHZ_DSP 5
  34. #define AR803x_CLK_25M_125MHZ_PLL 6
  35. #define AR803x_CLK_25M_125MHZ_DSP 7
  36. #define AR8035_CLK_25M_MASK GENMASK(4, 3)
  37. #define AR803x_CLK_25M_DR_MASK GENMASK(8, 7)
  38. #define AR803x_CLK_25M_DR_FULL 0
  39. #define AR803x_CLK_25M_DR_HALF 1
  40. #define AR803x_CLK_25M_DR_QUARTER 2
  41. #define AR8021_PHY_ID 0x004dd040
  42. #define AR8031_PHY_ID 0x004dd074
  43. #define AR8035_PHY_ID 0x004dd072
  44. struct ar803x_priv {
  45. int flags;
  46. #define AR803x_FLAG_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
  47. #define AR803x_FLAG_RGMII_1V8 BIT(1) /* use 1.8V RGMII I/O voltage */
  48. u16 clk_25m_reg;
  49. u16 clk_25m_mask;
  50. };
  51. static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
  52. {
  53. int ret;
  54. ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  55. reg);
  56. if (ret < 0)
  57. return ret;
  58. return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
  59. }
  60. static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
  61. u16 clear, u16 set)
  62. {
  63. int val;
  64. val = ar803x_debug_reg_read(phydev, reg);
  65. if (val < 0)
  66. return val;
  67. val &= 0xffff;
  68. val &= ~clear;
  69. val |= set;
  70. return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
  71. val);
  72. }
  73. static int ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
  74. {
  75. u16 clear = 0, set = 0;
  76. if (on)
  77. set = AR803x_RGMII_RX_CLK_DLY;
  78. else
  79. clear = AR803x_RGMII_RX_CLK_DLY;
  80. return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, clear, set);
  81. }
  82. static int ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
  83. {
  84. u16 clear = 0, set = 0;
  85. if (on)
  86. set = AR803x_RGMII_TX_CLK_DLY;
  87. else
  88. clear = AR803x_RGMII_TX_CLK_DLY;
  89. return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, clear, set);
  90. }
  91. static int ar8021_config(struct phy_device *phydev)
  92. {
  93. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
  94. BMCR_ANENABLE | BMCR_ANRESTART);
  95. ar803x_enable_tx_delay(phydev, true);
  96. phydev->supported = phydev->drv->features;
  97. return 0;
  98. }
  99. static int ar803x_delay_config(struct phy_device *phydev)
  100. {
  101. int ret;
  102. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
  103. phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  104. ret = ar803x_enable_tx_delay(phydev, true);
  105. else
  106. ret = ar803x_enable_tx_delay(phydev, false);
  107. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
  108. phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  109. ret = ar803x_enable_rx_delay(phydev, true);
  110. else
  111. ret = ar803x_enable_rx_delay(phydev, false);
  112. return ret;
  113. }
  114. static int ar803x_regs_config(struct phy_device *phydev)
  115. {
  116. struct ar803x_priv *priv = phydev->priv;
  117. u16 set = 0, clear = 0;
  118. int val;
  119. int ret;
  120. /* no configuration available */
  121. if (!priv)
  122. return 0;
  123. /*
  124. * Only supported on the AR8031, AR8035 has strappings for the PLL mode
  125. * as well as the RGMII voltage.
  126. */
  127. if (phydev->drv->uid == AR8031_PHY_ID) {
  128. if (priv->flags & AR803x_FLAG_KEEP_PLL_ENABLED)
  129. set |= AR803x_PLL_ON;
  130. else
  131. clear |= AR803x_PLL_ON;
  132. if (priv->flags & AR803x_FLAG_RGMII_1V8)
  133. set |= AR803x_RGMII_1V8;
  134. else
  135. clear |= AR803x_RGMII_1V8;
  136. ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_1F, clear,
  137. set);
  138. if (ret < 0)
  139. return ret;
  140. }
  141. /* save the write access if the mask is empty */
  142. if (priv->clk_25m_mask) {
  143. val = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
  144. if (val < 0)
  145. return val;
  146. val &= ~priv->clk_25m_mask;
  147. val |= priv->clk_25m_reg;
  148. ret = phy_write_mmd(phydev, MDIO_MMD_AN,
  149. AR803x_CLK_25M_SEL_REG, val);
  150. if (ret < 0)
  151. return ret;
  152. }
  153. return 0;
  154. }
  155. static int ar803x_of_init(struct phy_device *phydev)
  156. {
  157. #if defined(CONFIG_DM_ETH)
  158. struct ar803x_priv *priv;
  159. ofnode node, vddio_reg_node;
  160. u32 strength, freq, min_uV, max_uV;
  161. int sel;
  162. node = phy_get_ofnode(phydev);
  163. if (!ofnode_valid(node))
  164. return -EINVAL;
  165. priv = malloc(sizeof(*priv));
  166. if (!priv)
  167. return -ENOMEM;
  168. memset(priv, 0, sizeof(*priv));
  169. phydev->priv = priv;
  170. debug("%s: found PHY node: %s\n", __func__, ofnode_get_name(node));
  171. if (ofnode_read_bool(node, "qca,keep-pll-enabled"))
  172. priv->flags |= AR803x_FLAG_KEEP_PLL_ENABLED;
  173. /*
  174. * We can't use the regulator framework because the regulator is
  175. * a subnode of the PHY. So just read the two properties we are
  176. * interested in.
  177. */
  178. vddio_reg_node = ofnode_find_subnode(node, "vddio-regulator");
  179. if (ofnode_valid(vddio_reg_node)) {
  180. min_uV = ofnode_read_u32_default(vddio_reg_node,
  181. "regulator-min-microvolt", 0);
  182. max_uV = ofnode_read_u32_default(vddio_reg_node,
  183. "regulator-max-microvolt", 0);
  184. if (min_uV != max_uV) {
  185. free(priv);
  186. return -EINVAL;
  187. }
  188. switch (min_uV) {
  189. case 1500000:
  190. break;
  191. case 1800000:
  192. priv->flags |= AR803x_FLAG_RGMII_1V8;
  193. break;
  194. default:
  195. free(priv);
  196. return -EINVAL;
  197. }
  198. }
  199. /*
  200. * Get the CLK_25M frequency from the device tree. Only XTAL and PLL
  201. * sources are supported right now. There is also the possibilty to use
  202. * the DSP as frequency reference, this is used for synchronous
  203. * ethernet.
  204. */
  205. if (!ofnode_read_u32(node, "qca,clk-out-frequency", &freq)) {
  206. switch (freq) {
  207. case 25000000:
  208. sel = AR803x_CLK_25M_25MHZ_XTAL;
  209. break;
  210. case 50000000:
  211. sel = AR803x_CLK_25M_50MHZ_PLL;
  212. break;
  213. case 62500000:
  214. sel = AR803x_CLK_25M_62_5MHZ_PLL;
  215. break;
  216. case 125000000:
  217. sel = AR803x_CLK_25M_125MHZ_PLL;
  218. break;
  219. default:
  220. dev_err(phydev->dev,
  221. "invalid qca,clk-out-frequency\n");
  222. free(priv);
  223. return -EINVAL;
  224. }
  225. priv->clk_25m_mask |= AR803x_CLK_25M_MASK;
  226. priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel);
  227. /*
  228. * Fixup for the AR8035 which only has two bits. The two
  229. * remaining bits map to the same frequencies.
  230. */
  231. if (phydev->drv->uid == AR8035_PHY_ID) {
  232. priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
  233. priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
  234. }
  235. }
  236. if (phydev->drv->uid == AR8031_PHY_ID &&
  237. !ofnode_read_u32(node, "qca,clk-out-strength", &strength)) {
  238. switch (strength) {
  239. case AR803X_STRENGTH_FULL:
  240. sel = AR803x_CLK_25M_DR_FULL;
  241. break;
  242. case AR803X_STRENGTH_HALF:
  243. sel = AR803x_CLK_25M_DR_HALF;
  244. break;
  245. case AR803X_STRENGTH_QUARTER:
  246. sel = AR803x_CLK_25M_DR_QUARTER;
  247. break;
  248. default:
  249. dev_err(phydev->dev,
  250. "invalid qca,clk-out-strength\n");
  251. free(priv);
  252. return -EINVAL;
  253. }
  254. priv->clk_25m_mask |= AR803x_CLK_25M_DR_MASK;
  255. priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel);
  256. }
  257. debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__,
  258. priv->flags, priv->clk_25m_reg, priv->clk_25m_mask);
  259. #endif
  260. return 0;
  261. }
  262. static int ar803x_config(struct phy_device *phydev)
  263. {
  264. int ret;
  265. ret = ar803x_of_init(phydev);
  266. if (ret < 0)
  267. return ret;
  268. ret = ar803x_delay_config(phydev);
  269. if (ret < 0)
  270. return ret;
  271. ret = ar803x_regs_config(phydev);
  272. if (ret < 0)
  273. return ret;
  274. phydev->supported = phydev->drv->features;
  275. genphy_config_aneg(phydev);
  276. genphy_restart_aneg(phydev);
  277. return 0;
  278. }
  279. static struct phy_driver AR8021_driver = {
  280. .name = "AR8021",
  281. .uid = AR8021_PHY_ID,
  282. .mask = 0xfffffff0,
  283. .features = PHY_GBIT_FEATURES,
  284. .config = ar8021_config,
  285. .startup = genphy_startup,
  286. .shutdown = genphy_shutdown,
  287. };
  288. static struct phy_driver AR8031_driver = {
  289. .name = "AR8031/AR8033",
  290. .uid = AR8031_PHY_ID,
  291. .mask = 0xffffffef,
  292. .features = PHY_GBIT_FEATURES,
  293. .config = ar803x_config,
  294. .startup = genphy_startup,
  295. .shutdown = genphy_shutdown,
  296. };
  297. static struct phy_driver AR8035_driver = {
  298. .name = "AR8035",
  299. .uid = AR8035_PHY_ID,
  300. .mask = 0xffffffef,
  301. .features = PHY_GBIT_FEATURES,
  302. .config = ar803x_config,
  303. .startup = genphy_startup,
  304. .shutdown = genphy_shutdown,
  305. };
  306. int phy_atheros_init(void)
  307. {
  308. phy_register(&AR8021_driver);
  309. phy_register(&AR8031_driver);
  310. phy_register(&AR8035_driver);
  311. return 0;
  312. }