pcnet.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
  4. *
  5. * This driver for AMD PCnet network controllers is derived from the
  6. * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <asm/cache.h>
  17. #include <asm/io.h>
  18. #include <pci.h>
  19. #include <linux/delay.h>
  20. #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
  21. #define PCNET_DEBUG1(fmt,args...) \
  22. debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
  23. #define PCNET_DEBUG2(fmt,args...) \
  24. debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
  25. /*
  26. * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  27. * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  28. * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  29. */
  30. #define PCNET_LOG_TX_BUFFERS 0
  31. #define PCNET_LOG_RX_BUFFERS 2
  32. #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
  33. #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
  34. #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
  35. #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
  36. #define PKT_BUF_SZ 1544
  37. /* The PCNET Rx and Tx ring descriptors. */
  38. struct pcnet_rx_head {
  39. u32 base;
  40. s16 buf_length;
  41. s16 status;
  42. u32 msg_length;
  43. u32 reserved;
  44. };
  45. struct pcnet_tx_head {
  46. u32 base;
  47. s16 length;
  48. s16 status;
  49. u32 misc;
  50. u32 reserved;
  51. };
  52. /* The PCNET 32-Bit initialization block, described in databook. */
  53. struct pcnet_init_block {
  54. u16 mode;
  55. u16 tlen_rlen;
  56. u8 phys_addr[6];
  57. u16 reserved;
  58. u32 filter[2];
  59. /* Receive and transmit ring base, along with extra bits. */
  60. u32 rx_ring;
  61. u32 tx_ring;
  62. u32 reserved2;
  63. };
  64. struct pcnet_uncached_priv {
  65. struct pcnet_rx_head rx_ring[RX_RING_SIZE];
  66. struct pcnet_tx_head tx_ring[TX_RING_SIZE];
  67. struct pcnet_init_block init_block;
  68. } __aligned(ARCH_DMA_MINALIGN);
  69. struct pcnet_priv {
  70. struct pcnet_uncached_priv ucp;
  71. /* Receive Buffer space */
  72. unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
  73. struct pcnet_uncached_priv *uc;
  74. #ifdef CONFIG_DM_ETH
  75. struct udevice *dev;
  76. const char *name;
  77. #else
  78. pci_dev_t dev;
  79. char *name;
  80. #endif
  81. void __iomem *iobase;
  82. u8 *enetaddr;
  83. u16 status;
  84. int cur_rx;
  85. int cur_tx;
  86. };
  87. /* Offsets from base I/O address for WIO mode */
  88. #define PCNET_RDP 0x10
  89. #define PCNET_RAP 0x12
  90. #define PCNET_RESET 0x14
  91. #define PCNET_BDP 0x16
  92. static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
  93. {
  94. writew(index, lp->iobase + PCNET_RAP);
  95. return readw(lp->iobase + PCNET_RDP);
  96. }
  97. static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
  98. {
  99. writew(index, lp->iobase + PCNET_RAP);
  100. writew(val, lp->iobase + PCNET_RDP);
  101. }
  102. static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
  103. {
  104. writew(index, lp->iobase + PCNET_RAP);
  105. return readw(lp->iobase + PCNET_BDP);
  106. }
  107. static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
  108. {
  109. writew(index, lp->iobase + PCNET_RAP);
  110. writew(val, lp->iobase + PCNET_BDP);
  111. }
  112. static void pcnet_reset(struct pcnet_priv *lp)
  113. {
  114. readw(lp->iobase + PCNET_RESET);
  115. }
  116. static int pcnet_check(struct pcnet_priv *lp)
  117. {
  118. writew(88, lp->iobase + PCNET_RAP);
  119. return readw(lp->iobase + PCNET_RAP) == 88;
  120. }
  121. static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
  122. {
  123. void *virt_addr = addr;
  124. #ifdef CONFIG_DM_ETH
  125. return dm_pci_virt_to_mem(lp->dev, virt_addr);
  126. #else
  127. return pci_virt_to_mem(lp->dev, virt_addr);
  128. #endif
  129. }
  130. static struct pci_device_id supported[] = {
  131. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
  132. {}
  133. };
  134. static int pcnet_probe_common(struct pcnet_priv *lp)
  135. {
  136. int chip_version;
  137. char *chipname;
  138. int i;
  139. /* Reset the PCnet controller */
  140. pcnet_reset(lp);
  141. /* Check if register access is working */
  142. if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
  143. printf("%s: CSR register access check failed\n", lp->name);
  144. return -1;
  145. }
  146. /* Identify the chip */
  147. chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
  148. if ((chip_version & 0xfff) != 0x003)
  149. return -1;
  150. chip_version = (chip_version >> 12) & 0xffff;
  151. switch (chip_version) {
  152. case 0x2621:
  153. chipname = "PCnet/PCI II 79C970A"; /* PCI */
  154. break;
  155. case 0x2625:
  156. chipname = "PCnet/FAST III 79C973"; /* PCI */
  157. break;
  158. case 0x2627:
  159. chipname = "PCnet/FAST III 79C975"; /* PCI */
  160. break;
  161. default:
  162. printf("%s: PCnet version %#x not supported\n",
  163. lp->name, chip_version);
  164. return -1;
  165. }
  166. PCNET_DEBUG1("AMD %s\n", chipname);
  167. /*
  168. * In most chips, after a chip reset, the ethernet address is read from
  169. * the station address PROM at the base address and programmed into the
  170. * "Physical Address Registers" CSR12-14.
  171. */
  172. for (i = 0; i < 3; i++) {
  173. unsigned int val;
  174. val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
  175. /* There may be endianness issues here. */
  176. lp->enetaddr[2 * i] = val & 0x0ff;
  177. lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
  178. }
  179. return 0;
  180. }
  181. static int pcnet_init_common(struct pcnet_priv *lp)
  182. {
  183. struct pcnet_uncached_priv *uc;
  184. int i, val;
  185. unsigned long addr;
  186. PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
  187. /* Switch pcnet to 32bit mode */
  188. pcnet_write_bcr(lp, 20, 2);
  189. /* Set/reset autoselect bit */
  190. val = pcnet_read_bcr(lp, 2) & ~2;
  191. val |= 2;
  192. pcnet_write_bcr(lp, 2, val);
  193. /* Enable auto negotiate, setup, disable fd */
  194. val = pcnet_read_bcr(lp, 32) & ~0x98;
  195. val |= 0x20;
  196. pcnet_write_bcr(lp, 32, val);
  197. /*
  198. * Enable NOUFLO on supported controllers, with the transmit
  199. * start point set to the full packet. This will cause entire
  200. * packets to be buffered by the ethernet controller before
  201. * transmission, eliminating underflows which are common on
  202. * slower devices. Controllers which do not support NOUFLO will
  203. * simply be left with a larger transmit FIFO threshold.
  204. */
  205. val = pcnet_read_bcr(lp, 18);
  206. val |= 1 << 11;
  207. pcnet_write_bcr(lp, 18, val);
  208. val = pcnet_read_csr(lp, 80);
  209. val |= 0x3 << 10;
  210. pcnet_write_csr(lp, 80, val);
  211. uc = lp->uc;
  212. uc->init_block.mode = cpu_to_le16(0x0000);
  213. uc->init_block.filter[0] = 0x00000000;
  214. uc->init_block.filter[1] = 0x00000000;
  215. /*
  216. * Initialize the Rx ring.
  217. */
  218. lp->cur_rx = 0;
  219. for (i = 0; i < RX_RING_SIZE; i++) {
  220. addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
  221. uc->rx_ring[i].base = cpu_to_le32(addr);
  222. uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
  223. uc->rx_ring[i].status = cpu_to_le16(0x8000);
  224. PCNET_DEBUG1
  225. ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
  226. uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
  227. uc->rx_ring[i].status);
  228. }
  229. /*
  230. * Initialize the Tx ring. The Tx buffer address is filled in as
  231. * needed, but we do need to clear the upper ownership bit.
  232. */
  233. lp->cur_tx = 0;
  234. for (i = 0; i < TX_RING_SIZE; i++) {
  235. uc->tx_ring[i].base = 0;
  236. uc->tx_ring[i].status = 0;
  237. }
  238. /*
  239. * Setup Init Block.
  240. */
  241. PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
  242. for (i = 0; i < 6; i++) {
  243. lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
  244. PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
  245. }
  246. uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
  247. RX_RING_LEN_BITS);
  248. addr = pcnet_virt_to_mem(lp, uc->rx_ring);
  249. uc->init_block.rx_ring = cpu_to_le32(addr);
  250. addr = pcnet_virt_to_mem(lp, uc->tx_ring);
  251. uc->init_block.tx_ring = cpu_to_le32(addr);
  252. PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
  253. uc->init_block.tlen_rlen,
  254. uc->init_block.rx_ring, uc->init_block.tx_ring);
  255. /*
  256. * Tell the controller where the Init Block is located.
  257. */
  258. barrier();
  259. addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
  260. pcnet_write_csr(lp, 1, addr & 0xffff);
  261. pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
  262. pcnet_write_csr(lp, 4, 0x0915);
  263. pcnet_write_csr(lp, 0, 0x0001); /* start */
  264. /* Wait for Init Done bit */
  265. for (i = 10000; i > 0; i--) {
  266. if (pcnet_read_csr(lp, 0) & 0x0100)
  267. break;
  268. udelay(10);
  269. }
  270. if (i <= 0) {
  271. printf("%s: TIMEOUT: controller init failed\n", lp->name);
  272. pcnet_reset(lp);
  273. return -1;
  274. }
  275. /*
  276. * Finally start network controller operation.
  277. */
  278. pcnet_write_csr(lp, 0, 0x0002);
  279. return 0;
  280. }
  281. static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
  282. {
  283. int i, status;
  284. u32 addr;
  285. struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
  286. PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
  287. packet);
  288. flush_dcache_range((unsigned long)packet,
  289. (unsigned long)packet + pkt_len);
  290. /* Wait for completion by testing the OWN bit */
  291. for (i = 1000; i > 0; i--) {
  292. status = readw(&entry->status);
  293. if ((status & 0x8000) == 0)
  294. break;
  295. udelay(100);
  296. PCNET_DEBUG2(".");
  297. }
  298. if (i <= 0) {
  299. printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
  300. lp->name, lp->cur_tx, status);
  301. pkt_len = 0;
  302. goto failure;
  303. }
  304. /*
  305. * Setup Tx ring. Caution: the write order is important here,
  306. * set the status with the "ownership" bits last.
  307. */
  308. addr = pcnet_virt_to_mem(lp, packet);
  309. writew(-pkt_len, &entry->length);
  310. writel(0, &entry->misc);
  311. writel(addr, &entry->base);
  312. writew(0x8300, &entry->status);
  313. /* Trigger an immediate send poll. */
  314. pcnet_write_csr(lp, 0, 0x0008);
  315. failure:
  316. if (++lp->cur_tx >= TX_RING_SIZE)
  317. lp->cur_tx = 0;
  318. PCNET_DEBUG2("done\n");
  319. return pkt_len;
  320. }
  321. static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
  322. {
  323. struct pcnet_rx_head *entry;
  324. unsigned char *buf;
  325. int pkt_len = 0;
  326. u16 err_status;
  327. entry = &lp->uc->rx_ring[lp->cur_rx];
  328. /*
  329. * If we own the next entry, it's a new packet. Send it up.
  330. */
  331. lp->status = readw(&entry->status);
  332. if ((lp->status & 0x8000) != 0)
  333. return 0;
  334. err_status = lp->status >> 8;
  335. if (err_status != 0x03) { /* There was an error. */
  336. printf("%s: Rx%d", lp->name, lp->cur_rx);
  337. PCNET_DEBUG1(" (status=0x%x)", err_status);
  338. if (err_status & 0x20)
  339. printf(" Frame");
  340. if (err_status & 0x10)
  341. printf(" Overflow");
  342. if (err_status & 0x08)
  343. printf(" CRC");
  344. if (err_status & 0x04)
  345. printf(" Fifo");
  346. printf(" Error\n");
  347. lp->status &= 0x03ff;
  348. return 0;
  349. }
  350. pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
  351. if (pkt_len < 60) {
  352. printf("%s: Rx%d: invalid packet length %d\n",
  353. lp->name, lp->cur_rx, pkt_len);
  354. return 0;
  355. }
  356. *bufp = lp->rx_buf[lp->cur_rx];
  357. invalidate_dcache_range((unsigned long)*bufp,
  358. (unsigned long)*bufp + pkt_len);
  359. PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
  360. lp->cur_rx, pkt_len, buf);
  361. return pkt_len;
  362. }
  363. static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
  364. {
  365. struct pcnet_rx_head *entry;
  366. entry = &lp->uc->rx_ring[lp->cur_rx];
  367. lp->status |= 0x8000;
  368. writew(lp->status, &entry->status);
  369. if (++lp->cur_rx >= RX_RING_SIZE)
  370. lp->cur_rx = 0;
  371. }
  372. static void pcnet_halt_common(struct pcnet_priv *lp)
  373. {
  374. int i;
  375. PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
  376. /* Reset the PCnet controller */
  377. pcnet_reset(lp);
  378. /* Wait for Stop bit */
  379. for (i = 1000; i > 0; i--) {
  380. if (pcnet_read_csr(lp, 0) & 0x4)
  381. break;
  382. udelay(10);
  383. }
  384. if (i <= 0)
  385. printf("%s: TIMEOUT: controller reset failed\n", lp->name);
  386. }
  387. #ifndef CONFIG_DM_ETH
  388. static int pcnet_init(struct eth_device *dev, struct bd_info *bis)
  389. {
  390. struct pcnet_priv *lp = dev->priv;
  391. return pcnet_init_common(lp);
  392. }
  393. static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
  394. {
  395. struct pcnet_priv *lp = dev->priv;
  396. return pcnet_send_common(lp, packet, pkt_len);
  397. }
  398. static int pcnet_recv(struct eth_device *dev)
  399. {
  400. struct pcnet_priv *lp = dev->priv;
  401. uchar *packet;
  402. int ret;
  403. ret = pcnet_recv_common(lp, &packet);
  404. if (ret > 0)
  405. net_process_received_packet(packet, ret);
  406. if (ret)
  407. pcnet_free_pkt_common(lp, ret);
  408. return ret;
  409. }
  410. static void pcnet_halt(struct eth_device *dev)
  411. {
  412. struct pcnet_priv *lp = dev->priv;
  413. pcnet_halt_common(lp);
  414. }
  415. int pcnet_initialize(struct bd_info *bis)
  416. {
  417. pci_dev_t devbusfn;
  418. struct eth_device *dev;
  419. struct pcnet_priv *lp;
  420. u16 command, status;
  421. int dev_nr = 0;
  422. u32 bar;
  423. PCNET_DEBUG1("\n%s...\n", __func__);
  424. for (dev_nr = 0; ; dev_nr++) {
  425. /*
  426. * Find the PCnet PCI device(s).
  427. */
  428. devbusfn = pci_find_devices(supported, dev_nr);
  429. if (devbusfn < 0)
  430. break;
  431. /*
  432. * Allocate and pre-fill the device structure.
  433. */
  434. dev = calloc(1, sizeof(*dev));
  435. if (!dev) {
  436. printf("pcnet: Can not allocate memory\n");
  437. break;
  438. }
  439. /*
  440. * We only maintain one structure because the drivers will
  441. * never be used concurrently. In 32bit mode the RX and TX
  442. * ring entries must be aligned on 16-byte boundaries.
  443. */
  444. lp = malloc_cache_aligned(sizeof(*lp));
  445. lp->uc = map_physmem((phys_addr_t)&lp->ucp,
  446. sizeof(lp->ucp), MAP_NOCACHE);
  447. lp->dev = devbusfn;
  448. flush_dcache_range((unsigned long)lp,
  449. (unsigned long)lp + sizeof(*lp));
  450. dev->priv = lp;
  451. sprintf(dev->name, "pcnet#%d", dev_nr);
  452. lp->name = dev->name;
  453. lp->enetaddr = dev->enetaddr;
  454. /*
  455. * Setup the PCI device.
  456. */
  457. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
  458. lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
  459. PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
  460. lp->name, devbusfn, lp->iobase);
  461. command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  462. pci_write_config_word(devbusfn, PCI_COMMAND, command);
  463. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  464. if ((status & command) != command) {
  465. printf("%s: Couldn't enable IO access or Bus Mastering\n",
  466. lp->name);
  467. free(dev);
  468. continue;
  469. }
  470. pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
  471. /*
  472. * Probe the PCnet chip.
  473. */
  474. if (pcnet_probe_common(lp) < 0) {
  475. free(dev);
  476. continue;
  477. }
  478. /*
  479. * Setup device structure and register the driver.
  480. */
  481. dev->init = pcnet_init;
  482. dev->halt = pcnet_halt;
  483. dev->send = pcnet_send;
  484. dev->recv = pcnet_recv;
  485. eth_register(dev);
  486. }
  487. udelay(10 * 1000);
  488. return dev_nr;
  489. }
  490. #else /* DM_ETH */
  491. static int pcnet_start(struct udevice *dev)
  492. {
  493. struct eth_pdata *plat = dev_get_plat(dev);
  494. struct pcnet_priv *priv = dev_get_priv(dev);
  495. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  496. return pcnet_init_common(priv);
  497. }
  498. static void pcnet_stop(struct udevice *dev)
  499. {
  500. struct pcnet_priv *priv = dev_get_priv(dev);
  501. pcnet_halt_common(priv);
  502. }
  503. static int pcnet_send(struct udevice *dev, void *packet, int length)
  504. {
  505. struct pcnet_priv *priv = dev_get_priv(dev);
  506. int ret;
  507. ret = pcnet_send_common(priv, packet, length);
  508. return ret ? 0 : -ETIMEDOUT;
  509. }
  510. static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
  511. {
  512. struct pcnet_priv *priv = dev_get_priv(dev);
  513. return pcnet_recv_common(priv, packetp);
  514. }
  515. static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
  516. {
  517. struct pcnet_priv *priv = dev_get_priv(dev);
  518. pcnet_free_pkt_common(priv, length);
  519. return 0;
  520. }
  521. static int pcnet_bind(struct udevice *dev)
  522. {
  523. static int card_number;
  524. char name[16];
  525. sprintf(name, "pcnet#%u", card_number++);
  526. return device_set_name(dev, name);
  527. }
  528. static int pcnet_probe(struct udevice *dev)
  529. {
  530. struct eth_pdata *plat = dev_get_plat(dev);
  531. struct pcnet_priv *lp = dev_get_priv(dev);
  532. u16 command, status;
  533. u32 iobase;
  534. int ret;
  535. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
  536. iobase &= ~0xf;
  537. lp->uc = map_physmem((phys_addr_t)&lp->ucp,
  538. sizeof(lp->ucp), MAP_NOCACHE);
  539. lp->dev = dev;
  540. lp->name = dev->name;
  541. lp->enetaddr = plat->enetaddr;
  542. lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
  543. flush_dcache_range((unsigned long)lp,
  544. (unsigned long)lp + sizeof(*lp));
  545. command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  546. dm_pci_write_config16(dev, PCI_COMMAND, command);
  547. dm_pci_read_config16(dev, PCI_COMMAND, &status);
  548. if ((status & command) != command) {
  549. printf("%s: Couldn't enable IO access or Bus Mastering\n",
  550. lp->name);
  551. return -EINVAL;
  552. }
  553. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
  554. ret = pcnet_probe_common(lp);
  555. if (ret)
  556. return ret;
  557. return 0;
  558. }
  559. static const struct eth_ops pcnet_ops = {
  560. .start = pcnet_start,
  561. .send = pcnet_send,
  562. .recv = pcnet_recv,
  563. .stop = pcnet_stop,
  564. .free_pkt = pcnet_free_pkt,
  565. };
  566. U_BOOT_DRIVER(eth_pcnet) = {
  567. .name = "eth_pcnet",
  568. .id = UCLASS_ETH,
  569. .bind = pcnet_bind,
  570. .probe = pcnet_probe,
  571. .ops = &pcnet_ops,
  572. .priv_auto = sizeof(struct pcnet_priv),
  573. .plat_auto = sizeof(struct eth_pdata),
  574. .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
  575. };
  576. U_BOOT_PCI_DEVICE(eth_pcnet, supported);
  577. #endif