cgx_intf.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. */
  5. #ifndef __CGX_INTF_H__
  6. #define __CGX_INTF_H__
  7. #define CGX_FIRMWARE_MAJOR_VER 1
  8. #define CGX_FIRMWARE_MINOR_VER 0
  9. /* Register offsets */
  10. #define CGX_CMR_INT 0x87e0e0000040
  11. #define CGX_CMR_SCRATCH0 0x87e0e0001050
  12. #define CGX_CMR_SCRATCH1 0x87e0e0001058
  13. #define CGX_SHIFT(x) (0x1000000 * ((x) & 0x3))
  14. #define CMR_SHIFT(x) (0x40000 * ((x) & 0x3))
  15. /* CGX error types. set for cmd response status as CGX_STAT_FAIL */
  16. enum cgx_error_type {
  17. CGX_ERR_NONE,
  18. CGX_ERR_LMAC_NOT_ENABLED,
  19. CGX_ERR_LMAC_MODE_INVALID,
  20. CGX_ERR_REQUEST_ID_INVALID,
  21. CGX_ERR_PREV_ACK_NOT_CLEAR,
  22. CGX_ERR_PHY_LINK_DOWN,
  23. CGX_ERR_PCS_RESET_FAIL,
  24. CGX_ERR_AN_CPT_FAIL,
  25. CGX_ERR_TX_NOT_IDLE,
  26. CGX_ERR_RX_NOT_IDLE,
  27. CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
  28. CGX_ERR_SPUX_RX_ALIGN_FAIL,
  29. CGX_ERR_SPUX_TX_FAULT,
  30. CGX_ERR_SPUX_RX_FAULT,
  31. CGX_ERR_SPUX_RESET_FAIL,
  32. CGX_ERR_SPUX_AN_RESET_FAIL,
  33. CGX_ERR_SPUX_USX_AN_RESET_FAIL,
  34. CGX_ERR_SMUX_RX_LINK_NOT_OK,
  35. CGX_ERR_PCS_LINK_FAIL,
  36. CGX_ERR_TRAINING_FAIL,
  37. CGX_ERR_RX_EQU_FAIL,
  38. CGX_ERR_SPUX_BER_FAIL,
  39. CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
  40. CGX_ERR_SPUX_MARKER_LOCK_FAIL,
  41. CGX_ERR_SET_FEC_INVALID,
  42. CGX_ERR_SET_FEC_FAIL,
  43. CGX_ERR_MODULE_INVALID,
  44. CGX_ERR_MODULE_NOT_PRESENT,
  45. CGX_ERR_SPEED_CHANGE_INVALID, /* = 28 */
  46. /* FIXME : add more error types when adding support for new modes */
  47. };
  48. /* LINK speed types */
  49. enum cgx_link_speed {
  50. CGX_LINK_NONE,
  51. CGX_LINK_10M,
  52. CGX_LINK_100M,
  53. CGX_LINK_1G,
  54. CGX_LINK_2HG, /* 2.5 Gbps */
  55. CGX_LINK_5G,
  56. CGX_LINK_10G,
  57. CGX_LINK_20G,
  58. CGX_LINK_25G,
  59. CGX_LINK_40G,
  60. CGX_LINK_50G,
  61. CGX_LINK_80G,
  62. CGX_LINK_100G,
  63. CGX_LINK_MAX,
  64. };
  65. /* REQUEST ID types. Input to firmware */
  66. enum cgx_cmd_id {
  67. CGX_CMD_NONE = 0,
  68. CGX_CMD_GET_FW_VER,
  69. CGX_CMD_GET_MAC_ADDR,
  70. CGX_CMD_SET_MTU,
  71. CGX_CMD_GET_LINK_STS, /* optional to user */
  72. CGX_CMD_LINK_BRING_UP, /* = 5 */
  73. CGX_CMD_LINK_BRING_DOWN,
  74. CGX_CMD_INTERNAL_LBK,
  75. CGX_CMD_EXTERNAL_LBK,
  76. CGX_CMD_HIGIG,
  77. CGX_CMD_LINK_STAT_CHANGE, /* = 10 */
  78. CGX_CMD_MODE_CHANGE, /* hot plug support */
  79. CGX_CMD_INTF_SHUTDOWN,
  80. CGX_CMD_GET_MKEX_SIZE,
  81. CGX_CMD_GET_MKEX_PROFILE,
  82. CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */
  83. CGX_CMD_GET_LINK_MODES, /* Supported Link Modes */
  84. CGX_CMD_SET_LINK_MODE,
  85. CGX_CMD_GET_SUPPORTED_FEC,
  86. CGX_CMD_SET_FEC,
  87. CGX_CMD_GET_AN, /* = 20 */
  88. CGX_CMD_SET_AN,
  89. CGX_CMD_GET_ADV_LINK_MODES,
  90. CGX_CMD_GET_ADV_FEC,
  91. CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
  92. CGX_CMD_SET_PHY_MOD_TYPE, /* = 25 */
  93. CGX_CMD_PRBS,
  94. CGX_CMD_DISPLAY_EYE,
  95. CGX_CMD_GET_PHY_FEC_STATS,
  96. CGX_CMD_DISPLAY_SERDES,
  97. CGX_CMD_AN_LOOPBACK, /* = 30 */
  98. CGX_CMD_GET_PERSIST_IGNORE,
  99. CGX_CMD_SET_PERSIST_IGNORE,
  100. CGX_CMD_SET_MAC_ADDR,
  101. };
  102. /* async event ids */
  103. enum cgx_evt_id {
  104. CGX_EVT_NONE,
  105. CGX_EVT_LINK_CHANGE,
  106. };
  107. /* event types - cause of interrupt */
  108. enum cgx_evt_type {
  109. CGX_EVT_ASYNC,
  110. CGX_EVT_CMD_RESP
  111. };
  112. enum cgx_stat {
  113. CGX_STAT_SUCCESS,
  114. CGX_STAT_FAIL
  115. };
  116. enum cgx_cmd_own {
  117. /* default ownership with kernel/uefi/u-boot */
  118. CGX_OWN_NON_SECURE_SW,
  119. /* set by kernel/uefi/u-boot after posting a new request to ATF */
  120. CGX_OWN_FIRMWARE,
  121. };
  122. /* Supported LINK MODE enums
  123. * Each link mode is a bit mask of these
  124. * enums which are represented as bits
  125. */
  126. enum cgx_mode_t {
  127. CGX_MODE_SGMII_BIT = 0,
  128. CGX_MODE_1000_BASEX_BIT,
  129. CGX_MODE_QSGMII_BIT,
  130. CGX_MODE_10G_C2C_BIT,
  131. CGX_MODE_10G_C2M_BIT,
  132. CGX_MODE_10G_KR_BIT,
  133. CGX_MODE_20G_C2C_BIT,
  134. CGX_MODE_25G_C2C_BIT,
  135. CGX_MODE_25G_C2M_BIT,
  136. CGX_MODE_25G_2_C2C_BIT,
  137. CGX_MODE_25G_CR_BIT,
  138. CGX_MODE_25G_KR_BIT,
  139. CGX_MODE_40G_C2C_BIT,
  140. CGX_MODE_40G_C2M_BIT,
  141. CGX_MODE_40G_CR4_BIT,
  142. CGX_MODE_40G_KR4_BIT,
  143. CGX_MODE_40GAUI_C2C_BIT,
  144. CGX_MODE_50G_C2C_BIT,
  145. CGX_MODE_50G_C2M_BIT,
  146. CGX_MODE_50G_4_C2C_BIT,
  147. CGX_MODE_50G_CR_BIT,
  148. CGX_MODE_50G_KR_BIT,
  149. CGX_MODE_80GAUI_C2C_BIT,
  150. CGX_MODE_100G_C2C_BIT,
  151. CGX_MODE_100G_C2M_BIT,
  152. CGX_MODE_100G_CR4_BIT,
  153. CGX_MODE_100G_KR4_BIT,
  154. CGX_MODE_MAX_BIT /* = 29 */
  155. };
  156. /* scratchx(0) CSR used for ATF->non-secure SW communication.
  157. * This acts as the status register
  158. * Provides details on command ack/status, link status, error details
  159. */
  160. /* CAUTION : below structures are placed in order based on the bit positions
  161. * For any updates/new bitfields, corresponding structures needs to be updated
  162. */
  163. struct cgx_evt_sts_s { /* start from bit 0 */
  164. u64 ack:1;
  165. u64 evt_type:1; /* cgx_evt_type */
  166. u64 stat:1; /* cgx_stat */
  167. u64 id:6; /* cgx_evt_id/cgx_cmd_id */
  168. u64 reserved:55;
  169. };
  170. /* all the below structures are in the same memory location of SCRATCHX(0)
  171. * value can be read/written based on command ID
  172. */
  173. /* Resp to command IDs with command status as CGX_STAT_FAIL
  174. * Not applicable for commands :
  175. * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
  176. * check struct cgx_lnk_sts_s comments
  177. */
  178. struct cgx_err_sts_s { /* start from bit 9 */
  179. u64 reserved1:9;
  180. u64 type:10; /* cgx_error_type */
  181. u64 reserved2:35;
  182. };
  183. /* Resp to cmd ID as CGX_CMD_GET_FW_VER with cmd status as CGX_STAT_SUCCESS */
  184. struct cgx_ver_s { /* start from bit 9 */
  185. u64 reserved1:9;
  186. u64 major_ver:4;
  187. u64 minor_ver:4;
  188. u64 reserved2:47;
  189. };
  190. /* Resp to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as CGX_STAT_SUCCESS
  191. * Returns each byte of MAC address in a separate bit field
  192. */
  193. struct cgx_mac_addr_s { /* start from bit 9 */
  194. u64 reserved1:9;
  195. u64 addr_0:8;
  196. u64 addr_1:8;
  197. u64 addr_2:8;
  198. u64 addr_3:8;
  199. u64 addr_4:8;
  200. u64 addr_5:8;
  201. u64 reserved2:7;
  202. };
  203. /* Resp to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
  204. * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
  205. * In case of CGX_STAT_FAIL, it indicates CGX configuration failed when
  206. * processing link up/down/change command. Both err_type and current link status
  207. * will be updated
  208. * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
  209. * link status will be updated
  210. */
  211. struct cgx_lnk_sts_s {
  212. u64 reserved1:9;
  213. u64 link_up:1;
  214. u64 full_duplex:1;
  215. u64 speed:4; /* cgx_link_speed */
  216. u64 err_type:10;
  217. u64 an:1; /* Current AN state : enabled/disabled */
  218. u64 fec:2; /* Current FEC type if enabled, if not 0 */
  219. u64 port:8; /* Share the current port info if required */
  220. u64 mode:8; /* cgx_mode_t enum integer value */
  221. u64 reserved2:20;
  222. };
  223. struct sh_fwd_base_s {
  224. u64 reserved1:9;
  225. u64 addr:55;
  226. };
  227. struct cgx_link_modes_s {
  228. u64 reserved1:9;
  229. u64 modes:55;
  230. };
  231. /* Resp to cmd ID - CGX_CMD_GET_ADV_FEC/CGX_CMD_GET_SUPPORTED_FEC
  232. * fec : 2 bits
  233. * typedef enum cgx_fec_type {
  234. * CGX_FEC_NONE,
  235. * CGX_FEC_BASE_R,
  236. * CGX_FEC_RS
  237. * } fec_type_t;
  238. */
  239. struct cgx_fec_types_s {
  240. u64 reserved1:9;
  241. u64 fec:2;
  242. u64 reserved2:53;
  243. };
  244. /* Resp to cmd ID - CGX_CMD_GET_AN */
  245. struct cgx_get_an_s {
  246. u64 reserved1:9;
  247. u64 an:1;
  248. u64 reserved2:54;
  249. };
  250. /* Resp to cmd ID - CGX_CMD_GET_PHY_MOD_TYPE */
  251. struct cgx_get_phy_mod_type_s {
  252. u64 reserved1:9;
  253. u64 mod:1; /* 0=NRZ, 1=PAM4 */
  254. u64 reserved2:54;
  255. };
  256. /* Resp to cmd ID - CGX_CMD_GET_PERSIST_IGNORE */
  257. struct cgx_get_flash_ignore_s {
  258. uint64_t reserved1:9;
  259. uint64_t ignore:1;
  260. uint64_t reserved2:54;
  261. };
  262. union cgx_rsp_sts {
  263. /* Fixed, applicable for all commands/events */
  264. struct cgx_evt_sts_s evt_sts;
  265. /* response to CGX_CMD_LINK_BRINGUP/DOWN/LINK_CHANGE */
  266. struct cgx_lnk_sts_s link_sts;
  267. /* response to CGX_CMD_GET_FW_VER */
  268. struct cgx_ver_s ver;
  269. /* response to CGX_CMD_GET_MAC_ADDR */
  270. struct cgx_mac_addr_s mac_s;
  271. /* response to CGX_CMD_GET_FWD_BASE */
  272. struct sh_fwd_base_s fwd_base_s;
  273. /* response if evt_status = CMD_FAIL */
  274. struct cgx_err_sts_s err;
  275. /* response to CGX_CMD_GET_SUPPORTED_FEC */
  276. struct cgx_fec_types_s supported_fec;
  277. /* response to CGX_CMD_GET_LINK_MODES */
  278. struct cgx_link_modes_s supported_modes;
  279. /* response to CGX_CMD_GET_ADV_LINK_MODES */
  280. struct cgx_link_modes_s adv_modes;
  281. /* response to CGX_CMD_GET_ADV_FEC */
  282. struct cgx_fec_types_s adv_fec;
  283. /* response to CGX_CMD_GET_AN */
  284. struct cgx_get_an_s an;
  285. /* response to CGX_CMD_GET_PHY_MOD_TYPE */
  286. struct cgx_get_phy_mod_type_s phy_mod_type;
  287. /* response to CGX_CMD_GET_PERSIST_IGNORE */
  288. struct cgx_get_flash_ignore_s persist;
  289. #ifdef NT_FW_CONFIG
  290. /* response to CGX_CMD_GET_MKEX_SIZE */
  291. struct cgx_mcam_profile_sz_s prfl_sz;
  292. /* response to CGX_CMD_GET_MKEX_PROFILE */
  293. struct cgx_mcam_profile_addr_s prfl_addr;
  294. #endif
  295. };
  296. union cgx_scratchx0 {
  297. u64 u;
  298. union cgx_rsp_sts s;
  299. };
  300. /* scratchx(1) CSR used for non-secure SW->ATF communication
  301. * This CSR acts as a command register
  302. */
  303. struct cgx_cmd { /* start from bit 2 */
  304. u64 reserved1:2;
  305. u64 id:6; /* cgx_request_id */
  306. u64 reserved2:56;
  307. };
  308. /* all the below structures are in the same memory location of SCRATCHX(1)
  309. * corresponding arguments for command Id needs to be updated
  310. */
  311. /* Any command using enable/disable as an argument need
  312. * to pass the option via this structure.
  313. * Ex: Loopback, HiGig...
  314. */
  315. struct cgx_ctl_args { /* start from bit 8 */
  316. u64 reserved1:8;
  317. u64 enable:1;
  318. u64 reserved2:55;
  319. };
  320. /* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
  321. struct cgx_mtu_args {
  322. u64 reserved1:8;
  323. u64 size:16;
  324. u64 reserved2:40;
  325. };
  326. /* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
  327. struct cgx_mode_change_args {
  328. uint64_t reserved1:8;
  329. uint64_t speed:4; /* cgx_link_speed enum */
  330. uint64_t duplex:1; /* 0 - full duplex, 1 - half duplex */
  331. uint64_t an:1; /* 0 - disable AN, 1 - enable AN */
  332. uint64_t port:8; /* device port */
  333. uint64_t mode:42;
  334. };
  335. /* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
  336. struct cgx_link_change_args { /* start from bit 8 */
  337. u64 reserved1:8;
  338. u64 link_up:1;
  339. u64 full_duplex:1;
  340. u64 speed:4; /* cgx_link_speed */
  341. u64 reserved2:50;
  342. };
  343. /* command argument to be passed for cmd ID - CGX_CMD_SET_LINK_MODE */
  344. struct cgx_set_mode_args {
  345. u64 reserved1:8;
  346. u64 mode:56;
  347. };
  348. /* command argument to be passed for cmd ID - CGX_CMD_SET_FEC */
  349. struct cgx_set_fec_args {
  350. u64 reserved1:8;
  351. u64 fec:2;
  352. u64 reserved2:54;
  353. };
  354. /* command argument to be passed for cmd ID - CGX_CMD_SET_PHY_MOD_TYPE */
  355. struct cgx_set_phy_mod_args {
  356. u64 reserved1:8;
  357. u64 mod:1; /* 0=NRZ, 1=PAM4 */
  358. u64 reserved2:55;
  359. };
  360. /* command argument to be passed for cmd ID - CGX_CMD_SET_PERSIST_IGNORE */
  361. struct cgx_set_flash_ignore_args {
  362. uint64_t reserved1:8;
  363. uint64_t ignore:1;
  364. uint64_t reserved2:55;
  365. };
  366. /* command argument to be passed for cmd ID - CGX_CMD_SET_MAC_ADDR */
  367. struct cgx_mac_addr_args {
  368. uint64_t reserved1:8;
  369. uint64_t addr:48;
  370. uint64_t pf_id:8;
  371. };
  372. struct cgx_prbs_args {
  373. u64 reserved1:8; /* start from bit 8 */
  374. u64 lane:8;
  375. u64 qlm:8;
  376. u64 stop_on_error:1;
  377. u64 mode:8;
  378. u64 time:31;
  379. };
  380. struct cgx_display_eye_args {
  381. u64 reserved1:8; /* start from bit 8 */
  382. u64 qlm:8;
  383. u64 lane:47;
  384. };
  385. union cgx_cmd_s {
  386. u64 own_status:2; /* cgx_cmd_own */
  387. struct cgx_cmd cmd;
  388. struct cgx_ctl_args cmd_args;
  389. struct cgx_mtu_args mtu_size;
  390. struct cgx_link_change_args lnk_args; /* Input to CGX_CMD_LINK_CHANGE */
  391. struct cgx_set_mode_args mode_args;
  392. struct cgx_mode_change_args mode_change_args;
  393. struct cgx_set_fec_args fec_args;
  394. struct cgx_set_phy_mod_args phy_mod_args;
  395. struct cgx_set_flash_ignore_args persist_args;
  396. struct cgx_mac_addr_args mac_args;
  397. /* any other arg for command id * like : mtu, dmac filtering control */
  398. struct cgx_prbs_args prbs_args;
  399. struct cgx_display_eye_args dsp_eye_args;
  400. };
  401. union cgx_scratchx1 {
  402. u64 u;
  403. union cgx_cmd_s s;
  404. };
  405. #endif /* __CGX_INTF_H__ */