mvneta.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  4. *
  5. * U-Boot version:
  6. * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  7. *
  8. * Based on the Linux version which is:
  9. * Copyright (C) 2012 Marvell
  10. *
  11. * Rami Rosen <rosenr@marvell.com>
  12. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13. */
  14. #include <common.h>
  15. #include <cpu_func.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <net.h>
  19. #include <netdev.h>
  20. #include <config.h>
  21. #include <malloc.h>
  22. #include <asm/cache.h>
  23. #include <asm/global_data.h>
  24. #include <asm/io.h>
  25. #include <dm/device_compat.h>
  26. #include <dm/devres.h>
  27. #include <linux/bitops.h>
  28. #include <linux/bug.h>
  29. #include <linux/delay.h>
  30. #include <linux/errno.h>
  31. #include <phy.h>
  32. #include <miiphy.h>
  33. #include <watchdog.h>
  34. #include <asm/arch/cpu.h>
  35. #include <asm/arch/soc.h>
  36. #include <linux/compat.h>
  37. #include <linux/mbus.h>
  38. #include <asm-generic/gpio.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #if !defined(CONFIG_PHYLIB)
  41. # error Marvell mvneta requires PHYLIB
  42. #endif
  43. #define CONFIG_NR_CPUS 1
  44. #define ETH_HLEN 14 /* Total octets in header */
  45. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  46. #define WRAP (2 + ETH_HLEN + 4 + 32)
  47. #define MTU 1500
  48. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  49. #define MVNETA_SMI_TIMEOUT 10000
  50. /* Registers */
  51. #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
  52. #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
  53. #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
  54. #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
  55. #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
  56. #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
  57. #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
  58. #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
  59. #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
  60. #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
  61. #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
  62. #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
  63. #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
  64. #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
  65. #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
  66. #define MVNETA_PORT_RX_RESET 0x1cc0
  67. #define MVNETA_PORT_RX_DMA_RESET BIT(0)
  68. #define MVNETA_PHY_ADDR 0x2000
  69. #define MVNETA_PHY_ADDR_MASK 0x1f
  70. #define MVNETA_SMI 0x2004
  71. #define MVNETA_PHY_REG_MASK 0x1f
  72. /* SMI register fields */
  73. #define MVNETA_SMI_DATA_OFFS 0 /* Data */
  74. #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
  75. #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  76. #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  77. #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  78. #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
  79. #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
  80. #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
  81. #define MVNETA_MBUS_RETRY 0x2010
  82. #define MVNETA_UNIT_INTR_CAUSE 0x2080
  83. #define MVNETA_UNIT_CONTROL 0x20B0
  84. #define MVNETA_PHY_POLLING_ENABLE BIT(1)
  85. #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
  86. #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
  87. #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
  88. #define MVNETA_WIN_SIZE_MASK (0xffff0000)
  89. #define MVNETA_BASE_ADDR_ENABLE 0x2290
  90. #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
  91. #define MVNETA_PORT_ACCESS_PROTECT 0x2294
  92. #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
  93. #define MVNETA_PORT_CONFIG 0x2400
  94. #define MVNETA_UNI_PROMISC_MODE BIT(0)
  95. #define MVNETA_DEF_RXQ(q) ((q) << 1)
  96. #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
  97. #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
  98. #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
  99. #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
  100. #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
  101. #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
  102. #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
  103. MVNETA_DEF_RXQ_ARP(q) | \
  104. MVNETA_DEF_RXQ_TCP(q) | \
  105. MVNETA_DEF_RXQ_UDP(q) | \
  106. MVNETA_DEF_RXQ_BPDU(q) | \
  107. MVNETA_TX_UNSET_ERR_SUM | \
  108. MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
  109. #define MVNETA_PORT_CONFIG_EXTEND 0x2404
  110. #define MVNETA_MAC_ADDR_LOW 0x2414
  111. #define MVNETA_MAC_ADDR_HIGH 0x2418
  112. #define MVNETA_SDMA_CONFIG 0x241c
  113. #define MVNETA_SDMA_BRST_SIZE_16 4
  114. #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
  115. #define MVNETA_RX_NO_DATA_SWAP BIT(4)
  116. #define MVNETA_TX_NO_DATA_SWAP BIT(5)
  117. #define MVNETA_DESC_SWAP BIT(6)
  118. #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
  119. #define MVNETA_PORT_STATUS 0x2444
  120. #define MVNETA_TX_IN_PRGRS BIT(1)
  121. #define MVNETA_TX_FIFO_EMPTY BIT(8)
  122. #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
  123. #define MVNETA_SERDES_CFG 0x24A0
  124. #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
  125. #define MVNETA_QSGMII_SERDES_PROTO 0x0667
  126. #define MVNETA_TYPE_PRIO 0x24bc
  127. #define MVNETA_FORCE_UNI BIT(21)
  128. #define MVNETA_TXQ_CMD_1 0x24e4
  129. #define MVNETA_TXQ_CMD 0x2448
  130. #define MVNETA_TXQ_DISABLE_SHIFT 8
  131. #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
  132. #define MVNETA_ACC_MODE 0x2500
  133. #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
  134. #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
  135. #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
  136. #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
  137. /* Exception Interrupt Port/Queue Cause register */
  138. #define MVNETA_INTR_NEW_CAUSE 0x25a0
  139. #define MVNETA_INTR_NEW_MASK 0x25a4
  140. /* bits 0..7 = TXQ SENT, one bit per queue.
  141. * bits 8..15 = RXQ OCCUP, one bit per queue.
  142. * bits 16..23 = RXQ FREE, one bit per queue.
  143. * bit 29 = OLD_REG_SUM, see old reg ?
  144. * bit 30 = TX_ERR_SUM, one bit for 4 ports
  145. * bit 31 = MISC_SUM, one bit for 4 ports
  146. */
  147. #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
  148. #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
  149. #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
  150. #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
  151. #define MVNETA_INTR_OLD_CAUSE 0x25a8
  152. #define MVNETA_INTR_OLD_MASK 0x25ac
  153. /* Data Path Port/Queue Cause Register */
  154. #define MVNETA_INTR_MISC_CAUSE 0x25b0
  155. #define MVNETA_INTR_MISC_MASK 0x25b4
  156. #define MVNETA_INTR_ENABLE 0x25b8
  157. #define MVNETA_RXQ_CMD 0x2680
  158. #define MVNETA_RXQ_DISABLE_SHIFT 8
  159. #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
  160. #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
  161. #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
  162. #define MVNETA_GMAC_CTRL_0 0x2c00
  163. #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
  164. #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  165. #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
  166. #define MVNETA_GMAC_CTRL_2 0x2c08
  167. #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
  168. #define MVNETA_GMAC2_PORT_RGMII BIT(4)
  169. #define MVNETA_GMAC2_PORT_RESET BIT(6)
  170. #define MVNETA_GMAC_STATUS 0x2c10
  171. #define MVNETA_GMAC_LINK_UP BIT(0)
  172. #define MVNETA_GMAC_SPEED_1000 BIT(1)
  173. #define MVNETA_GMAC_SPEED_100 BIT(2)
  174. #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
  175. #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
  176. #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
  177. #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
  178. #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
  179. #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
  180. #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
  181. #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
  182. #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
  183. #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
  184. #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
  185. #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
  186. #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
  187. #define MVNETA_GMAC_SET_FC_EN BIT(8)
  188. #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
  189. #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  190. #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
  191. #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
  192. #define MVNETA_MIB_COUNTERS_BASE 0x3080
  193. #define MVNETA_MIB_LATE_COLLISION 0x7c
  194. #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
  195. #define MVNETA_DA_FILT_OTH_MCAST 0x3500
  196. #define MVNETA_DA_FILT_UCAST_BASE 0x3600
  197. #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
  198. #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
  199. #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
  200. #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
  201. #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
  202. #define MVNETA_TXQ_DEC_SENT_SHIFT 16
  203. #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
  204. #define MVNETA_TXQ_SENT_DESC_SHIFT 16
  205. #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
  206. #define MVNETA_PORT_TX_RESET 0x3cf0
  207. #define MVNETA_PORT_TX_DMA_RESET BIT(0)
  208. #define MVNETA_TX_MTU 0x3e0c
  209. #define MVNETA_TX_TOKEN_SIZE 0x3e14
  210. #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
  211. #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
  212. #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  213. /* Descriptor ring Macros */
  214. #define MVNETA_QUEUE_NEXT_DESC(q, index) \
  215. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  216. /* Various constants */
  217. /* Coalescing */
  218. #define MVNETA_TXDONE_COAL_PKTS 16
  219. #define MVNETA_RX_COAL_PKTS 32
  220. #define MVNETA_RX_COAL_USEC 100
  221. /* The two bytes Marvell header. Either contains a special value used
  222. * by Marvell switches when a specific hardware mode is enabled (not
  223. * supported by this driver) or is filled automatically by zeroes on
  224. * the RX side. Those two bytes being at the front of the Ethernet
  225. * header, they allow to have the IP header aligned on a 4 bytes
  226. * boundary automatically: the hardware skips those two bytes on its
  227. * own.
  228. */
  229. #define MVNETA_MH_SIZE 2
  230. #define MVNETA_VLAN_TAG_LEN 4
  231. #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
  232. #define MVNETA_TX_CSUM_MAX_SIZE 9800
  233. #define MVNETA_ACC_MODE_EXT 1
  234. /* Timeout constants */
  235. #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
  236. #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
  237. #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
  238. #define MVNETA_TX_MTU_MAX 0x3ffff
  239. /* Max number of Rx descriptors */
  240. #define MVNETA_MAX_RXD 16
  241. /* Max number of Tx descriptors */
  242. #define MVNETA_MAX_TXD 16
  243. /* descriptor aligned size */
  244. #define MVNETA_DESC_ALIGNED_SIZE 32
  245. struct mvneta_port {
  246. void __iomem *base;
  247. struct mvneta_rx_queue *rxqs;
  248. struct mvneta_tx_queue *txqs;
  249. u8 mcast_count[256];
  250. u16 tx_ring_size;
  251. u16 rx_ring_size;
  252. phy_interface_t phy_interface;
  253. unsigned int link;
  254. unsigned int duplex;
  255. unsigned int speed;
  256. int init;
  257. int phyaddr;
  258. struct phy_device *phydev;
  259. #if CONFIG_IS_ENABLED(DM_GPIO)
  260. struct gpio_desc phy_reset_gpio;
  261. #endif
  262. struct mii_dev *bus;
  263. };
  264. /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
  265. * layout of the transmit and reception DMA descriptors, and their
  266. * layout is therefore defined by the hardware design
  267. */
  268. #define MVNETA_TX_L3_OFF_SHIFT 0
  269. #define MVNETA_TX_IP_HLEN_SHIFT 8
  270. #define MVNETA_TX_L4_UDP BIT(16)
  271. #define MVNETA_TX_L3_IP6 BIT(17)
  272. #define MVNETA_TXD_IP_CSUM BIT(18)
  273. #define MVNETA_TXD_Z_PAD BIT(19)
  274. #define MVNETA_TXD_L_DESC BIT(20)
  275. #define MVNETA_TXD_F_DESC BIT(21)
  276. #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
  277. MVNETA_TXD_L_DESC | \
  278. MVNETA_TXD_F_DESC)
  279. #define MVNETA_TX_L4_CSUM_FULL BIT(30)
  280. #define MVNETA_TX_L4_CSUM_NOT BIT(31)
  281. #define MVNETA_RXD_ERR_CRC 0x0
  282. #define MVNETA_RXD_ERR_SUMMARY BIT(16)
  283. #define MVNETA_RXD_ERR_OVERRUN BIT(17)
  284. #define MVNETA_RXD_ERR_LEN BIT(18)
  285. #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
  286. #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
  287. #define MVNETA_RXD_L3_IP4 BIT(25)
  288. #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
  289. #define MVNETA_RXD_L4_CSUM_OK BIT(30)
  290. struct mvneta_tx_desc {
  291. u32 command; /* Options used by HW for packet transmitting.*/
  292. u16 reserverd1; /* csum_l4 (for future use) */
  293. u16 data_size; /* Data size of transmitted packet in bytes */
  294. u32 buf_phys_addr; /* Physical addr of transmitted buffer */
  295. u32 reserved2; /* hw_cmd - (for future use, PMT) */
  296. u32 reserved3[4]; /* Reserved - (for future use) */
  297. };
  298. struct mvneta_rx_desc {
  299. u32 status; /* Info about received packet */
  300. u16 reserved1; /* pnc_info - (for future use, PnC) */
  301. u16 data_size; /* Size of received packet in bytes */
  302. u32 buf_phys_addr; /* Physical address of the buffer */
  303. u32 reserved2; /* pnc_flow_id (for future use, PnC) */
  304. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  305. u16 reserved3; /* prefetch_cmd, for future use */
  306. u16 reserved4; /* csum_l4 - (for future use, PnC) */
  307. u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
  308. u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
  309. };
  310. struct mvneta_tx_queue {
  311. /* Number of this TX queue, in the range 0-7 */
  312. u8 id;
  313. /* Number of TX DMA descriptors in the descriptor ring */
  314. int size;
  315. /* Index of last TX DMA descriptor that was inserted */
  316. int txq_put_index;
  317. /* Index of the TX DMA descriptor to be cleaned up */
  318. int txq_get_index;
  319. /* Virtual address of the TX DMA descriptors array */
  320. struct mvneta_tx_desc *descs;
  321. /* DMA address of the TX DMA descriptors array */
  322. dma_addr_t descs_phys;
  323. /* Index of the last TX DMA descriptor */
  324. int last_desc;
  325. /* Index of the next TX DMA descriptor to process */
  326. int next_desc_to_proc;
  327. };
  328. struct mvneta_rx_queue {
  329. /* rx queue number, in the range 0-7 */
  330. u8 id;
  331. /* num of rx descriptors in the rx descriptor ring */
  332. int size;
  333. /* Virtual address of the RX DMA descriptors array */
  334. struct mvneta_rx_desc *descs;
  335. /* DMA address of the RX DMA descriptors array */
  336. dma_addr_t descs_phys;
  337. /* Index of the last RX DMA descriptor */
  338. int last_desc;
  339. /* Index of the next RX DMA descriptor to process */
  340. int next_desc_to_proc;
  341. };
  342. /* U-Boot doesn't use the queues, so set the number to 1 */
  343. static int rxq_number = 1;
  344. static int txq_number = 1;
  345. static int rxq_def;
  346. struct buffer_location {
  347. struct mvneta_tx_desc *tx_descs;
  348. struct mvneta_rx_desc *rx_descs;
  349. u32 rx_buffers;
  350. };
  351. /*
  352. * All 4 interfaces use the same global buffer, since only one interface
  353. * can be enabled at once
  354. */
  355. static struct buffer_location buffer_loc;
  356. /*
  357. * Page table entries are set to 1MB, or multiples of 1MB
  358. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  359. */
  360. #define BD_SPACE (1 << 20)
  361. /*
  362. * Dummy implementation that can be overwritten by a board
  363. * specific function
  364. */
  365. __weak int board_network_enable(struct mii_dev *bus)
  366. {
  367. return 0;
  368. }
  369. /* Utility/helper methods */
  370. /* Write helper method */
  371. static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
  372. {
  373. writel(data, pp->base + offset);
  374. }
  375. /* Read helper method */
  376. static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
  377. {
  378. return readl(pp->base + offset);
  379. }
  380. /* Clear all MIB counters */
  381. static void mvneta_mib_counters_clear(struct mvneta_port *pp)
  382. {
  383. int i;
  384. /* Perform dummy reads from MIB counters */
  385. for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
  386. mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
  387. }
  388. /* Rx descriptors helper methods */
  389. /* Checks whether the RX descriptor having this status is both the first
  390. * and the last descriptor for the RX packet. Each RX packet is currently
  391. * received through a single RX descriptor, so not having each RX
  392. * descriptor with its first and last bits set is an error
  393. */
  394. static int mvneta_rxq_desc_is_first_last(u32 status)
  395. {
  396. return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
  397. MVNETA_RXD_FIRST_LAST_DESC;
  398. }
  399. /* Add number of descriptors ready to receive new packets */
  400. static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
  401. struct mvneta_rx_queue *rxq,
  402. int ndescs)
  403. {
  404. /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
  405. * be added at once
  406. */
  407. while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
  408. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  409. (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
  410. MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  411. ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
  412. }
  413. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  414. (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  415. }
  416. /* Get number of RX descriptors occupied by received packets */
  417. static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
  418. struct mvneta_rx_queue *rxq)
  419. {
  420. u32 val;
  421. val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
  422. return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
  423. }
  424. /* Update num of rx desc called upon return from rx path or
  425. * from mvneta_rxq_drop_pkts().
  426. */
  427. static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
  428. struct mvneta_rx_queue *rxq,
  429. int rx_done, int rx_filled)
  430. {
  431. u32 val;
  432. if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
  433. val = rx_done |
  434. (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
  435. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  436. return;
  437. }
  438. /* Only 255 descriptors can be added at once */
  439. while ((rx_done > 0) || (rx_filled > 0)) {
  440. if (rx_done <= 0xff) {
  441. val = rx_done;
  442. rx_done = 0;
  443. } else {
  444. val = 0xff;
  445. rx_done -= 0xff;
  446. }
  447. if (rx_filled <= 0xff) {
  448. val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  449. rx_filled = 0;
  450. } else {
  451. val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  452. rx_filled -= 0xff;
  453. }
  454. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  455. }
  456. }
  457. /* Get pointer to next RX descriptor to be processed by SW */
  458. static struct mvneta_rx_desc *
  459. mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
  460. {
  461. int rx_desc = rxq->next_desc_to_proc;
  462. rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
  463. return rxq->descs + rx_desc;
  464. }
  465. /* Tx descriptors helper methods */
  466. /* Update HW with number of TX descriptors to be sent */
  467. static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
  468. struct mvneta_tx_queue *txq,
  469. int pend_desc)
  470. {
  471. u32 val;
  472. /* Only 255 descriptors can be added at once ; Assume caller
  473. * process TX descriptors in quanta less than 256
  474. */
  475. val = pend_desc;
  476. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  477. }
  478. /* Get pointer to next TX descriptor to be processed (send) by HW */
  479. static struct mvneta_tx_desc *
  480. mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
  481. {
  482. int tx_desc = txq->next_desc_to_proc;
  483. txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
  484. return txq->descs + tx_desc;
  485. }
  486. /* Set rxq buf size */
  487. static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
  488. struct mvneta_rx_queue *rxq,
  489. int buf_size)
  490. {
  491. u32 val;
  492. val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
  493. val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
  494. val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
  495. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
  496. }
  497. static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
  498. {
  499. /* phy_addr is set to invalid value for fixed link */
  500. return pp->phyaddr > PHY_MAX_ADDR;
  501. }
  502. /* Start the Ethernet port RX and TX activity */
  503. static void mvneta_port_up(struct mvneta_port *pp)
  504. {
  505. int queue;
  506. u32 q_map;
  507. /* Enable all initialized TXs. */
  508. mvneta_mib_counters_clear(pp);
  509. q_map = 0;
  510. for (queue = 0; queue < txq_number; queue++) {
  511. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  512. if (txq->descs != NULL)
  513. q_map |= (1 << queue);
  514. }
  515. mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
  516. /* Enable all initialized RXQs. */
  517. q_map = 0;
  518. for (queue = 0; queue < rxq_number; queue++) {
  519. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  520. if (rxq->descs != NULL)
  521. q_map |= (1 << queue);
  522. }
  523. mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
  524. }
  525. /* Stop the Ethernet port activity */
  526. static void mvneta_port_down(struct mvneta_port *pp)
  527. {
  528. u32 val;
  529. int count;
  530. /* Stop Rx port activity. Check port Rx activity. */
  531. val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
  532. /* Issue stop command for active channels only */
  533. if (val != 0)
  534. mvreg_write(pp, MVNETA_RXQ_CMD,
  535. val << MVNETA_RXQ_DISABLE_SHIFT);
  536. /* Wait for all Rx activity to terminate. */
  537. count = 0;
  538. do {
  539. if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
  540. dev_warn(pp->phydev->dev,
  541. "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
  542. val);
  543. break;
  544. }
  545. mdelay(1);
  546. val = mvreg_read(pp, MVNETA_RXQ_CMD);
  547. } while (val & 0xff);
  548. /* Stop Tx port activity. Check port Tx activity. Issue stop
  549. * command for active channels only
  550. */
  551. val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
  552. if (val != 0)
  553. mvreg_write(pp, MVNETA_TXQ_CMD,
  554. (val << MVNETA_TXQ_DISABLE_SHIFT));
  555. /* Wait for all Tx activity to terminate. */
  556. count = 0;
  557. do {
  558. if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
  559. dev_warn(pp->phydev->dev,
  560. "TIMEOUT for TX stopped status=0x%08x\n",
  561. val);
  562. break;
  563. }
  564. mdelay(1);
  565. /* Check TX Command reg that all Txqs are stopped */
  566. val = mvreg_read(pp, MVNETA_TXQ_CMD);
  567. } while (val & 0xff);
  568. /* Double check to verify that TX FIFO is empty */
  569. count = 0;
  570. do {
  571. if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
  572. dev_warn(pp->phydev->dev,
  573. "TX FIFO empty timeout status=0x08%x\n",
  574. val);
  575. break;
  576. }
  577. mdelay(1);
  578. val = mvreg_read(pp, MVNETA_PORT_STATUS);
  579. } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
  580. (val & MVNETA_TX_IN_PRGRS));
  581. udelay(200);
  582. }
  583. /* Enable the port by setting the port enable bit of the MAC control register */
  584. static void mvneta_port_enable(struct mvneta_port *pp)
  585. {
  586. u32 val;
  587. /* Enable port */
  588. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  589. val |= MVNETA_GMAC0_PORT_ENABLE;
  590. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  591. }
  592. /* Disable the port and wait for about 200 usec before retuning */
  593. static void mvneta_port_disable(struct mvneta_port *pp)
  594. {
  595. u32 val;
  596. /* Reset the Enable bit in the Serial Control Register */
  597. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  598. val &= ~MVNETA_GMAC0_PORT_ENABLE;
  599. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  600. udelay(200);
  601. }
  602. /* Multicast tables methods */
  603. /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
  604. static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
  605. {
  606. int offset;
  607. u32 val;
  608. if (queue == -1) {
  609. val = 0;
  610. } else {
  611. val = 0x1 | (queue << 1);
  612. val |= (val << 24) | (val << 16) | (val << 8);
  613. }
  614. for (offset = 0; offset <= 0xc; offset += 4)
  615. mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
  616. }
  617. /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
  618. static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
  619. {
  620. int offset;
  621. u32 val;
  622. if (queue == -1) {
  623. val = 0;
  624. } else {
  625. val = 0x1 | (queue << 1);
  626. val |= (val << 24) | (val << 16) | (val << 8);
  627. }
  628. for (offset = 0; offset <= 0xfc; offset += 4)
  629. mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
  630. }
  631. /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
  632. static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
  633. {
  634. int offset;
  635. u32 val;
  636. if (queue == -1) {
  637. memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
  638. val = 0;
  639. } else {
  640. memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
  641. val = 0x1 | (queue << 1);
  642. val |= (val << 24) | (val << 16) | (val << 8);
  643. }
  644. for (offset = 0; offset <= 0xfc; offset += 4)
  645. mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
  646. }
  647. /* This method sets defaults to the NETA port:
  648. * Clears interrupt Cause and Mask registers.
  649. * Clears all MAC tables.
  650. * Sets defaults to all registers.
  651. * Resets RX and TX descriptor rings.
  652. * Resets PHY.
  653. * This method can be called after mvneta_port_down() to return the port
  654. * settings to defaults.
  655. */
  656. static void mvneta_defaults_set(struct mvneta_port *pp)
  657. {
  658. int cpu;
  659. int queue;
  660. u32 val;
  661. /* Clear all Cause registers */
  662. mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
  663. mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
  664. mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
  665. /* Mask all interrupts */
  666. mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
  667. mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
  668. mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
  669. mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
  670. /* Enable MBUS Retry bit16 */
  671. mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
  672. /* Set CPU queue access map - all CPUs have access to all RX
  673. * queues and to all TX queues
  674. */
  675. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
  676. mvreg_write(pp, MVNETA_CPU_MAP(cpu),
  677. (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
  678. MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
  679. /* Reset RX and TX DMAs */
  680. mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
  681. mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
  682. /* Disable Legacy WRR, Disable EJP, Release from reset */
  683. mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
  684. for (queue = 0; queue < txq_number; queue++) {
  685. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
  686. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
  687. }
  688. mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
  689. mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
  690. /* Set Port Acceleration Mode */
  691. val = MVNETA_ACC_MODE_EXT;
  692. mvreg_write(pp, MVNETA_ACC_MODE, val);
  693. /* Update val of portCfg register accordingly with all RxQueue types */
  694. val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
  695. mvreg_write(pp, MVNETA_PORT_CONFIG, val);
  696. val = 0;
  697. mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
  698. mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
  699. /* Build PORT_SDMA_CONFIG_REG */
  700. val = 0;
  701. /* Default burst size */
  702. val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  703. val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  704. val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
  705. /* Assign port SDMA configuration */
  706. mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
  707. /* Enable PHY polling in hardware if not in fixed-link mode */
  708. if (!mvneta_port_is_fixed_link(pp)) {
  709. val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
  710. val |= MVNETA_PHY_POLLING_ENABLE;
  711. mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
  712. }
  713. mvneta_set_ucast_table(pp, -1);
  714. mvneta_set_special_mcast_table(pp, -1);
  715. mvneta_set_other_mcast_table(pp, -1);
  716. }
  717. /* Set unicast address */
  718. static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
  719. int queue)
  720. {
  721. unsigned int unicast_reg;
  722. unsigned int tbl_offset;
  723. unsigned int reg_offset;
  724. /* Locate the Unicast table entry */
  725. last_nibble = (0xf & last_nibble);
  726. /* offset from unicast tbl base */
  727. tbl_offset = (last_nibble / 4) * 4;
  728. /* offset within the above reg */
  729. reg_offset = last_nibble % 4;
  730. unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
  731. if (queue == -1) {
  732. /* Clear accepts frame bit at specified unicast DA tbl entry */
  733. unicast_reg &= ~(0xff << (8 * reg_offset));
  734. } else {
  735. unicast_reg &= ~(0xff << (8 * reg_offset));
  736. unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
  737. }
  738. mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
  739. }
  740. /* Set mac address */
  741. static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
  742. int queue)
  743. {
  744. unsigned int mac_h;
  745. unsigned int mac_l;
  746. if (queue != -1) {
  747. mac_l = (addr[4] << 8) | (addr[5]);
  748. mac_h = (addr[0] << 24) | (addr[1] << 16) |
  749. (addr[2] << 8) | (addr[3] << 0);
  750. mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
  751. mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
  752. }
  753. /* Accept frames of this address */
  754. mvneta_set_ucast_addr(pp, addr[5], queue);
  755. }
  756. static int mvneta_write_hwaddr(struct udevice *dev)
  757. {
  758. mvneta_mac_addr_set(dev_get_priv(dev),
  759. ((struct eth_pdata *)dev_get_plat(dev))->enetaddr,
  760. rxq_def);
  761. return 0;
  762. }
  763. /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
  764. static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
  765. u32 phys_addr, u32 cookie)
  766. {
  767. rx_desc->buf_cookie = cookie;
  768. rx_desc->buf_phys_addr = phys_addr;
  769. }
  770. /* Decrement sent descriptors counter */
  771. static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
  772. struct mvneta_tx_queue *txq,
  773. int sent_desc)
  774. {
  775. u32 val;
  776. /* Only 255 TX descriptors can be updated at once */
  777. while (sent_desc > 0xff) {
  778. val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
  779. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  780. sent_desc = sent_desc - 0xff;
  781. }
  782. val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
  783. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  784. }
  785. /* Get number of TX descriptors already sent by HW */
  786. static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
  787. struct mvneta_tx_queue *txq)
  788. {
  789. u32 val;
  790. int sent_desc;
  791. val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
  792. sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
  793. MVNETA_TXQ_SENT_DESC_SHIFT;
  794. return sent_desc;
  795. }
  796. /* Display more error info */
  797. static void mvneta_rx_error(struct mvneta_port *pp,
  798. struct mvneta_rx_desc *rx_desc)
  799. {
  800. u32 status = rx_desc->status;
  801. if (!mvneta_rxq_desc_is_first_last(status)) {
  802. dev_err(pp->phydev->dev,
  803. "bad rx status %08x (buffer oversize), size=%d\n",
  804. status, rx_desc->data_size);
  805. return;
  806. }
  807. switch (status & MVNETA_RXD_ERR_CODE_MASK) {
  808. case MVNETA_RXD_ERR_CRC:
  809. dev_err(pp->phydev->dev,
  810. "bad rx status %08x (crc error), size=%d\n", status,
  811. rx_desc->data_size);
  812. break;
  813. case MVNETA_RXD_ERR_OVERRUN:
  814. dev_err(pp->phydev->dev,
  815. "bad rx status %08x (overrun error), size=%d\n", status,
  816. rx_desc->data_size);
  817. break;
  818. case MVNETA_RXD_ERR_LEN:
  819. dev_err(pp->phydev->dev,
  820. "bad rx status %08x (max frame length error), size=%d\n",
  821. status, rx_desc->data_size);
  822. break;
  823. case MVNETA_RXD_ERR_RESOURCE:
  824. dev_err(pp->phydev->dev,
  825. "bad rx status %08x (resource error), size=%d\n",
  826. status, rx_desc->data_size);
  827. break;
  828. }
  829. }
  830. static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
  831. int rxq)
  832. {
  833. return &pp->rxqs[rxq];
  834. }
  835. /* Drop packets received by the RXQ and free buffers */
  836. static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
  837. struct mvneta_rx_queue *rxq)
  838. {
  839. int rx_done;
  840. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  841. if (rx_done)
  842. mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
  843. }
  844. /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
  845. static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
  846. int num)
  847. {
  848. int i;
  849. for (i = 0; i < num; i++) {
  850. u32 addr;
  851. /* U-Boot special: Fill in the rx buffer addresses */
  852. addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
  853. mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
  854. }
  855. /* Add this number of RX descriptors as non occupied (ready to
  856. * get packets)
  857. */
  858. mvneta_rxq_non_occup_desc_add(pp, rxq, i);
  859. return 0;
  860. }
  861. /* Rx/Tx queue initialization/cleanup methods */
  862. /* Create a specified RX queue */
  863. static int mvneta_rxq_init(struct mvneta_port *pp,
  864. struct mvneta_rx_queue *rxq)
  865. {
  866. rxq->size = pp->rx_ring_size;
  867. /* Allocate memory for RX descriptors */
  868. rxq->descs_phys = (dma_addr_t)rxq->descs;
  869. if (rxq->descs == NULL)
  870. return -ENOMEM;
  871. WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
  872. rxq->last_desc = rxq->size - 1;
  873. /* Set Rx descriptors queue starting address */
  874. mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
  875. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
  876. /* Fill RXQ with buffers from RX pool */
  877. mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
  878. mvneta_rxq_fill(pp, rxq, rxq->size);
  879. return 0;
  880. }
  881. /* Cleanup Rx queue */
  882. static void mvneta_rxq_deinit(struct mvneta_port *pp,
  883. struct mvneta_rx_queue *rxq)
  884. {
  885. mvneta_rxq_drop_pkts(pp, rxq);
  886. rxq->descs = NULL;
  887. rxq->last_desc = 0;
  888. rxq->next_desc_to_proc = 0;
  889. rxq->descs_phys = 0;
  890. }
  891. /* Create and initialize a tx queue */
  892. static int mvneta_txq_init(struct mvneta_port *pp,
  893. struct mvneta_tx_queue *txq)
  894. {
  895. txq->size = pp->tx_ring_size;
  896. /* Allocate memory for TX descriptors */
  897. txq->descs_phys = (dma_addr_t)txq->descs;
  898. if (txq->descs == NULL)
  899. return -ENOMEM;
  900. WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
  901. txq->last_desc = txq->size - 1;
  902. /* Set maximum bandwidth for enabled TXQs */
  903. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
  904. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
  905. /* Set Tx descriptors queue starting address */
  906. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
  907. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
  908. return 0;
  909. }
  910. /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
  911. static void mvneta_txq_deinit(struct mvneta_port *pp,
  912. struct mvneta_tx_queue *txq)
  913. {
  914. txq->descs = NULL;
  915. txq->last_desc = 0;
  916. txq->next_desc_to_proc = 0;
  917. txq->descs_phys = 0;
  918. /* Set minimum bandwidth for disabled TXQs */
  919. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
  920. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
  921. /* Set Tx descriptors queue starting address and size */
  922. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
  923. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
  924. }
  925. /* Cleanup all Tx queues */
  926. static void mvneta_cleanup_txqs(struct mvneta_port *pp)
  927. {
  928. int queue;
  929. for (queue = 0; queue < txq_number; queue++)
  930. mvneta_txq_deinit(pp, &pp->txqs[queue]);
  931. }
  932. /* Cleanup all Rx queues */
  933. static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
  934. {
  935. int queue;
  936. for (queue = 0; queue < rxq_number; queue++)
  937. mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
  938. }
  939. /* Init all Rx queues */
  940. static int mvneta_setup_rxqs(struct mvneta_port *pp)
  941. {
  942. int queue;
  943. for (queue = 0; queue < rxq_number; queue++) {
  944. int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
  945. if (err) {
  946. dev_err(pp->phydev->dev, "%s: can't create rxq=%d\n",
  947. __func__, queue);
  948. mvneta_cleanup_rxqs(pp);
  949. return err;
  950. }
  951. }
  952. return 0;
  953. }
  954. /* Init all tx queues */
  955. static int mvneta_setup_txqs(struct mvneta_port *pp)
  956. {
  957. int queue;
  958. for (queue = 0; queue < txq_number; queue++) {
  959. int err = mvneta_txq_init(pp, &pp->txqs[queue]);
  960. if (err) {
  961. dev_err(pp->phydev->dev, "%s: can't create txq=%d\n",
  962. __func__, queue);
  963. mvneta_cleanup_txqs(pp);
  964. return err;
  965. }
  966. }
  967. return 0;
  968. }
  969. static void mvneta_start_dev(struct mvneta_port *pp)
  970. {
  971. /* start the Rx/Tx activity */
  972. mvneta_port_enable(pp);
  973. }
  974. static void mvneta_adjust_link(struct udevice *dev)
  975. {
  976. struct mvneta_port *pp = dev_get_priv(dev);
  977. struct phy_device *phydev = pp->phydev;
  978. int status_change = 0;
  979. if (mvneta_port_is_fixed_link(pp)) {
  980. debug("Using fixed link, skip link adjust\n");
  981. return;
  982. }
  983. if (phydev->link) {
  984. if ((pp->speed != phydev->speed) ||
  985. (pp->duplex != phydev->duplex)) {
  986. u32 val;
  987. val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  988. val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  989. MVNETA_GMAC_CONFIG_GMII_SPEED |
  990. MVNETA_GMAC_CONFIG_FULL_DUPLEX |
  991. MVNETA_GMAC_AN_SPEED_EN |
  992. MVNETA_GMAC_AN_DUPLEX_EN);
  993. if (phydev->duplex)
  994. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  995. if (phydev->speed == SPEED_1000)
  996. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  997. else
  998. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  999. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1000. pp->duplex = phydev->duplex;
  1001. pp->speed = phydev->speed;
  1002. }
  1003. }
  1004. if (phydev->link != pp->link) {
  1005. if (!phydev->link) {
  1006. pp->duplex = -1;
  1007. pp->speed = 0;
  1008. }
  1009. pp->link = phydev->link;
  1010. status_change = 1;
  1011. }
  1012. if (status_change) {
  1013. if (phydev->link) {
  1014. u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  1015. val |= (MVNETA_GMAC_FORCE_LINK_PASS |
  1016. MVNETA_GMAC_FORCE_LINK_DOWN);
  1017. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1018. mvneta_port_up(pp);
  1019. } else {
  1020. mvneta_port_down(pp);
  1021. }
  1022. }
  1023. }
  1024. static int mvneta_open(struct udevice *dev)
  1025. {
  1026. struct mvneta_port *pp = dev_get_priv(dev);
  1027. int ret;
  1028. ret = mvneta_setup_rxqs(pp);
  1029. if (ret)
  1030. return ret;
  1031. ret = mvneta_setup_txqs(pp);
  1032. if (ret)
  1033. return ret;
  1034. mvneta_adjust_link(dev);
  1035. mvneta_start_dev(pp);
  1036. return 0;
  1037. }
  1038. /* Initialize hw */
  1039. static int mvneta_init2(struct mvneta_port *pp)
  1040. {
  1041. int queue;
  1042. /* Disable port */
  1043. mvneta_port_disable(pp);
  1044. /* Set port default values */
  1045. mvneta_defaults_set(pp);
  1046. pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
  1047. GFP_KERNEL);
  1048. if (!pp->txqs)
  1049. return -ENOMEM;
  1050. /* U-Boot special: use preallocated area */
  1051. pp->txqs[0].descs = buffer_loc.tx_descs;
  1052. /* Initialize TX descriptor rings */
  1053. for (queue = 0; queue < txq_number; queue++) {
  1054. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  1055. txq->id = queue;
  1056. txq->size = pp->tx_ring_size;
  1057. }
  1058. pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
  1059. GFP_KERNEL);
  1060. if (!pp->rxqs) {
  1061. kfree(pp->txqs);
  1062. return -ENOMEM;
  1063. }
  1064. /* U-Boot special: use preallocated area */
  1065. pp->rxqs[0].descs = buffer_loc.rx_descs;
  1066. /* Create Rx descriptor rings */
  1067. for (queue = 0; queue < rxq_number; queue++) {
  1068. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  1069. rxq->id = queue;
  1070. rxq->size = pp->rx_ring_size;
  1071. }
  1072. return 0;
  1073. }
  1074. /* platform glue : initialize decoding windows */
  1075. /*
  1076. * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
  1077. * First layer is: GbE Address window that resides inside the GBE unit,
  1078. * Second layer is: Fabric address window which is located in the NIC400
  1079. * (South Fabric).
  1080. * To simplify the address decode configuration for Armada3700, we bypass the
  1081. * first layer of GBE decode window by setting the first window to 4GB.
  1082. */
  1083. static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
  1084. {
  1085. /*
  1086. * Set window size to 4GB, to bypass GBE address decode, leave the
  1087. * work to MBUS decode window
  1088. */
  1089. mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
  1090. /* Enable GBE address decode window 0 by set bit 0 to 0 */
  1091. clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
  1092. MVNETA_BASE_ADDR_ENABLE_BIT);
  1093. /* Set GBE address decode window 0 to full Access (read or write) */
  1094. setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
  1095. MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
  1096. }
  1097. static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
  1098. {
  1099. const struct mbus_dram_target_info *dram;
  1100. u32 win_enable;
  1101. u32 win_protect;
  1102. int i;
  1103. dram = mvebu_mbus_dram_info();
  1104. for (i = 0; i < 6; i++) {
  1105. mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
  1106. mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
  1107. if (i < 4)
  1108. mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
  1109. }
  1110. win_enable = 0x3f;
  1111. win_protect = 0;
  1112. for (i = 0; i < dram->num_cs; i++) {
  1113. const struct mbus_dram_window *cs = dram->cs + i;
  1114. mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
  1115. (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
  1116. mvreg_write(pp, MVNETA_WIN_SIZE(i),
  1117. (cs->size - 1) & 0xffff0000);
  1118. win_enable &= ~(1 << i);
  1119. win_protect |= 3 << (2 * i);
  1120. }
  1121. mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
  1122. }
  1123. /* Power up the port */
  1124. static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
  1125. {
  1126. u32 ctrl;
  1127. /* MAC Cause register should be cleared */
  1128. mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
  1129. ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  1130. /* Even though it might look weird, when we're configured in
  1131. * SGMII or QSGMII mode, the RGMII bit needs to be set.
  1132. */
  1133. switch (phy_mode) {
  1134. case PHY_INTERFACE_MODE_QSGMII:
  1135. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
  1136. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1137. break;
  1138. case PHY_INTERFACE_MODE_SGMII:
  1139. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
  1140. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1141. break;
  1142. case PHY_INTERFACE_MODE_RGMII:
  1143. case PHY_INTERFACE_MODE_RGMII_ID:
  1144. ctrl |= MVNETA_GMAC2_PORT_RGMII;
  1145. break;
  1146. default:
  1147. return -EINVAL;
  1148. }
  1149. /* Cancel Port Reset */
  1150. ctrl &= ~MVNETA_GMAC2_PORT_RESET;
  1151. mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
  1152. while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
  1153. MVNETA_GMAC2_PORT_RESET) != 0)
  1154. continue;
  1155. return 0;
  1156. }
  1157. /* Device initialization routine */
  1158. static int mvneta_init(struct udevice *dev)
  1159. {
  1160. struct eth_pdata *pdata = dev_get_plat(dev);
  1161. struct mvneta_port *pp = dev_get_priv(dev);
  1162. int err;
  1163. pp->tx_ring_size = MVNETA_MAX_TXD;
  1164. pp->rx_ring_size = MVNETA_MAX_RXD;
  1165. err = mvneta_init2(pp);
  1166. if (err < 0) {
  1167. dev_err(dev, "can't init eth hal\n");
  1168. return err;
  1169. }
  1170. mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
  1171. err = mvneta_port_power_up(pp, pp->phy_interface);
  1172. if (err < 0) {
  1173. dev_err(dev, "can't power up port\n");
  1174. return err;
  1175. }
  1176. /* Call open() now as it needs to be done before runing send() */
  1177. mvneta_open(dev);
  1178. return 0;
  1179. }
  1180. /* U-Boot only functions follow here */
  1181. /* SMI / MDIO functions */
  1182. static int smi_wait_ready(struct mvneta_port *pp)
  1183. {
  1184. u32 timeout = MVNETA_SMI_TIMEOUT;
  1185. u32 smi_reg;
  1186. /* wait till the SMI is not busy */
  1187. do {
  1188. /* read smi register */
  1189. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1190. if (timeout-- == 0) {
  1191. printf("Error: SMI busy timeout\n");
  1192. return -EFAULT;
  1193. }
  1194. } while (smi_reg & MVNETA_SMI_BUSY);
  1195. return 0;
  1196. }
  1197. /*
  1198. * mvneta_mdio_read - miiphy_read callback function.
  1199. *
  1200. * Returns 16bit phy register value, or 0xffff on error
  1201. */
  1202. static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  1203. {
  1204. struct mvneta_port *pp = bus->priv;
  1205. u32 smi_reg;
  1206. u32 timeout;
  1207. /* check parameters */
  1208. if (addr > MVNETA_PHY_ADDR_MASK) {
  1209. printf("Error: Invalid PHY address %d\n", addr);
  1210. return -EFAULT;
  1211. }
  1212. if (reg > MVNETA_PHY_REG_MASK) {
  1213. printf("Err: Invalid register offset %d\n", reg);
  1214. return -EFAULT;
  1215. }
  1216. /* wait till the SMI is not busy */
  1217. if (smi_wait_ready(pp) < 0)
  1218. return -EFAULT;
  1219. /* fill the phy address and regiser offset and read opcode */
  1220. smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1221. | (reg << MVNETA_SMI_REG_ADDR_OFFS)
  1222. | MVNETA_SMI_OPCODE_READ;
  1223. /* write the smi register */
  1224. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1225. /* wait till read value is ready */
  1226. timeout = MVNETA_SMI_TIMEOUT;
  1227. do {
  1228. /* read smi register */
  1229. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1230. if (timeout-- == 0) {
  1231. printf("Err: SMI read ready timeout\n");
  1232. return -EFAULT;
  1233. }
  1234. } while (!(smi_reg & MVNETA_SMI_READ_VALID));
  1235. /* Wait for the data to update in the SMI register */
  1236. for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
  1237. ;
  1238. return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
  1239. }
  1240. /*
  1241. * mvneta_mdio_write - miiphy_write callback function.
  1242. *
  1243. * Returns 0 if write succeed, -EINVAL on bad parameters
  1244. * -ETIME on timeout
  1245. */
  1246. static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  1247. u16 value)
  1248. {
  1249. struct mvneta_port *pp = bus->priv;
  1250. u32 smi_reg;
  1251. /* check parameters */
  1252. if (addr > MVNETA_PHY_ADDR_MASK) {
  1253. printf("Error: Invalid PHY address %d\n", addr);
  1254. return -EFAULT;
  1255. }
  1256. if (reg > MVNETA_PHY_REG_MASK) {
  1257. printf("Err: Invalid register offset %d\n", reg);
  1258. return -EFAULT;
  1259. }
  1260. /* wait till the SMI is not busy */
  1261. if (smi_wait_ready(pp) < 0)
  1262. return -EFAULT;
  1263. /* fill the phy addr and reg offset and write opcode and data */
  1264. smi_reg = value << MVNETA_SMI_DATA_OFFS;
  1265. smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1266. | (reg << MVNETA_SMI_REG_ADDR_OFFS);
  1267. smi_reg &= ~MVNETA_SMI_OPCODE_READ;
  1268. /* write the smi register */
  1269. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1270. return 0;
  1271. }
  1272. static int mvneta_start(struct udevice *dev)
  1273. {
  1274. struct mvneta_port *pp = dev_get_priv(dev);
  1275. struct phy_device *phydev;
  1276. mvneta_port_power_up(pp, pp->phy_interface);
  1277. if (!pp->init || pp->link == 0) {
  1278. if (mvneta_port_is_fixed_link(pp)) {
  1279. u32 val;
  1280. pp->init = 1;
  1281. pp->link = 1;
  1282. mvneta_init(dev);
  1283. val = MVNETA_GMAC_FORCE_LINK_UP |
  1284. MVNETA_GMAC_IB_BYPASS_AN_EN |
  1285. MVNETA_GMAC_SET_FC_EN |
  1286. MVNETA_GMAC_ADVERT_FC_EN |
  1287. MVNETA_GMAC_SAMPLE_TX_CFG_EN;
  1288. if (pp->duplex)
  1289. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  1290. if (pp->speed == SPEED_1000)
  1291. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  1292. else if (pp->speed == SPEED_100)
  1293. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  1294. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1295. } else {
  1296. /* Set phy address of the port */
  1297. mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
  1298. phydev = phy_connect(pp->bus, pp->phyaddr, dev,
  1299. pp->phy_interface);
  1300. if (!phydev) {
  1301. printf("phy_connect failed\n");
  1302. return -ENODEV;
  1303. }
  1304. pp->phydev = phydev;
  1305. phy_config(phydev);
  1306. phy_startup(phydev);
  1307. if (!phydev->link) {
  1308. printf("%s: No link.\n", phydev->dev->name);
  1309. return -1;
  1310. }
  1311. /* Full init on first call */
  1312. mvneta_init(dev);
  1313. pp->init = 1;
  1314. return 0;
  1315. }
  1316. }
  1317. /* Upon all following calls, this is enough */
  1318. mvneta_port_up(pp);
  1319. mvneta_port_enable(pp);
  1320. return 0;
  1321. }
  1322. static int mvneta_send(struct udevice *dev, void *packet, int length)
  1323. {
  1324. struct mvneta_port *pp = dev_get_priv(dev);
  1325. struct mvneta_tx_queue *txq = &pp->txqs[0];
  1326. struct mvneta_tx_desc *tx_desc;
  1327. int sent_desc;
  1328. u32 timeout = 0;
  1329. /* Get a descriptor for the first part of the packet */
  1330. tx_desc = mvneta_txq_next_desc_get(txq);
  1331. tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
  1332. tx_desc->data_size = length;
  1333. flush_dcache_range((ulong)packet,
  1334. (ulong)packet + ALIGN(length, PKTALIGN));
  1335. /* First and Last descriptor */
  1336. tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
  1337. mvneta_txq_pend_desc_add(pp, txq, 1);
  1338. /* Wait for packet to be sent (queue might help with speed here) */
  1339. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1340. while (!sent_desc) {
  1341. if (timeout++ > 10000) {
  1342. printf("timeout: packet not sent\n");
  1343. return -1;
  1344. }
  1345. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1346. }
  1347. /* txDone has increased - hw sent packet */
  1348. mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
  1349. return 0;
  1350. }
  1351. static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
  1352. {
  1353. struct mvneta_port *pp = dev_get_priv(dev);
  1354. int rx_done;
  1355. struct mvneta_rx_queue *rxq;
  1356. int rx_bytes = 0;
  1357. /* get rx queue */
  1358. rxq = mvneta_rxq_handle_get(pp, rxq_def);
  1359. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  1360. if (rx_done) {
  1361. struct mvneta_rx_desc *rx_desc;
  1362. unsigned char *data;
  1363. u32 rx_status;
  1364. /*
  1365. * No cache invalidation needed here, since the desc's are
  1366. * located in a uncached memory region
  1367. */
  1368. rx_desc = mvneta_rxq_next_desc_get(rxq);
  1369. rx_status = rx_desc->status;
  1370. if (!mvneta_rxq_desc_is_first_last(rx_status) ||
  1371. (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
  1372. mvneta_rx_error(pp, rx_desc);
  1373. /* leave the descriptor untouched */
  1374. return -EIO;
  1375. }
  1376. /* 2 bytes for marvell header. 4 bytes for crc */
  1377. rx_bytes = rx_desc->data_size - 6;
  1378. /* give packet to stack - skip on first 2 bytes */
  1379. data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
  1380. /*
  1381. * No cache invalidation needed here, since the rx_buffer's are
  1382. * located in a uncached memory region
  1383. */
  1384. *packetp = data;
  1385. /*
  1386. * Only mark one descriptor as free
  1387. * since only one was processed
  1388. */
  1389. mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
  1390. }
  1391. return rx_bytes;
  1392. }
  1393. static int mvneta_probe(struct udevice *dev)
  1394. {
  1395. struct eth_pdata *pdata = dev_get_plat(dev);
  1396. struct mvneta_port *pp = dev_get_priv(dev);
  1397. void *blob = (void *)gd->fdt_blob;
  1398. int node = dev_of_offset(dev);
  1399. struct mii_dev *bus;
  1400. unsigned long addr;
  1401. void *bd_space;
  1402. int ret;
  1403. int fl_node;
  1404. /*
  1405. * Allocate buffer area for descs and rx_buffers. This is only
  1406. * done once for all interfaces. As only one interface can
  1407. * be active. Make this area DMA safe by disabling the D-cache
  1408. */
  1409. if (!buffer_loc.tx_descs) {
  1410. u32 size;
  1411. /* Align buffer area for descs and rx_buffers to 1MiB */
  1412. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  1413. flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
  1414. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
  1415. DCACHE_OFF);
  1416. buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
  1417. size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
  1418. ARCH_DMA_MINALIGN);
  1419. memset(buffer_loc.tx_descs, 0, size);
  1420. buffer_loc.rx_descs = (struct mvneta_rx_desc *)
  1421. ((phys_addr_t)bd_space + size);
  1422. size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
  1423. ARCH_DMA_MINALIGN);
  1424. buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
  1425. }
  1426. pp->base = (void __iomem *)pdata->iobase;
  1427. /* Configure MBUS address windows */
  1428. if (device_is_compatible(dev, "marvell,armada-3700-neta"))
  1429. mvneta_bypass_mbus_windows(pp);
  1430. else
  1431. mvneta_conf_mbus_windows(pp);
  1432. /* PHY interface is already decoded in mvneta_of_to_plat() */
  1433. pp->phy_interface = pdata->phy_interface;
  1434. /* fetch 'fixed-link' property from 'neta' node */
  1435. fl_node = fdt_subnode_offset(blob, node, "fixed-link");
  1436. if (fl_node != -FDT_ERR_NOTFOUND) {
  1437. /* set phy_addr to invalid value for fixed link */
  1438. pp->phyaddr = PHY_MAX_ADDR + 1;
  1439. pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
  1440. pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
  1441. } else {
  1442. /* Now read phyaddr from DT */
  1443. addr = fdtdec_get_int(blob, node, "phy", 0);
  1444. addr = fdt_node_offset_by_phandle(blob, addr);
  1445. pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
  1446. }
  1447. bus = mdio_alloc();
  1448. if (!bus) {
  1449. printf("Failed to allocate MDIO bus\n");
  1450. return -ENOMEM;
  1451. }
  1452. bus->read = mvneta_mdio_read;
  1453. bus->write = mvneta_mdio_write;
  1454. snprintf(bus->name, sizeof(bus->name), dev->name);
  1455. bus->priv = (void *)pp;
  1456. pp->bus = bus;
  1457. ret = mdio_register(bus);
  1458. if (ret)
  1459. return ret;
  1460. #if CONFIG_IS_ENABLED(DM_GPIO)
  1461. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1462. &pp->phy_reset_gpio, GPIOD_IS_OUT);
  1463. if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
  1464. dm_gpio_set_value(&pp->phy_reset_gpio, 1);
  1465. mdelay(10);
  1466. dm_gpio_set_value(&pp->phy_reset_gpio, 0);
  1467. }
  1468. #endif
  1469. return board_network_enable(bus);
  1470. }
  1471. static void mvneta_stop(struct udevice *dev)
  1472. {
  1473. struct mvneta_port *pp = dev_get_priv(dev);
  1474. mvneta_port_down(pp);
  1475. mvneta_port_disable(pp);
  1476. }
  1477. static const struct eth_ops mvneta_ops = {
  1478. .start = mvneta_start,
  1479. .send = mvneta_send,
  1480. .recv = mvneta_recv,
  1481. .stop = mvneta_stop,
  1482. .write_hwaddr = mvneta_write_hwaddr,
  1483. };
  1484. static int mvneta_of_to_plat(struct udevice *dev)
  1485. {
  1486. struct eth_pdata *pdata = dev_get_plat(dev);
  1487. const char *phy_mode;
  1488. pdata->iobase = dev_read_addr(dev);
  1489. /* Get phy-mode / phy_interface from DT */
  1490. pdata->phy_interface = -1;
  1491. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1492. NULL);
  1493. if (phy_mode)
  1494. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1495. if (pdata->phy_interface == -1) {
  1496. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1497. return -EINVAL;
  1498. }
  1499. return 0;
  1500. }
  1501. static const struct udevice_id mvneta_ids[] = {
  1502. { .compatible = "marvell,armada-370-neta" },
  1503. { .compatible = "marvell,armada-xp-neta" },
  1504. { .compatible = "marvell,armada-3700-neta" },
  1505. { }
  1506. };
  1507. U_BOOT_DRIVER(mvneta) = {
  1508. .name = "mvneta",
  1509. .id = UCLASS_ETH,
  1510. .of_match = mvneta_ids,
  1511. .of_to_plat = mvneta_of_to_plat,
  1512. .probe = mvneta_probe,
  1513. .ops = &mvneta_ops,
  1514. .priv_auto = sizeof(struct mvneta_port),
  1515. .plat_auto = sizeof(struct eth_pdata),
  1516. };